 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 21-S3C2500B-032003 user's manual S3C2500B 32-bit risc microprocessor revision 1
S3C2500B 32-bit risc microprocessor user's manual revision 1 important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. S3C2500B risc microprocessor user's manual, revision 1.0 publication number: 21.0-s3-c2500b-052003 ? 2003 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microprocessor business has been awarded full iso-14001 certification (bsi certificate no. fm24653). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, kiheung-eup yongin-city, kyunggi-do, korea c.p.o. box #37, suwon 449-900 tel: (82)-(31)-209-2831 fax: (82)-(31)-209-3262 home-page url: http://www.samsungsemi.com printed in the republic of korea S3C2500B risc microcontroller iii table of contents chapter 1 product overview 1.1 overview ................................ ................................ ................................ ................................ ........... 1-1 1.2 features ................................ ................................ ................................ ................................ ............ 1-2 1.3 block diagram ................................ ................................ ................................ ................................ ... 1-5 1.4 package diagram ................................ ................................ ................................ .............................. 1-6 1.5 pin assignment ................................ ................................ ................................ ................................ .. 1-7 1.6 signal description ................................ ................................ ................................ .............................. 1-13 1.7 pad type ................................ ................................ ................................ ................................ ........... 1-31 1.8 special registers ................................ ................................ ................................ ............................... 1-32 chapter 2 programmer's model 2.1 overview ................................ ................................ ................................ ................................ ........... 2-1 2.2 switching state ................................ ................................ ................................ ................................ .. 2-1 2.2.1 entering thumb state ................................ ................................ ................................ ........... 2-1 2.2.2 entering arm state ................................ ................................ ................................ ................ 2-1 2.3 memory formats ................................ ................................ ................................ ................................ 2-2 2.3.1 big-endian format ................................ ................................ ................................ .................. 2-2 2.3.2 little-endian format ................................ ................................ ................................ ............... 2-2 2.4 instruction length ................................ ................................ ................................ .............................. 2-3 2.5 data types ................................ ................................ ................................ ................................ ........ 2-3 2.6 operating modes ................................ ................................ ................................ ............................... 2-3 2.7 registers ................................ ................................ ................................ ................................ ........... 2-4 2.7.3 the relationship between arm and thumb state registers ................................ ................. 2-7 2.7.4 accessing hi-registers in thumb state ................................ ................................ ................. 2-8 2.8 the program status registers ................................ ................................ ................................ ........... 2-8 2.8.1 the condition code flags ................................ ................................ ................................ ...... 2-9 2.8.2 the control bits ................................ ................................ ................................ ...................... 2-9 2.9 exceptions ................................ ................................ ................................ ................................ ......... 2-11 2.9.1 action on entering an exception ................................ ................................ ............................. 2-11 2.9.2 action on leaving an exception ................................ ................................ .............................. 2-11 2.9.3 exception entry/exit summary ................................ ................................ ............................... 2-12 2.9.4 fiq ................................ ................................ ................................ ................................ ......... 2-12 2.9.5 irq ................................ ................................ ................................ ................................ ......... 2-13 2.9.6 abort ................................ ................................ ................................ ................................ ...... 2-13 2.9.7 software interrupt ................................ ................................ ................................ ................... 2-14 2.9.8 undefined instruction ................................ ................................ ................................ .............. 2-14 2.10 exception vectors ................................ ................................ ................................ ............................ 2-14 2.10.1 exception priorities ................................ ................................ ................................ ............... 2-15 2.10.2 not all exceptions can occur at once: ................................ ................................ ................ 2-15 2.11 interrupt latencies ................................ ................................ ................................ ........................... 2-16 2.12 reset ................................ ................................ ................................ ................................ ............... 2-16 2.13 introduction for arm940t ................................ ................................ ................................ ................ 2-17 2.14 arm940t block diagram ................................ ................................ ................................ ................. 2-18 2.15 about the arm940t programmer's model ................................ ................................ ...................... 2-19 2.15.1 data abort model ................................ ................................ ................................ .................. 2-20 2.15.2 instruction set extension spaces ................................ ................................ .......................... 2-20 2.16 arm940t cp15 registers ................................ ................................ ................................ ............... 2-21 2.16.1 cp15 register map summary ................................ ................................ .............................. 2-21 iv iv S3C2500B risc microcontroller table of contents (continued) chapter 3 instruction set 3.1 instruction set summay ................................ ................................ ................................ .................... 3-1 3.1.1 format summary ................................ ................................ ................................ ................... 3-1 3.1.2 instruction summary ................................ ................................ ................................ .............. 3-2 3.2 the condition field ................................ ................................ ................................ ........................... 3-4 3.3 branch and exchange (bx) ................................ ................................ ................................ ............... 3-5 3.3.1 instruction cycle times ................................ ................................ ................................ .......... 3-5 3.3.2 assembler syntax ................................ ................................ ................................ .................. 3-5 3.3.3 using r15 as an operand ................................ ................................ ................................ ...... 3-5 3.4 branch and branch with link (b, bl) ................................ ................................ ................................ . 3-7 3.4.1 the link bit ................................ ................................ ................................ ........................... 3-7 3.4.2 instruction cycle times ................................ ................................ ................................ .......... 3-7 3.4.3 assembler syntax ................................ ................................ ................................ .................. 3-8 3.5 data processing ................................ ................................ ................................ ................................ 3-9 3.5.1 cpsr flags ................................ ................................ ................................ ........................... 3-11 3.5.2 shifts ................................ ................................ ................................ ................................ ..... 3-12 3.5.3 immediate operand rotates ................................ ................................ ................................ .. 3-16 3.5.4 writing to r15 ................................ ................................ ................................ ........................ 3-16 3.5.5 using r15 as an operand ................................ ................................ ................................ ...... 3-16 3.5.6 teq, tst, cmp and cmn opcodes ................................ ................................ ......................... 3-16 3.5.7 instruction cycle times ................................ ................................ ................................ .......... 3-17 3.6.8 assembler syntax ................................ ................................ ................................ .................. 3-17 3.6 psr transfer (mrs, msr) ................................ ................................ ................................ ............... 3-19 3.6.1 operand restrictions ................................ ................................ ................................ ............. 3-19 3.6.2 reserved bits ................................ ................................ ................................ ........................ 3-21 3.6.3 instruction cycle times ................................ ................................ ................................ .......... 3-21 3.6.4 assembler syntax ................................ ................................ ................................ .................. 3-22 3.7 multiply and multiply-accumulate (mul, mla) ................................ ................................ .................. 3-23 3.7.1 cpsr flags ................................ ................................ ................................ ........................... 3-24 3.7.2 instruction cycle times ................................ ................................ ................................ .......... 3-24 3.7.3 assembler syntax ................................ ................................ ................................ .................. 3-24 3.8 multiply long and multiply-accumulate long (mull, mlal) ................................ ............................. 3-25 3.8.1 operand restrictions ................................ ................................ ................................ ............. 3-25 3.8.2 cpsr flags ................................ ................................ ................................ ........................... 3-26 3.8.3 instruction cycle times ................................ ................................ ................................ .......... 3-26 3.8.4 assembler syntax ................................ ................................ ................................ .................. 3-27 3.9 single data transfer (ldr, str) ................................ ................................ ................................ ...... 3-28 3.9.1 offsets and auto-indexing ................................ ................................ ................................ ..... 3-29 3.9.2 shifted register offset ................................ ................................ ................................ ........... 3-29 3.9.3 bytes and words ................................ ................................ ................................ ................... 3-29 3.9.4 use of r15 ................................ ................................ ................................ ............................. 3-31 3.9.5 restriction on the use of base register ................................ ................................ ................. 3-31 3.9.6 data aborts ................................ ................................ ................................ ............................ 3-31 3.9.7 instruction cycle times ................................ ................................ ................................ .......... 3-31 3.9.8 assembler syntax ................................ ................................ ................................ .................. 3-32 S3C2500B risc microcontroller v table of contents (continued) chapter 3 instruction set (continued) 3.10 halfword and signed data transfer (ldrh/strh/ldrsb/ldrsh) ................................ ................. 3-34 3.10.1 offsets and auto-indexing ................................ ................................ ................................ .... 3-35 3.10.2 half-word load and stores ................................ ................................ ................................ .. 3-36 3.10.3 signed byte and half-word loads ................................ ................................ ........................ 3-36 3.10.4 endianness and byte/half-word selection ................................ ................................ ............ 3-36 3.10.5 use of r15 ................................ ................................ ................................ ........................... 3-37 3.10.6 data aborts ................................ ................................ ................................ ........................... 3-37 3.10.7 instruction cycle times ................................ ................................ ................................ ........ 3-37 3.10.8 assembler syntax ................................ ................................ ................................ ................. 3-38 3.11 block data transfer (ldm, stm) ................................ ................................ ................................ ..... 3-40 3.11.1 the register list ................................ ................................ ................................ ................... 3-40 3.11.2 addressing modes ................................ ................................ ................................ ................ 3-41 3.11.3 address alignment ................................ ................................ ................................ ................ 3-41 3.11.4 use of the s bit ................................ ................................ ................................ .................... 3-43 3.11.5 use of r15 as the base ................................ ................................ ................................ ........ 3-43 3.11.6 inclusion of the base in the register list ................................ ................................ ............... 3-44 3.11.7 data aborts ................................ ................................ ................................ ........................... 3-44 3.11.8 instruction cycle times ................................ ................................ ................................ ........ 3-44 3.11.9 assembler syntax ................................ ................................ ................................ ................. 3-45 3.12 single data swap (swp) ................................ ................................ ................................ ................. 3-47 3.12.1 bytes and words ................................ ................................ ................................ .................. 3-47 3.12.2 use of r15 ................................ ................................ ................................ ........................... 3-47 3.12.3 data aborts ................................ ................................ ................................ ........................... 3-48 3.12.4 instruction cycle times ................................ ................................ ................................ ........ 3-48 3.12.5 assembler syntax ................................ ................................ ................................ ................. 3-48 3.13 software interrupt (swi) ................................ ................................ ................................ .................. 3-49 3.13.1 return from the supervisor ................................ ................................ ................................ ... 3-49 3.13.2 comment field ................................ ................................ ................................ ..................... 3-49 3.13.3 instruction cycle times ................................ ................................ ................................ ........ 3-49 3.13.4 assembler syntax ................................ ................................ ................................ ................. 3-50 3.14 coprocessor data operations (cdp) ................................ ................................ ................................ 3-51 3.14.1 coprocessor instructions ................................ ................................ ................................ ....... 3-51 3.14.2 the coprocessor fields ................................ ................................ ................................ ........ 3-51 3.14.3 instruction cycle times ................................ ................................ ................................ ........ 3-52 3.14.4 assembler syntax ................................ ................................ ................................ ................. 3-52 3.15 coprocessor data transfers (ldc, stc) ................................ ................................ ......................... 3-53 3.15.1 the coprocessor fields ................................ ................................ ................................ ........ 3-53 3.15.2 addressing modes ................................ ................................ ................................ ................ 3-54 3.15.3 address alignment ................................ ................................ ................................ ................ 3-54 3.15.4 use of r15 ................................ ................................ ................................ ........................... 3-54 3.15.5 data aborts ................................ ................................ ................................ ........................... 3-54 3.15.6 instruction cycle times ................................ ................................ ................................ ........ 3-54 3.15.7 assembler syntax ................................ ................................ ................................ ................. 3-55 vi vi S3C2500B risc microcontroller table of contents (continued) chapter 3 instruction set (continued) 3.16 coprocessor register transfers (mrc, mcr) ................................ ................................ ................. 3-56 3.16.1 the coprocessor fields ................................ ................................ ................................ ....... 3-56 3.16.2 transfers to r15 ................................ ................................ ................................ .................. 3-57 3.16.3 transfers from r15 ................................ ................................ ................................ .............. 3-57 3.16.4 instruction cycle times ................................ ................................ ................................ ........ 3-57 3.16.5 assembler syntax ................................ ................................ ................................ ................ 3-57 3.17 undefined instruction ................................ ................................ ................................ ...................... 3-58 3.17.1 instruction cycle times ................................ ................................ ................................ ........ 3-58 3.17.2 assembler syntax ................................ ................................ ................................ ................ 3-58 3.18 instruction set examples ................................ ................................ ................................ ................. 3-59 3.18.1 using the conditional instructions ................................ ................................ ....................... 3-59 3.18.2 pseudo-random binary sequence generator ................................ ................................ ...... 3-61 3.18.3 multiplication by constant using the barrel shifter ................................ .............................. 3-61 3.18.4 loading a word from an unknown alignment ................................ ................................ ..... 3-63 3.19 thumb instruction set format ................................ ................................ ................................ ......... 3-64 3.19.1 format summary ................................ ................................ ................................ ................. 3-64 3.19.2 opcode summary ................................ ................................ ................................ ................ 3-65 3.20 format 1: move shifted register ................................ ................................ ................................ ..... 3-67 3.20.1 operation ................................ ................................ ................................ ............................. 3-67 3.20.2 instruction cycle times ................................ ................................ ................................ ........ 3-67 3.21 format 2: add/subtract ................................ ................................ ................................ ................... 3-68 3.21.1 operation ................................ ................................ ................................ ............................. 3-68 3.21.2 instruction cycle times ................................ ................................ ................................ ........ 3-69 3.22 format 3: move/compare/add/subtract immediate ................................ ................................ ......... 3-70 3.22.1 operations ................................ ................................ ................................ ........................... 3-70 3.22.2 instruction cycle times ................................ ................................ ................................ ........ 3-70 3.23 format 4: alu operations ................................ ................................ ................................ .............. 3-71 3.23.1 operation ................................ ................................ ................................ ............................. 3-71 3.23.2 instruction cycle times ................................ ................................ ................................ ........ 3-72 3.24 format 5: hi-register operations/branch exchange ................................ ................................ ....... 3-73 3.24.1 operation ................................ ................................ ................................ ............................. 3-73 3.24.2 instruction cycle times ................................ ................................ ................................ ........ 3-74 3.24.3 the bx instruction ................................ ................................ ................................ ................ 3-74 3.24.4 using r15 as an operand ................................ ................................ ................................ .... 3-75 3.25 format 6: pc-relative load ................................ ................................ ................................ ............ 3-76 3.25.1 operation ................................ ................................ ................................ ............................. 3-76 3.25.2 instruction cycle times ................................ ................................ ................................ ........ 3-76 3.26 format 7: load/store with register offset ................................ ................................ ...................... 3-77 3.26.1 operation ................................ ................................ ................................ ............................. 3-77 3.26.2 instruction cycle times ................................ ................................ ................................ ........ 3-78 3.27 format 8: load/store sign-extended byte/half-word ................................ ................................ ..... 3-79 3.27.1 operation ................................ ................................ ................................ ............................. 3-79 3.27.2 instruction cycle times ................................ ................................ ................................ ........ 3-80 S3C2500B risc microcontroller vii table of contents (continued) chapter 3 instruction set (continued) 3.28 format 9: load/store with immediate offset ................................ ................................ .................... 3-81 3.28.1 operation ................................ ................................ ................................ .............................. 3-81 3.28.2 instruction cycle times ................................ ................................ ................................ ........ 3-82 3.29 format 10: load/store half-word ................................ ................................ ................................ .... 3-83 3.29.1 operation ................................ ................................ ................................ .............................. 3-83 3.29.2 instruction cycle times ................................ ................................ ................................ ........ 3-83 3.30 format 11: sp-relative load/store ................................ ................................ ................................ . 3-84 3.30.1 operation ................................ ................................ ................................ .............................. 3-84 3.30.2 instruction cycle times ................................ ................................ ................................ ........ 3-84 3.31 format 12: load addres ................................ ................................ ................................ ................... 3-85 3.31.1 operation ................................ ................................ ................................ .............................. 3-85 3.31.2 instruction cycle times ................................ ................................ ................................ ........ 3-86 3.32 format 13: add offset to stack pointer ................................ ................................ ............................ 3-87 3.32.1 operation ................................ ................................ ................................ .............................. 3-87 3.32.2 instruction cycle times ................................ ................................ ................................ ........ 3-87 3.33 format 14: push/pop registers ................................ ................................ ................................ ........ 3-88 3.33.1 operation ................................ ................................ ................................ .............................. 3-88 3.33.2 instruction cycle times ................................ ................................ ................................ ........ 3-89 3.34 format 15: multiple load/store ................................ ................................ ................................ ........ 3-90 3.34.1 operation ................................ ................................ ................................ .............................. 3-90 3.34.2 instruction cycle times ................................ ................................ ................................ ........ 3-90 3.35 format 16: conditional branch ................................ ................................ ................................ ......... 3-91 3.35.1 operation ................................ ................................ ................................ .............................. 3-91 3.35.2 instruction cycle times ................................ ................................ ................................ ........ 3-92 3.36 format 17: software interrupt ................................ ................................ ................................ .......... 3-93 3.36.1 operation ................................ ................................ ................................ .............................. 3-93 3.36.2 instruction cycle times ................................ ................................ ................................ ........ 3-93 3.37 format 18: unconditional branch ................................ ................................ ................................ ..... 3-94 3.37.1 operation ................................ ................................ ................................ .............................. 3-94 3.38 format 19: long branch with link ................................ ................................ ................................ ... 3-95 3.38.1 operation ................................ ................................ ................................ .............................. 3-95 3.38.2 instruction cycle times ................................ ................................ ................................ ........ 3-96 3.39 instruction set examples ................................ ................................ ................................ ................. 3-97 3.39.1 multiplication by a constant using shifts and adds ................................ ............................... 3-97 3.39.2 general purpose signed divide ................................ ................................ ............................ 3-98 3.39.3 division by a constant ................................ ................................ ................................ .......... 3-100 viii viii S3C2500B risc microcontroller table of contents (continued) chapter 4 system configuration 4.1 overview ................................ ................................ ................................ ................................ .......... 4-1 4.2 features ................................ ................................ ................................ ................................ ............ 4-1 4.3 address map ................................ ................................ ................................ ................................ ..... 4-2 4.4 remap of memory space ................................ ................................ ................................ ................. 4-3 4.5 external address translation ................................ ................................ ................................ ............ 4- 3 4.6 arbitration scheme ................................ ................................ ................................ ........................... 4- 4 4.6.1 problem solvings with programmable round-robin ................................ .............................. 4- 7 4.7 clock configuration ................................ ................................ ................................ ........................... 4- 9 4.8 external bus master ................................ ................................ ................................ .......................... 4-14 4.9 system configuration special registers ................................ ................................ ............................ 4- 15 4.9.1 system configuration register ................................ ................................ ............................... 4- 16 4.9.2 product code and revision number register ................................ ................................ ........ 4- 18 4.9.3 clock control register ................................ ................................ ................................ ........... 4- 19 4.9.4 peripheral clock disable register ................................ ................................ .......................... 4- 20 4.9.5 clock status register ................................ ................................ ................................ ............ 4- 21 4.9.6 ahb bus master priority register ................................ ................................ .......................... 4- 21 4.9.7 core pll control register ................................ ................................ ................................ ..... 4- 22 4.9.8 system bus pll control register ................................ ................................ .......................... 4- 23 4.9.9 usb pll control register ................................ ................................ ................................ ..... 4- 24 4.9.10 phy pll control register ................................ ................................ ................................ .... 4- 24 chapter 5 memory controller 5.1 overview ................................ ................................ ................................ ................................ .......... 5-1 5.2 features ................................ ................................ ................................ ................................ ............ 5-2 5.3 memory map ................................ ................................ ................................ ................................ ..... 5-3 5.4 bus interface signals ................................ ................................ ................................ ........................ 5-5 5.5 endian modes ................................ ................................ ................................ ................................ ... 5-7 5.6 ext i/o bank controller ................................ ................................ ................................ ..................... 5-13 5.6.1 features ................................ ................................ ................................ ................................ 5-13 5.6.2 external device connection ................................ ................................ ................................ ... 5-14 5.6.3 ext. i/o bank controller special register ................................ ................................ ............... 5-21 5.6.4 timing diagram ................................ ................................ ................................ ..................... 5-29 5.7 sdram controller ................................ ................................ ................................ ............................ 5-38 5.7.1 features ................................ ................................ ................................ ................................ 5-38 5.7.2 sdram size and configuration ................................ ................................ ............................. 5-39 5.7.3 address mapping ................................ ................................ ................................ ................... 5-42 5.7.4 sdram commands ................................ ................................ ................................ ............... 5-44 5.7.5 external data bus width ................................ ................................ ................................ ........ 5-45 5.7.6 merging write buffer ................................ ................................ ................................ ............. 5-45 5.7.7 self refresh ................................ ................................ ................................ ........................... 5-45 5.7.8 basic operation ................................ ................................ ................................ ..................... 5-46 5.7.9 sdram special registers ................................ ................................ ................................ ..... 5-47 5.7.10 sdram controller timing ................................ ................................ ................................ .... 5-54 S3C2500B risc microcontroller ix table of contents (continued) chapter 6 i 2 c controller 6.1 overview ................................ ................................ ................................ ................................ ........... 6-1 6.2 features ................................ ................................ ................................ ................................ ............ 6-1 6.3 functional description ................................ ................................ ................................ ....................... 6-2 6.4 i 2 c concepts ................................ ................................ ................................ ................................ ..... 6-3 6.4.1 basic operation ................................ ................................ ................................ ...................... 6-3 6.4.2 general characteristics ................................ ................................ ................................ .......... 6-4 6.4.3 bit transfers ................................ ................................ ................................ ........................... 6-4 6.4.4 data validity ................................ ................................ ................................ ........................... 6-5 6.4.5 start and stop conditions ................................ ................................ ................................ ....... 6-5 6.4.6 data trsansfer operations ................................ ................................ ................................ ...... 6-6 6.5 i 2 c special registers ................................ ................................ ................................ ......................... 6-9 6.5.1 control status register ................................ ................................ ................................ ........... 6-9 6.5.2 shift buffer register ................................ ................................ ................................ ............... 6-11 6.5.3 prescaler register ................................ ................................ ................................ .................. 6-11 6.5.4 prescaler counter register ................................ ................................ ................................ ..... 6-12 6.5.5 interrupt pending register ................................ ................................ ................................ ...... 6-12 chapter 7 ethernet controller 7.1 overview ................................ ................................ ................................ ................................ ........... 7-1 7.2 features ................................ ................................ ................................ ................................ ............ 7-2 7.3 mac function blocks ................................ ................................ ................................ ......................... 7-3 7.3.1 media independent interface (mii) ................................ ................................ .......................... 7-3 7.3.2 physical layer entity (phy) ................................ ................................ ................................ .... 7-4 7.3.3 buffered dma interface (bdi) ................................ ................................ ................................ . 7-4 7.3.4 the mac transmitter block ................................ ................................ ................................ .... 7-4 7.3.5 the mac receiver block ................................ ................................ ................................ ........ 7-6 7.3.6 flow control block ................................ ................................ ................................ .................. 7-7 7.3.7 buffered dma (bdma) overview ................................ ................................ ........................... 7-7 7.4 ethernet controller special registers ................................ ................................ ................................ . 7-13 7.4.1 bdma relative special register ................................ ................................ ............................ 7-15 7.4.2 mac relative special register ................................ ................................ ............................... 7-24 7.5 ethernet operations ................................ ................................ ................................ ........................... 7-37 7.5.1 mac frame format ................................ ................................ ................................ ................ 7-37 7.5.2 the mii station manager ................................ ................................ ................................ ........ 7-45 7.5.3 full-duplex pause operations ................................ ................................ ................................ 7-46 7.5.4 error signalling ................................ ................................ ................................ ....................... 7-48 7.5.5 timing parameters for mii transactions ................................ ................................ ................. 7-50 x x S3C2500B risc microcontroller table of contents (continued) chapter 8 hdlc controller 8.1 overview ................................ ................................ ................................ ................................ .......... 8-1 8.2 features ................................ ................................ ................................ ................................ ............ 8-2 8.3 function descriptions ................................ ................................ ................................ ........................ 8-3 8.3.1 hdlc frame format ................................ ................................ ................................ ............. 8-4 8.4 protocol features ................................ ................................ ................................ .............................. 8-6 8.4.1 invalid frame ................................ ................................ ................................ ........................ 8-6 8.4.2 zero insertion and zero deletion ................................ ................................ ............................ 8-6 8.4.3 abort ................................ ................................ ................................ ................................ ...... 8-6 8.4.4 idle and time fill ................................ ................................ ................................ ................... 8-6 8.4.5 fifo structure ................................ ................................ ................................ ....................... 8-7 8.4.6 two-channel dma engine ................................ ................................ ................................ ..... 8-7 8.4.7 baud rate generator ................................ ................................ ................................ ............. 8-7 8.4.8 digital phase-locked loop (dpll) ................................ ................................ ........................ 8-9 8.4.9 clock usage method ................................ ................................ ................................ .............. 8-9 8.5 hdlc operational description ................................ ................................ ................................ .......... 8-11 8.5.1 hdlc initialization ................................ ................................ ................................ ................. 8-11 8.5.2 hdlc data encoding/decoding ................................ ................................ ............................. 8-12 8.5.3 hdlc data setup and hold timing with clock ................................ ................................ ....... 8-13 8.5.4 hdlc transmitter operation ................................ ................................ ................................ . 8-14 8.5.5 hdlc receiver operation ................................ ................................ ................................ ..... 8-16 8.5.6 hardware flow control ................................ ................................ ................................ .......... 8-17 8.5.7 memory data structure ................................ ................................ ................................ .......... 8-19 8.5.8 data buffer descriptor ................................ ................................ ................................ ........... 8-20 8.6 buffer descriptor ................................ ................................ ................................ ............................... 8-21 8.6.1 transmit buffer descriptor ................................ ................................ ................................ ..... 8-21 8.6.2 receive buffer descriptor ................................ ................................ ................................ ...... 8-22 8.7 hdlc special registers ................................ ................................ ................................ .................... 8-24 8.7.1 hdlc global mode register ................................ ................................ ................................ .. 8-27 8.7.2 hdlc control register ................................ ................................ ................................ .......... 8-30 8.7.3 hdlc status register ................................ ................................ ................................ ........... 8-36 8.7.4 summary ................................ ................................ ................................ ............................... 8-36 8.7.5 hdlc interrupt enable register ................................ ................................ ............................. 8-42 8.7.6 hdlc tx fifo ................................ ................................ ................................ ......................... 8-44 8.7.7 hdlc rx fifo ................................ ................................ ................................ ........................ 8-45 8.7.8 hdlc brg time constant registers ................................ ................................ ....................... 8-46 8.7.9 hdlc preamble constant register ................................ ................................ ........................ 8-47 8.7.10 hdlc station address registers and hmask register ................................ ......................... 8-48 8.7.11 dma tx buffer descriptor pointer register ................................ ................................ .......... 8-49 8.7.12 dma rx buffer descriptor pointer register ................................ ................................ .......... 8-50 8.7.13 maximum frame length register ................................ ................................ ........................ 8-50 8.7.14 receive buffer size register ................................ ................................ ............................... 8-51 8.7.15 synchronization register ................................ ................................ ................................ ..... 8-51 8.7.16 transparent control register ................................ ................................ ............................... 8-52 8.7.17 tx buffer descriptor count register ................................ ................................ ..................... 8-53 8.7.18 rx buffer descriptor count register ................................ ................................ .................... 8-53 8.7.19 tx buffer descriptor maximum count register ................................ ................................ .... 8-54 8.7.20 rx buffer descriptor maximum count register ................................ ................................ .... 8-54 S3C2500B risc microcontroller xi table of contents (continued) chapter 9 iom2 & tsa controller 9.1 overview ................................ ................................ ................................ ................................ ........... 9-1 9.2 features ................................ ................................ ................................ ................................ ............ 9-1 9.3 iom2 bus ................................ ................................ ................................ ................................ ........... 9-2 9.3.1 b channels ................................ ................................ ................................ ............................. 9-3 9.3.2 d channel ................................ ................................ ................................ .............................. 9- 3 9.3.3 monitor channels ................................ ................................ ................................ .................... 9-3 9.3.4 command and indicate channels ................................ ................................ ........................... 9-3 9.3.5 intercommunication channels ................................ ................................ ................................ . 9-3 9.3.6 tic bus ................................ ................................ ................................ ................................ .. 9-3 9.3.7 channel operation ................................ ................................ ................................ .................. 9-4 9.4 tsa (time slot assigner) ................................ ................................ ................................ .................. 9-9 9.4.1 overview ................................ ................................ ................................ ................................ 9-9 9.4.2 tsa block diagram ................................ ................................ ................................ ................ 9-9 9.4.3 hdlc external pin multiplexed signals ................................ ................................ .................. 9-10 9.4.4 operation ................................ ................................ ................................ ............................... 9-10 9.5 iom2 special registers ................................ ................................ ................................ ..................... 9-11 9.5.1 iom2con register ................................ ................................ ................................ ................. 9-12 9.5.2 iom2 status register ................................ ................................ ................................ ............. 9-14 9.5.3 iom2 interrupt enable register ................................ ................................ .............................. 9-16 9.5.4 iom2 tic bus address register ................................ ................................ ............................. 9-18 9.5.5 iom2 ic channel transmit data register ................................ ................................ ............... 9-19 9.5.6 iom2 c/i0 channel transmit data register ................................ ................................ ............ 9-20 9.5.7 iom2 c/i1 channel transmit data register ................................ ................................ ............ 9-21 9.5.8 iom2 c/i1 channel receive data register ................................ ................................ ............. 9-21 9.5.9 iom2 monitor channel transmit data register ................................ ................................ ....... 9-22 9.5.10 iom2 monitor channel receive data register ................................ ................................ ...... 9-22 9.5.11 tsa a control register ................................ ................................ ................................ ......... 9-23 9.5.12 tsa b control register ................................ ................................ ................................ ......... 9-24 9.5.13 tsa c control register ................................ ................................ ................................ ........ 9-25 9.5.14 iom2strb (strobe register) ................................ ................................ ............................... 9-26 xii xii S3C2500B risc microcontroller table of contents (continued) chapter 10 usb control ler 10.1 overview ................................ ................................ ................................ ................................ ........ 10-1 10.2 features ................................ ................................ ................................ ................................ .......... 10-2 10.3 function descriptions ................................ ................................ ................................ ...................... 10-3 10.3.1 usb bus topology and physical connection ................................ ................................ ....... 10-3 10.3.2 frame generation ................................ ................................ ................................ ................ 10-3 10.3.3 packet formats ................................ ................................ ................................ .................... 10-4 10.3.4 bit stuffing and nrzi coding ................................ ................................ ............................... 10-5 10.3.5 bulk transactions ................................ ................................ ................................ ................ 10-5 10.3.6 control transactions ................................ ................................ ................................ ............ 10-6 10.3.7 isochronous transactions ................................ ................................ ................................ .... 10-6 10.3.8 interrupt transactions ................................ ................................ ................................ .......... 10-6 10.4 usb block descriptions ................................ ................................ ................................ .................. 10-7 10.4.1 usb block overview ................................ ................................ ................................ ........... 10-7 10.4.2 sie (serial interface engine) block ................................ ................................ ...................... 10-7 10.5 usb special registers ................................ ................................ ................................ .................... 10-9 10.5.1 usb function address register ................................ ................................ ........................... 10-10 10.5.2 usb power management register ................................ ................................ ....................... 10-12 10.5.3 usb interrupt register ................................ ................................ ................................ ......... 10-14 10.5.4 usb interrupt enable register ................................ ................................ ............................. 10-17 10.5.5 usb frame number register ................................ ................................ .............................. 10-19 10.5.6 usb disconnect timer register ................................ ................................ ........................... 10-20 10.5.7 usb endpoint 0 common status register ................................ ................................ ........... 10-22 10.5.8 usb endpoint 1 common status register ................................ ................................ ........... 10-25 10.5.9 usb endpoint 2 common status register ................................ ................................ ........... 10-30 10.5.10 usb endpoint 3 common status register ................................ ................................ ......... 10-35 10.5.11 usb endpoint 4 common status register ................................ ................................ ......... 10-40 10.5.12 usb write count for endpoint 0 register ................................ ................................ ........... 10-45 10.5.13 usb write count for endpoint 1 register ................................ ................................ ........... 10-47 10.5.14 usb write count for endpoint 2 register ................................ ................................ ........... 10-49 10.5.15 usb write count for endpoint 3 register ................................ ................................ ........... 10-51 10.5.16 usb write count for endpoint 4 register ................................ ................................ ........... 10-53 10.5.17 usb endpoint 0/1/2/3/4 fifo register ................................ ................................ ............... 10-55 S3C2500B risc microcontroller xiii table of contents (continued) chapter 11 des/3des 11.1 overview ................................ ................................ ................................ ................................ ......... 11-1 11.2 feature ................................ ................................ ................................ ................................ ............ 11-1 11.3 des/3des special registers ................................ ................................ ................................ ........... 11-3 11.3.1 des/3des control register ................................ ................................ ................................ . 11-4 11.3.2 des/3des status register ................................ ................................ ................................ ... 11-5 11.3.3 des/3des interrupt enable register ................................ ................................ .................... 11-6 11.3.4 des/3des run enable register ................................ ................................ ........................... 11-6 11.3.5 des/3des key1 left/right side register ................................ ................................ ............. 11-6 11.3.6 des/3des key 2 left/right side register ................................ ................................ ............ 11-7 11.3.7 des/3des key 3 left side register ................................ ................................ ..................... 11-7 11.3.8 des/3des iv left/right side register ................................ ................................ ................. 11-7 11.3.9 des/3des input/output data fifo register ................................ ................................ ........ 11-8 11.4 des/3des operation ................................ ................................ ................................ ....................... 11-9 11.5 performance calculation guide ................................ ................................ ................................ ....... 11-10 chapter 12 gdma controller 12.1 overview ................................ ................................ ................................ ................................ ......... 12-1 12.2 feature ................................ ................................ ................................ ................................ ............ 12-1 12.3 gdma special registers ................................ ................................ ................................ .................. 1 2-3 12.3.1 gdma programmable priority registers ................................ ................................ ............... 12-4 12.3.2 gdma control registers ................................ ................................ ................................ ....... 12-9 12.3.3 gdma source/destination address registers ................................ ................................ ....... 12-12 12.3.4 gdma transfer count registers ................................ ................................ ........................... 12-13 12.3.5 gdma run enable registers ................................ ................................ ................................ 12-14 12.3.6 gdma interrupt pending register ................................ ................................ ......................... 12-15 12.4 gdma mode operation ................................ ................................ ................................ .................... 12-16 12.4.1 software mode ................................ ................................ ................................ ..................... 12-16 12.4.2 external gdma request mode ................................ ................................ ............................. 12-16 12.4.3 huart mode ................................ ................................ ................................ ....................... 12-16 12.4.4 des mode ................................ ................................ ................................ ............................ 12-17 12.5 gdma function description ................................ ................................ ................................ ............. 12-17 12.5.1 gdma transfers ................................ ................................ ................................ ................... 12-17 12.5.2 starting/ending gdma transfers ................................ ................................ .......................... 12-17 12.5.3 data transfer modes ................................ ................................ ................................ ............ 12-18 12.6 gdma transfer timing data ................................ ................................ ................................ ............ 12-19 12.6.1 single and one data burst mode ................................ ................................ .......................... 12-20 12.6.2 single and four data burst mode ................................ ................................ ......................... 12-21 12.6.3 block and one data burst mode ................................ ................................ ........................... 12-22 12.6.4 block and four data burst ................................ ................................ ................................ .... 12-23 xiv xiv S3C2500B risc microcontroller table of contents (continued) chapter 13 serial i/o (console uart) 13.1 overview ................................ ................................ ................................ ................................ ........ 13-1 13.2 features ................................ ................................ ................................ ................................ .......... 13-1 13.3 console uart special registers ................................ ................................ ................................ .... 13-3 13.3.1 console uart control registers ................................ ................................ ......................... 13-4 13.3.2 console uart status registers ................................ ................................ .......................... 13-8 13.3.3 console uart interrupt enable register ................................ ................................ ............. 13-11 13.3.4 uart transmit data register ................................ ................................ .............................. 13-13 13.3.5 uart receive data register ................................ ................................ ............................... 13-14 13.3.6 uart baud rate divisor register ................................ ................................ ....................... 13-15 13.3.7 console uart baud rate examples ................................ ................................ ................... 13-16 13.3.8 uart control character register 1 and 2 ................................ ................................ ............ 13-17 chapter 14 serial i/o (high-speed uart) 14.1 overview ................................ ................................ ................................ ................................ ........ 14-1 14.2 features ................................ ................................ ................................ ................................ .......... 14-1 14.3 high-speed uart special registers ................................ ................................ .............................. 14-3 14.3.1 high-speed uart control registers ................................ ................................ ................... 14-4 14.3.2 high-speed uart status registers ................................ ................................ ..................... 14-9 14.3.3 high-speed uart interrupt enable register ................................ ................................ ....... 14-14 14.3.4 high-speed uart transmit buffer register ................................ ................................ ........ 14-16 14.3.5 high-speed uart receive buffer register ................................ ................................ ......... 14-17 14.3.6 high-speed uart baud rate divisor register ................................ ................................ .... 14-18 14.3.7 high-speed uart baud rate examples ................................ ................................ ............. 14-19 14.3.8 high-speed uart control character 1 register ................................ ................................ .. 14-20 14.3.9 high-speed uart control character 2 register ................................ ................................ .. 14-21 14.3.10 high-speed uart autoband boundary register ................................ ................................ 14-22 14.3.11 high-speed uart autobaud table regsiter ................................ ................................ ...... 14-23 14.4 high-speed uart operation ................................ ................................ ................................ .......... 14-24 14.4.1 fifo operation ................................ ................................ ................................ .................... 14-24 14.4.2 hardware flow control ................................ ................................ ................................ ......... 14-24 14.4.3 software flow control ................................ ................................ ................................ .......... 14-26 14.4.4 auto baud rate detection ................................ ................................ ................................ .... 14-26 chapter 15 i/o ports 15.1 overview ................................ ................................ ................................ ................................ ........ 15-1 15.2 features ................................ ................................ ................................ ................................ .......... 15-1 15.3 i/o port special register ................................ ................................ ................................ ................. 15-2 15.3.1 i/o port mode select register ................................ ................................ .............................. 15-3 15.3.2 i/o port function control register ................................ ................................ ....................... 15-5 15.3.3 i/o port control register for gdma ................................ ................................ ..................... 15-8 15.3.4 i/o port control register for external interrupt ................................ ................................ ..... 15-9 15.3.5 i/o port external interrupt clear register ................................ ................................ ............. 15-11 15.3.6 i/o port data register ................................ ................................ ................................ .......... 15-12 15.3.7 i/o port drive control register ................................ ................................ ............................ 15-12 S3C2500B risc microcontroller xv table of contents (concluded) chapter 16 interrupt controller 16.1 overview ................................ ................................ ................................ ................................ ......... 16-1 16.2 features ................................ ................................ ................................ ................................ .......... 16-1 16.3 interrupt sources ................................ ................................ ................................ ............................. 16-2 16.4 interrupt controller special registers ................................ ................................ ............................... 16-3 16.4.1 interrupt mode registers ................................ ................................ ................................ ....... 16-3 16.4.2 interrupt mask registers ................................ ................................ ................................ ....... 16-5 16.4.3 interrupt priority registers ................................ ................................ ................................ .... 16-8 16.4.4 interrupt offset register ................................ ................................ ................................ ....... 16-9 16.4.5 interrupt by priority register ................................ ................................ ................................ . 16-12 16.4.6 interrupt test register ................................ ................................ ................................ .......... 16-12 chapter 17 32-bit timers 17.1 overview ................................ ................................ ................................ ................................ ......... 17-1 17.2 feature ................................ ................................ ................................ ................................ ............ 17-1 17.3 interval mode operation ................................ ................................ ................................ .................. 17-2 17.4 toggle mode operation ................................ ................................ ................................ ................... 17-2 17.5 timer operation guidelines ................................ ................................ ................................ ............. 17-3 17.6 timer special register ................................ ................................ ................................ ..................... 17-4 17.6.1 timer mode register ................................ ................................ ................................ ............ 17-4 17.6.2 timer data registers ................................ ................................ ................................ ............ 17-6 17.6.3 timer count registers ................................ ................................ ................................ .......... 17-7 17.6.4 timer interrupt clear registers ................................ ................................ ............................. 17-8 17.6.5 watchdog timer register ................................ ................................ ................................ ..... 17-9 chapter 18 electrical data 18.1 overview ................................ ................................ ................................ ................................ ......... 18-1 18.2 absolute maximum ratings ................................ ................................ ................................ ............. 18-1 18.3 recommended operating conditions ................................ ................................ ............................... 18-1 18.4 dc electrical specifications ................................ ................................ ................................ ............. 18-2 18.5 max power consumption ................................ ................................ ................................ ................. 18-4 18.6 ac electrical characteristics ................................ ................................ ................................ ............ 18-5 chapter 19 mechanical data 19.1 overview ................................ ................................ ................................ ................................ ......... 19-1 S3C2500B risc microcontroller xvii list of figures figure title page number number 1-1 S3C2500B block diagram ................................ ................................ ...................... 1-5 1-2 S3C2500B pin assignment diagram ................................ ................................ ...... 1-6 2-1 big-endian addresses of bytes within words ................................ .......................... 2-2 2-2 little-endian addresses of bytes words ................................ ................................ . 2-2 2-3 register organization in arm state ................................ ................................ ....... 2-5 2-4 register organization in thumb state ................................ ................................ .. 2-6 2-5 mapping of thumb state registers onto arm state registers .............................. 2-7 2-6 program status register format ................................ ................................ ............ 2-8 2-7 arm940t block diagram ................................ ................................ ....................... 2-18 3-1 arm instruction set format ................................ ................................ ................... 3-1 3-2 branch and exchange instructions ................................ ................................ .......... 3-5 3-3 branch instructions ................................ ................................ ................................ . 3-7 3-4 data processing instructions ................................ ................................ .................. 3-9 3-5 arm shift operations ................................ ................................ ............................. 3-12 3-6 logical shift left ................................ ................................ ................................ .... 3-12 3-7 logical shift right ................................ ................................ ................................ .. 3-13 3-8 arithmetic shift right ................................ ................................ ............................. 3-13 3-9 rotate right ................................ ................................ ................................ ........... 3-14 3-10 rotate right extended ................................ ................................ ........................... 3-14 3-11 psr transfer ................................ ................................ ................................ ......... 3-20 3-12 multiply instructions ................................ ................................ ................................ 3-23 3-13 multiply long instructions ................................ ................................ ....................... 3-25 3-14 single data transfer instructions ................................ ................................ ............ 3-28 3-15 little-endian offset addressing ................................ ................................ .............. 3-30 3-16 half-word and signed data transfer with register offset ................................ ....... 3-34 3-17 half-word and signed data transfer with immediate offset and auto-indexing ...... 3-35 3-18 block data transfer instructions ................................ ................................ ............. 3-40 3-19 post-increment addressing ................................ ................................ ..................... 3-41 3-20 pre-increment addressing ................................ ................................ ...................... 3-42 3-21 post-decrement addressing ................................ ................................ ................... 3-42 3-22 pre-decrement addressing ................................ ................................ ..................... 3-43 3-23 swap instruction ................................ ................................ ................................ ..... 3-47 3-24 software interrupt instruction ................................ ................................ .................. 3-49 3-25 coprocessor data operation instruction ................................ ................................ . 3-51 3-26 coprocessor data transfer instructions ................................ ................................ .. 3-53 3-27 coprocessor register transfer instructions ................................ ............................ 3-56 3-28 undefined instruction ................................ ................................ .............................. 3-58 3-29 thumb instruction set formats ................................ ................................ ............. 3-64 xviii xviii S3C2500B risc microcontroller list of figures (continued) figure title page number number 3-30 format 1 ................................ ................................ ................................ ................ 3-67 3-31 format 2 ................................ ................................ ................................ ................ 3-68 3-32 format 3 ................................ ................................ ................................ ................ 3-70 3-33 format 4 ................................ ................................ ................................ ................ 3-71 3-34 format 5 ................................ ................................ ................................ ................ 3-73 3-35 format 6 ................................ ................................ ................................ ................ 3-76 3-36 format 7 ................................ ................................ ................................ ................ 3-77 3-37 format 8 ................................ ................................ ................................ ................ 3-79 3-38 format 9 ................................ ................................ ................................ ................ 3-81 3-39 format 10 ................................ ................................ ................................ .............. 3-83 3-40 format 11 ................................ ................................ ................................ .............. 3-84 3-41 format 12 ................................ ................................ ................................ .............. 3-85 3-42 format 13 ................................ ................................ ................................ .............. 3-87 3-43 format 14 ................................ ................................ ................................ .............. 3-88 3-44 format 15 ................................ ................................ ................................ .............. 3-90 3-45 format 16 ................................ ................................ ................................ .............. 3-91 3-46 format 17 ................................ ................................ ................................ .............. 3-93 3-47 format 18 ................................ ................................ ................................ .............. 3-94 3-48 format 19 ................................ ................................ ................................ .............. 3-95 4-1 S3C2500B address map after resest ................................ ................................ ..... 4-2 4-2 external address bus diagram ................................ ................................ .............. 4-4 4-3 priority groups of S3C2500B ................................ ................................ ................. 4-5 4-4 ahb programmable priority registers ................................ ................................ ... 4-6 4-5 shows the clock generation logic of the S3C2500B ................................ ............. 4-14 4-6 divided system clock timing diagram ................................ ................................ .. 4-19 5-1 memory bank address map ................................ ................................ ................... 5-4 5-2 memory controller bus signals ................................ ................................ .............. 5-6 5-3 8-bit rom, sram and flash basic connection ................................ ..................... 5-14 5-4 8-bit rom, sram and flash basic connection (8-bit memory x 2) ........................ 5-15 5-5 16-bit sram basic connection ................................ ................................ .............. 5-16 5-6 16-bit rom and flash basic connection ................................ ............................... 5-17 5-7 16-bit rom basic connection 2 ................................ ................................ ............. 5-18 5-8 16-bit sram basic connection 2 ................................ ................................ ........... 5-19 5-9 rom & sram with muxed address & data bus connection ................................ .. 5-20 5-10 bncon ................................ ................................ ................................ .................. 5-22 5-11 bank n control (bncon) register configuration ................................ .................... 5-24 5-12 muxed bus control (muxbcon) register config uration ................................ ....... 5-26 5-13 wait control (waitcon) register configuration ................................ .................. 5-28 S3C2500B risc microcontroller xix list of figures (continued) figure title page number number 5-14 read timing diagram 1 ................................ ................................ ......................... 5-29 5-15 write timing diagram 1 ................................ ................................ ......................... 5-30 5-16 read timing diagram 2 ................................ ................................ ......................... 5-31 5-17 write timing diagram 2 ................................ ................................ ......................... 5-32 5-18 read after write at the same bank (cohdis = 1) ................................ ................. 5-33 5-19 read timing diagram (muxed bus) ................................ ................................ ........ 5-34 5-20 write timing diagram (muxed bus) ................................ ................................ ....... 5-35 5-21 write timing diagram (newait) ................................ ................................ ............ 5-36 5-22 write timing diagram (nready) ................................ ................................ ........... 5-37 5 -23 sdram configu ration register 0 ................................ ................................ ........... 5-49 5 -24 sdram command register ................................ ................................ ................... 5-51 5 -25 sdram refresh timer register ................................ ................................ ............. 5-52 5 -26 sdram write buffer time-out register ................................ ................................ . 5-53 5 -27 single read operation (cas latency=2) ................................ .... 5-54 5 -28 single read operation (cas latency=3) ................................ .... 5-55 5 -29 single write operation ................................ ................... 5-56 5 -30 burst read operation (cas latency = 2) ................................ ... 5-57 5-31 burst read operation (cas latency = 3) ................................ ... 5-58 5-32 burst write operation ................................ ................................ ............................. 5-59 6-1 i 2 c block diagram ................................ ................................ ................................ .. 6-1 6-2 master transmitter and slave receiver ................................ ................................ .. 6-3 6-3 master receiver and slave transmitter ................................ ................................ .. 6-4 6-4 start and stop conditions ................................ ................................ ....................... 6-5 6-5 data transfer format ................................ ................................ ............................. 6-7 6-6 i 2 c control status register ................................ ................................ ..................... 6-10 7-1 ethernet diagram ................................ ................................ ................................ ... 7-1 7-2 data structure of tx buffer descriptor ................................ ................................ .... 7-10 7-3 data structure of rx buffer descriptor ................................ ................................ ... 7-11 7-4 data structure of the receive frame ................................ ................................ ..... 7-12 7-5 fields of an ieee802.3/ethernet frame ................................ ................................ . 7-38 7-6 csma/cd transmit operation ................................ ................................ ............... 7-40 7-7 timing for transmission without collision ................................ ............................... 7-41 7-8 timing for transmission with collision in preamble ................................ ................ 7-42 7-9 receiving frame without error ................................ ................................ ............... 7-43 7-10 receiving frame with error ................................ ................................ .................... 7-43 7-11 csma/cd receive operation ................................ ................................ ................ 7-44 7-12 mac control frame format ................................ ................................ ................... 7-46 7-13 timing relationship of transmission signals at mii ................................ ................ 7-50 7-14 timing relationship of reception signals at mii ................................ ..................... 7-50 7-15 mdio sourced by phy ................................ ................................ ........................... 7-50 7-16 mdio sourced by sta ................................ ................................ ........................... 7-50 xx xx S3C2500B risc microcontroller list of figures (continued) figure title page number number 8-1 hdlc module block diagram ................................ ................................ ................ 8-3 8-2 baud rate generator block diagram ................................ ................................ ..... 8-7 8-3 dpll block diagram ................................ ................................ ............................. 8-9 8-4 clo ck usage method diagram ................................ ................................ ............... 8-9 8-5 data encoding methods and timing diagrams ................................ ...................... 8-12 8-6 hdlc data setup and timing diagrams ................................ ................................ 8-13 8-7 ncts already asserted ................................ ................................ ......................... 8-17 8-8 cts lost during transmission ................................ ................................ .............. 8-17 8-9 cts delayed on ................................ ................................ ................................ .... 8-18 8-10 transmit buffer descriptor ................................ ................................ ..................... 8-21 8-11 receive buffer descriptor ................................ ................................ ...................... 8-22 8-12 data structure of the receive data buffer ................................ ............................. 8-23 8-13 hmode register ................................ ................................ ................................ ... 8-29 8-14 hdlc control register ................................ ................................ .......................... 8-34 8-15 hdlc status register ................................ ................................ ............................ 8-40 8-16 hdlc interrupt enable register ................................ ................................ ............. 8-43 8-17 hdlc tx fifo function diagram ................................ ................................ .......... 8-44 8-18 hdlc rx fifo function diagram ................................ ................................ ......... 8-45 8-19 hdlc brg time constant register ................................ ................................ ...... 8-46 8-20 hdlc preamble constant register ................................ ................................ ........ 8-47 8-21 address recognition ................................ ................................ .............................. 8-48 8-22 hdlc station address and hmask register ................................ ......................... 8-49 8-23 dma tx buffer descriptor pointer ................................ ................................ .......... 8-49 8-24 dma rx buffer descriptor pointer ................................ ................................ ......... 8-50 8-25 maximum frame length register ................................ ................................ .......... 8-50 8-26 dma receive buffer size register ................................ ................................ ........ 8-51 8-27 hdlc synchronization register ................................ ................................ ............. 8-51 8-28 data sampling method ................................ ................................ .......................... 8-52 9-1 iom2 channel str ucture in terminal ................................ ................................ ...... 9-2 9-2 monitor channel handshake protocol ................................ ................................ .... 9-4 9-3 abortion of monitor channel transmission ................................ ............................ 9-5 9-4 structure of last byte of channel 2 on du ................................ ............................ 9-7 9-5 structure of last byte of channel 2 on dd ................................ ............................ 9-8 9-6 tsa block diagram ................................ ................................ ............................... 9-9 9-7 iom2 control register ................................ ................................ ........................... 9-13 9-8 iom2 status register ................................ ................................ ............................ 9-15 9-9 iom2 interrupt enable register ................................ ................................ ............. 9-17 9-10 iom2 tic bus address register ................................ ................................ ............ 9-18 9-11 iom2 ic channel transmit data register ................................ .............................. 9-19 9-12 iom2 ic channel receive data register ................................ ............................... 9-19 S3C2500B risc microcontroller xxi list of figures (continued) figure title page number number 9-13 iom2 c/i0 channel transmit data register ................................ ............................ 9-20 9-14 iom2 c/i0 channel receive data register ................................ ............................. 9-20 9-15 iom2 c/i1 channel transmit data register ................................ ............................ 9-21 9-16 iom2 c/i1 channel receive data register ................................ ............................. 9-21 9-17 iom2 monitor channel transmit data register ................................ ...................... 9-22 9-18 iom2 monitor channel receive data register ................................ ....................... 9-22 9-19 tsa a control register ................................ ................................ .......................... 9-23 9-20 tsa b control register ................................ ................................ .......................... 9-24 9-21 tsa c control register ................................ ................................ .......................... 9-25 9-22 iom2 strobe register ................................ ................................ ............................. 9-26 10-1 sof packets ................................ ................................ ................................ .......... 10-3 10-2 usb 1.1 frame model ................................ ................................ ............................ 10-4 10-3 usb frame format ................................ ................................ ................................ 10-5 10-4 usb core block diagram ................................ ................................ ....................... 10-7 10-5 sie block diagram ................................ ................................ ................................ . 10-8 10-6 usbfa register ................................ ................................ ................................ ..... 10-11 10-7 usbpm register ................................ ................................ ................................ .... 10-13 10-8 usbintr register ................................ ................................ ................................ . 10-16 10-9 usbintre register ................................ ................................ ............................... 10-18 10-10 usbfn register ................................ ................................ ................................ ..... 10-19 10-11 usbdisconn register ................................ ................................ ......................... 10-21 10-12 usbep0csr register ................................ ................................ ............................ 10-24 10-13 usbep1csr register ................................ ................................ ............................ 10-29 10-14 usbep2csr register ................................ ................................ ............................ 10-34 10-15 usbep3csr register ................................ ................................ ............................ 10-39 10-16 usbep4csr register ................................ ................................ ............................ 10-44 10-17 usbwcep0 register ................................ ................................ ............................. 10-46 10-18 usbwcep1 register ................................ ................................ ............................. 1 0-48 10-19 usbwcep2 register ................................ ................................ ............................. 10-50 10-20 usbwcep3 register ................................ ................................ ............................. 10-52 10-21 usbwcep4 register ................................ ................................ ............................. 10-54 10-22 usbep0/1/2/3/4 fifo registers ................................ ................................ ............ 10-56 11-1 des/3des block diagram ................................ ................................ ..................... 11-2 xxii xxii S3C2500B risc microcontroller list of figures (continued) figure title page number number 12-1 gdma controller block diagram ................................ ................................ ........... 12-2 12-2 gdma programmable priority registers ................................ ................................ 12-5 12-3 gdma control register ................................ ................................ ......................... 12-11 12-4 gdma source/destination address register ................................ ......................... 12-12 12-5 gdma transfer count register ................................ ................................ ............. 12-13 12-6 gdma run enable register ................................ ................................ .................. 12-14 12-7 gdma interrupt pending register ................................ ................................ .......... 12-15 12-8 external gdma requests (single mode) ................................ ............................... 12-18 12-9 external gdma requests (block mode) ................................ ................................ 12-18 12-10 external gdma requests detailed timing ................................ ............................ 12-19 12-11 single and one data burst mode timing ................................ ............................... 12-20 12-12 single and four data burst mode timing ................................ .............................. 12-21 12-13 block and one data burst mode timing ................................ ................................ 12-22 12-14 block and four data burst timing ................................ ................................ ......... 12-23 13-1 console uart block diagram ................................ ................................ ............... 13-2 13-2 console uart control register ................................ ................................ ............ 13-6 13-3 console uart control register ................................ ................................ ............ 13-7 13-4 console uart status register ................................ ................................ .............. 13-10 13-5 console uart interrupt enable register ................................ ............................... 13-12 13-6 console uart transmit data register ................................ ................................ .. 13-13 13-7 console uart receive data register ................................ ................................ ... 13-14 13-8 console uart baud rate divisor register ................................ ........................... 13-15 13-9 console uart baud rate generator (brg) ................................ .......................... 13-16 13-10 console uart control character 1 register ................................ ......................... 13-17 13-11 console uart control character 2 register ................................ ......................... 13-17 13-12 interrupt-based serial i/o transmit and receive timing diagram ......................... 13-18 13-13 serial i/o frame timing diagram (no rmal console uart) ................................ ... 13-19 13-14 infra-red transmit mode frame timing diagram ................................ .................. 13-19 13-15 infra-red receive mode frame timing diagram ................................ ................... 13-20 14-1 high-speed uart block diagram ................................ ................................ ......... 14-2 14-2 high-speed uart control register ................................ ................................ ....... 14-7 14-3 high-speed uart status register ................................ ................................ ........ 14-12 14-4 high-speed uart interrupt enable register ................................ ......................... 14-15 14-5 high-speed uart transmit buffer register ................................ .......................... 14-16 14-6 high-speed uart receive buffer register ................................ ........................... 14-17 14-7 high-speed uart baud rate divisor register ................................ ...................... 14-18 14-8 high-speed uart baud rate generator (brg) ................................ .................... 14-19 14-9 high-speed uart control character 1 register ................................ .................... 14-20 14-10 high-speed uart control character 2 register ................................ .................... 14-21 S3C2500B risc microcontroller xxiii list of figures (concluded) figure title page number number 14-11 autobaud boundary regsiter range ................................ ................................ ...... 14-22 14-12 high-speed uart autobaud boundary register ................................ .................... 14-22 14-13 example of autobaud table register setting ................................ ......................... 14-23 14-14 high-speed uart autobaud boundary register ................................ .................... 14-23 14-15 when signal is asserted during transmit operation ................................ .............. 14-25 14-16 whe n cts signal is deasserted during transmit operation ................................ .. 14-25 14-17 normal received rx data ................................ ................................ ...................... 14-26 14-18 dcd lost during rx data receive ................................ ................................ ......... 14-26 14-19 interrupt-based serial i/o transmit and receive timing diagram .......................... 14-27 14-20 dma-based serial i/o timing diagram (tx only) ................................ ................... 14-28 14-21 dma-based serial i/o timing diagram (rx only) ................................ .................. 14-28 14-22 serial i/o frame timing diagram (normal high-speed uart) .............................. 14-29 14-23 infra-red transmit mode frame timing diagram ................................ ................... 14-29 14-24 infra-red receive mode frame timing diagra m ................................ ................... 14-30 15-1 i/o port mode registers 1/2 ................................ ................................ ................... 15-4 15-2 i/o function control register 1 ................................ ................................ .............. 15-6 15-3 i/o function control register 2 ................................ ................................ .............. 15-7 15-4 i/o port control register for gdma ................................ ................................ ........ 15-8 15-5 i/o port control register for external interrupt ................................ ....................... 15-10 15-6 i/o port external interrupt clear register ................................ ............................... 15-11 16-1 internal interrupt mode register ................................ ................................ ............. 16-4 16-2 external interrupt mode register ................................ ................................ ............ 16-5 16-3 internal interrupt mask register ................................ ................................ .............. 16-6 16-4 external interrupt mask register ................................ ................................ ............ 16-7 16-5 interrupt priority register ................................ ................................ ........................ 16-8 17-1 timer output signal timing ................................ ................................ .................... 17-2 17-2 32-bit timer block diagram ................................ ................................ ................... 17-3 17-3 timer mode register ................................ ................................ .............................. 17-5 17-4 timer data registers ................................ ................................ .............................. 17-6 17-5 timer counter registers ................................ ................................ ......................... 17-7 17-6 timer interrupt clear register ................................ ................................ ................ 17-8 17-7 watchdog timer register ................................ ................................ ....................... 17-9 19-1 272-bga-2727-an package dimensions ................................ ................................ 19-2 list of tables table title page number number 1-1 S3C2500B signal descriptions ................................ ................................ ............... 1-13 1-2 S3C2500B pad type and feature ................................ ................................ .......... 1-31 1-3 S3C2500B system configuration ................................ ................................ ........... 1-32 1-4 S3C2500B memory controller ................................ ................................ ................ 1-32 1-5 S3C2500B sdram controller ................................ ................................ ................ 1-32 1-6 S3C2500B iic controller ................................ ................................ ........................ 1-33 1-7 S3C2500B ethernet controller 0 ................................ ................................ ............. 1-33 1-8 S3C2500B ethernet controller 1 ................................ ................................ ............. 1-34 1-9 S3C2500B hdlc controller 0 ................................ ................................ ................ 1-35 1-10 S3C2500B hdlc controller 1 ................................ ................................ ................ 1-36 1-11 S3C2500B hdlc controller 2 ................................ ................................ ................ 1-37 1-12 S3C2500B iom2 controller ................................ ................................ .................... 1-38 1-13 S3C2500B usb controller ................................ ................................ ..................... 1-39 1-14 S3C2500B des controller ................................ ................................ ..................... 1-40 1-15 S3C2500B gdma controller ................................ ................................ .................. 1-41 1-16 S3C2500B console uart controller ................................ ................................ ..... 1-42 1-17 S3C2500B high-speed uar t controller 0 ................................ .............................. 1-42 1-18 S3C2500B high speed uart controller 1 ................................ .............................. 1-43 1-19 S3C2500B i/o port controller ................................ ................................ ................ 1-43 1-20 S3C2500B interrupt controller ................................ ................................ ................ 1-44 1-21 S3C2500B timer controller ................................ ................................ .................... 1-45 2-1 psr mode. bit values ................................ ................................ ............................ 2-10 2-2 exception entry/exit ................................ ................................ ............................... 2-12 2-3 exception vectors ................................ ................................ ................................ .. 2-14 2-4 arm9tdmi implementation option ................................ ................................ ........ 2-19 2-5 cp15 register map ................................ ................................ ................................ 2-21 2-6 id code register ................................ ................................ ................................ .... 2-21 2-7 cache type register format ................................ ................................ .................. 2-22 2-8 cp15 register 1 ................................ ................................ ................................ ..... 2-23 2-9 clocking modes ................................ ................................ ................................ ...... 2-23 2-10 cacheable register format ................................ ................................ .................... 2-24 2-11 write buffer control register ................................ ................................ ................. 2-25 2-12 protection space register format ................................ ................................ .......... 2-26 2-13 permission encoding ................................ ................................ .............................. 2-26 2-14 cp15 data protection region registers ................................ ................................ . 2-27 2-15 cp15 instruction protection region registers ................................ ........................ 2-27 2-16 cp15 protection region register format ................................ ............................... 2-28 2-17 area size encoding ................................ ................................ ................................ 2-28 2-18 cache operations writing to register 7 ................................ ................................ .. 2-29 2-19 cp15 register 7 index/segment data format ................................ ........................ 2-30 2-20 cp15 register 7 prefetch address format ................................ ............................. 2-30 2-21 lockdown register format ................................ ................................ ..................... 2-31 2-22 cp15 register 15 ................................ ................................ ................................ ... 2-32 xxvi xxvi S3C2500B risc microcontroller list of tables (continued) table title page number number 3-1 the arm instruction set ................................ ................................ ........................ 3-2 3-2 condition code summary ................................ ................................ ...................... 3-4 3-3 arm data processing instructions ................................ ................................ ......... 3-11 3-4 incremental cycle times ................................ ................................ ....................... 3-17 3-5 assembler syntax descriptions ................................ ................................ ............. 3-27 3-6 addressing mode names ................................ ................................ ....................... 3-45 3-7 thumb instruction set opcodes ................................ ................................ ........... 3-65 3-8 summary of format 1 instructions ................................ ................................ ......... 3-67 3-9 summary of format 2 instructions ................................ ................................ ......... 3-68 3-10 summary of format 3 instructions ................................ ................................ ......... 3-70 3-11 summary of format 4 instructions ................................ ................................ ......... 3-71 3-12 summary of forma t 5 instructions ................................ ................................ ......... 3-74 3-13 summary of pc-relative load instruction ................................ ............................. 3-76 3-14 summary of format 7 instructions ................................ ................................ ......... 3-77 3-15 summary of format 8 instructions ................................ ................................ .......... 3-79 3-16 summary of format 9 instructions ................................ ................................ ......... 3-81 3-17 half-word data transfer instructions ................................ ................................ ...... 3-83 3-18 sp-relative load/store instructions ................................ ................................ ...... 3-84 3-19 load address ................................ ................................ ................................ ........ 3-85 3-20 the add sp instruction ................................ ................................ ......................... 3-87 3-21 push and pop instructions ................................ ................................ .................. 3-88 3-22 the multiple load/store instructions ................................ ................................ ...... 3-90 3-23 the conditional branch instructions ................................ ................................ ...... 3-91 3-24 the swi instruction ................................ ................................ ............................... 3-92 3-25 summary of branch instruction ................................ ................................ .............. 3-93 3-26 the bl instruction ................................ ................................ ................................ . 3-94 4-1 the base address of remapped memory ................................ .............................. 4-3 4-2 ahb bus priorities for arbitration ................................ ................................ ........... 4-4 4-3 clock frequencies for clkmod pins, cpu_freq pins, and bus_freq pins .... 4-9 4-4 p, m, s values of the S3C2500B pll ................................ ................................ .... 4-13 4-5 s ystem c onfiguration r egisters ................................ ................................ ............. 4-15 S3C2500B risc microcontroller xxvii list of tables (continued) table title page number number 5-1 base address of each bank ................................ ................................ ................... 5-3 5-2 bus interface signals ................................ ................................ .............................. 5-5 5-3 external 32-bit memory store op eration with big-endian ................................ ....... 5-7 5-4 external 32-bit memory load operation with big-endian ................................ ........ 5-7 5-5 external 16-bit store operation with big-endian ................................ ..................... 5-8 5-6 external 16-bit load operation with big-endian ................................ ...................... 5-8 5-7 external 8-bit store operation with big-endian ................................ ....................... 5-9 5-8 external 8-bit load operation with big-endian ................................ ........................ 5-9 5-9 external 32-bit memory store operation with little-endian ................................ ..... 5-10 5-10 external 32-bit memory load operation with little-endian ................................ ...... 5-10 5-11 external 16-bit store operation with little-endian ................................ ................... 5-11 5-12 external 16-bit load operation with little-endian ................................ ................... 5-11 5-13 external 8-bit store operation with little-endian ................................ .................... 5-12 5-14 external 8-bit load operation with little-endian ................................ ..................... 5-12 5-15 ext. i/o bank controller special registers ................................ ............................. 5-21 5-16 bank n control (bncon) register ................................ ................................ .......... 5-23 5-17 muxed bus control register ................................ ................................ ................... 5-25 5-18 wait control register ................................ ................................ ........................... 5-27 5-19 supported sdram configuration of 32-bit external bus ................................ ......... 5-40 5-20 supported sdram configuration of 16-bit external bus ................................ ......... 5-41 5-21 sdram address mapping of 32-bit external bus ................................ ................... 5-42 5-22 sdram address mapping of 16-bit external bus ................................ ..................... 5-43 5-23 sdram commands ................................ ................................ ................................ 5-44 5-24 sdram special registers ................................ ................................ ...................... 5-47 5-25 sdram configuration register ................................ ................................ .............. 5-47 5-26 sdram command register ................................ ................................ ................... 5-50 5-27 sdram refresh timer register ................................ ................................ ............. 5-52 5-28 sdram write buffer time-out register ................................ ................................ . 5-53 6-1 control status register ................................ ................................ ........................... 6-9 6-2 iiccon register description ................................ ................................ .................. 6-9 6-3 iicbuf register ................................ ................................ ................................ ..... 6-11 6-4 iicbuf register description ................................ ................................ ................... 6-11 6-5 iicps register ................................ ................................ ................................ ....... 6-11 6-6 iicps register des cription ................................ ................................ ..................... 6-11 6-7 iiccnt register ................................ ................................ ................................ ..... 6-12 6-8 iiccnt register description ................................ ................................ ................... 6-12 6-9 iicpnd register ................................ ................................ ................................ ..... 6-12 6-10 iicpnd register description ................................ ................................ .................. 6-12 xxviii xxviii S3C2500B risc microcontroller list of tables (continued) table title page number number 7-1 mac function block descriptions ................................ ................................ .......... 7-3 7-2 ethernet 0 special registers ................................ ................................ ............ 7-13 7-3 ethernet 1 special registers ................................ ................................ ............ 7-14 7-4 bdmatxcon register ................................ ................................ .......................... 7-15 7-5 bdma transmit control register description ................................ ........................ 7-15 7-6 bdma rxcon register ................................ ................................ ........................ 7-16 7-7 bdma receive control register description ................................ ......................... 7-16 7-8 bdmatxdptr register ................................ ................................ ........................ 7 -17 7-9 bdma transmit buffer descriptor start address register description .................... 7-17 7-10 bdmarxdptr register ................................ ................................ ....................... 7-17 7-11 bdma receive buffer descriptor start address register description .................... 7-17 7-12 btxbdcnt register ................................ ................................ ............................. 7-18 7-13 bdma transmit buffer descriptor counter ................................ ............................. 7-18 7-14 brxbdcnt register ................................ ................................ ............................. 7-18 7-15 bdma receive buffer descriptor counter ................................ .............................. 7-18 7-16 bmtxinten register ................................ ................................ ............................ 7-19 7-17 bdma/mac transmit interrupt enable register description ................................ .. 7-19 7-18 bmtxstat register ................................ ................................ ............................. 7-20 7-19 bdma/mac transmit interrupt status register description ................................ ... 7-20 7-20 bmrxinten register ................................ ................................ ........................... 7-21 7-21 bdma/mac receive interrupt enable register description ................................ ... 7-21 7-22 bmrxstat register ................................ ................................ ............................. 7-22 7-23 bdma/mac receive interrupt status register description ................................ .... 7-22 7-24 bdmarxlen register ................................ ................................ .......................... 7-23 7-25 bdma receive frame size register description ................................ ................... 7-23 7-26 cftxstat register ................................ ................................ .............................. 7-24 7-27 transmit control frame register description ................................ ........................ 7-24 7-28 maccon register ................................ ................................ ................................ 7-25 7-29 mac control register description ................................ ................................ ......... 7-25 7-30 camcon regist er ................................ ................................ ................................ 7-26 7-31 cam control register description ................................ ................................ ......... 7-26 7-32 mactxcon register ................................ ................................ ............................ 7-27 7-33 mac transmit control register description ................................ ........................... 7-27 7-34 mactxstat register ................................ ................................ ........................... 7-28 7-35 mac transmit status register description ................................ ............................ 7-28 7-36 macrxcon register ................................ ................................ ............................ 7-29 7-37 mac receive control register description ................................ ............................ 7-29 7-38 macrxstat register ................................ ................................ .......................... 7-30 7-39 mac receive status register description ................................ ............................. 7-30 7-40 stadata register ................................ ................................ ................................ 7-31 S3C2500B risc microcontroller xxix list of tables (continued) table title page number number 7-41 station management register description ................................ .............................. 7 -31 7-42 stacon register ................................ ................................ ................................ .. 7-32 7-43 stacon register description ................................ ................................ ................ 7-32 7-44 camen register ................................ ................................ ................................ .... 7-33 7-45 cam enable register description ................................ ................................ ........... 7-33 7-46 misscnt register ................................ ................................ ................................ . 7-34 7-47 missed error count register description ................................ ................................ 7-34 7-48 pzcnt register ................................ ................................ ................................ ..... 7-35 7-49 received pause count register description ................................ ........................... 7-35 7-50 rmpzcnt register ................................ ................................ ................................ 7-35 7-51 remote pause count register description ................................ ............................. 7-35 7-52 cam register ................................ ................................ ................................ ......... 7-36 7-55 content address memory (cam) register description ................................ ............ 7-36 7-53 mac frame format description ................................ ................................ ............. 7-37 7-54 sta frame structure description ................................ ................................ ........... 7-45 8-1 hdlc data frame format ................................ ................................ ..................... 8-4 8-2 baud rate example of hdlc ................................ ................................ ................. 8-8 8-3 hdlc data setup and hold timing ................................ ................................ ........ 8-13 8-4 hdlc channel a special registers ................................ ................................ ....... 8-24 8-5 hdlc channel b special registers ................................ ................................ ....... 8-25 8-6 hdlc channel c special registers ................................ ................................ ....... 8-26 8-7 hmodea, hmodeb, and hmodec register ................................ ........................ 8-27 8-8 hmode register description ................................ ................................ ................. 8-27 8-9 hcona , hconb, and hconc register ................................ ............................... 8-30 8-10 hcon register description ................................ ................................ .................... 8-30 8-11 hstata, hstatb, and hstatc register ................................ ............................ 8-36 8-12 hstat register d escription ................................ ................................ ................... 8-37 8-13 hintena, hintenb, and hintenc register ................................ ........................ 8-42 8-14 hinten register description ................................ ................................ ................. 8-42 8-15 hbrgtca and hbrgtcb register ................................ ................................ ....... 8-46 8-16 hprmba and hprmbb register ................................ ................................ ........... 8-47 8-17 preamble reference pattern ................................ ................................ .................. 8-47 8-18 hsadr and hmask register ................................ ................................ ................ 8-48 8-19 dma tx buffer descriptor pointer registers ................................ ........................... 8-49 8-20 dma rx buffer descriptor pointer registers ................................ .......................... 8-50 8-21 hdmatxcnt and hdmarxcnt registers ................................ ........................... 8-50 8-22 dma rx buffer size register ................................ ................................ ................. 8-51 8-23 synchronization register ................................ ................................ ........................ 8-51 8-24 transparent control r egister ................................ ................................ .................. 8-52 8-25 htxbdcnta, htxbdcntb, and htxbdcntc register ................................ ...... 8-53 8-26 hrxbdcnta, hrxbdcntb, and hrxbdcntc register ................................ ..... 8-53 8-27 htxbdmaxcnta, htxbdmaxcntb, and htxbdmaxcntc register ............... 8-54 8-28 hrxbdmaxcnta, hrxbdmaxcntb, and hrxbdmaxcntc register .............. 8-54 xxx xxx S3C2500B risc microcontroller list of tables (continued) table title page number number 9-1 hdlc external pin multiplexed signals ................................ ................................ . 9-10 9-2 iom2 special registers ................................ ................................ ......................... 9-11 9-3 iom2con register (control register) ................................ ................................ ... 9-12 9-4 iom2stat register (status register) ................................ ................................ ... 9-14 9-5 iom2inten register (interrupt enable register) ................................ ................... 9-16 9-6 iom2tba register (tic bus address register) ................................ ..................... 9-18 9-7 iom2ictd (iom2 ic channel transmit data register) ................................ .......... 9-19 9-8 iom2icrd (iom2 ic channel receive data register) ................................ .......... 9-19 9-9 iom2citd0 (iom2 c/i0 channel transmit data register) ................................ ..... 9-20 9-10 iom2cird0 (iom2 c/i0 channel receive data register) ................................ ..... 9-20 9-11 iom2citd1 (iom2 c/i1 channel transmit data register) ................................ ..... 9-21 9-12 iom2cird1 (iom2 c/i1 channel receive data register) ................................ ..... 9-21 9-13 iom2mtd (iom2 monitor channe l transmit data register) ................................ .. 9-22 9-14 iom2mrd (iom2 monitor channel receive data register) ................................ ... 9-22 9-15 tsaacon (tsa a control register) ................................ ................................ ..... 9-23 9-16 tsabcon (tsa b control register) ................................ ................................ ..... 9-24 9-17 tsaccon (tsa c control register) ................................ ................................ ..... 9-25 9-18 iom2strb (strobe register) ................................ ................................ ................ 9-26 10-1 usb registers ................................ ................................ ................................ ....... 10-9 10-2 usbfa register ................................ ................................ ................................ .... 10-10 10-3 usbfa register description ................................ ................................ .................. 10-10 10-4 usbpm register ................................ ................................ ................................ ... 10-12 10-5 usbpm register description ................................ ................................ ................. 10-12 10-6 usbintr register ................................ ................................ ................................ 10-14 10-7 usbintr register description ................................ ................................ .............. 10-15 10-8 usbintre regi ster ................................ ................................ .............................. 10-17 10-9 usbintre register description ................................ ................................ ............ 10-17 10-10 usbfn register ................................ ................................ ................................ .... 10-19 10-11 usbfn register descriptions ................................ ................................ ................ 10-19 10-12 cntvle table ................................ ................................ ................................ ...... 10-20 10-13 usbdisconn register ................................ ................................ ......................... 10-20 10-14 usbdisconn register description ................................ ................................ ...... 10-20 10-15 usbep0csr register ................................ ................................ ........................... 10-22 10-16 usbep0csr register description ................................ ................................ ........ 10-22 10-17 usbep1csr register ................................ ................................ ........................... 10-25 10-18 usbep1csr register description ................................ ................................ ........ 10-25 10-19 usbep2csr register ................................ ................................ ........................... 10-30 10-20 usbep2csr register description ................................ ................................ ........ 10-30 S3C2500B risc microcontroller xxxi list of tables (continued) table title page number number 10-21 usbep3csr register ................................ ................................ ............................ 10-35 10-22 usbep3csr register description ................................ ................................ ......... 10-35 10-23 usbep4csr register ................................ ................................ ............................ 10-40 10-24 usbep4csr register description ................................ ................................ ......... 10-40 10-25 usbwcep0 register ................................ ................................ ............................. 10-45 10-26 usbwcep0 register description ................................ ................................ .......... 10-45 10-27 usbwcep1 register ................................ ................................ ............................. 10-47 10-28 usbwcep1 register description ................................ ................................ .......... 10-47 10-29 usbwcep2 register ................................ ................................ ............................. 10-49 10-30 usbwcep2 register description ................................ ................................ .......... 10-49 10-31 usbwcep3 register ................................ ................................ ............................. 10-51 10-32 usbwcep3 register description ................................ ................................ .......... 10-51 10-33 usbwcep4 register ................................ ................................ ............................. 10-53 10-34 usbwcep4 register d escription ................................ ................................ .......... 10-53 10-35 usbep0, 1, 2, 3, 4, 5 descriptions ................................ ................................ ......... 10-55 11-1 des/3des special registers overview ................................ ................................ . 11-3 11-2 des/3des control register description ................................ ................................ . 11-4 11-3 des/3des status register description ................................ ................................ .. 11-5 11-4 des/3des interrupt enable register description ................................ ................... 11-6 11-5 des/3des run enable register description ................................ .......................... 11-6 11-6 des/3des key1 left side register description ................................ ..................... 11-6 11-7 des/3des key 1 right side register description ................................ .................. 11-6 11-8 des/3des key 2 left side register description ................................ .................... 11-7 11-9 des/3des key 2 right side register description ................................ .................. 11-7 11-10 des/3des key 3 left side register description ................................ .................... 11-7 11-11 des/3des key 3 right side register description ................................ .................. 11-7 11-12 des/3des iv left side register description ................................ .......................... 11-7 11-13 des/3des iv right side register description ................................ ....................... 11-7 11-14 des/3des input data fifo description ................................ ................................ . 11-8 11-15 des/3des output data fifo description ................................ .............................. 11-8 12-1 gdma special registers overview ................................ ................................ ........ 12-3 12-2 gdma programmable priority registers ................................ ................................ 12-4 12-3 dcon0/1/2/3/4/5 registers ................................ ................................ .................... 12-9 12-4 gdma control register description ................................ ................................ ....... 12-9 12-5 dsar0/1/2/3/4/5 and ddar0/1/2/3/4/5 registers ................................ ................... 12-12 12-6 dtcr0/1/2/3/4/5 registers ................................ ................................ ..................... 12-13 12-7 drer0/1/2/3/4/5 registers ................................ ................................ ..................... 12-14 12-8 dipr0/1/2/3 registers ................................ ................................ ............................ 12-15 xxxii xxxii S3C2500B risc microcontroller list of tables (continued) table title page number number 13-1 console uart special registers overview ................................ ........................... 13-3 13-2 cucon registers ................................ ................................ ................................ . 13-4 13-3 console uart control register description ................................ .......................... 13-4 13-4 custat registers ................................ ................................ ................................ 13-8 13-5 console uart status register description ................................ ........................... 13-8 13-6 cuint registers ................................ ................................ ................................ ... 13-11 13-7 console uart interrupt enable register description ................................ ............ 13-11 13-8 cutxbuf registers ................................ ................................ .............................. 13-13 13-9 console uart transmit register description ................................ ........................ 13-13 13-10 curxbuf registers ................................ ................................ ............................. 13-14 13-11 console uart receive register description ................................ ........................ 13-14 13-12 cubrd registers ................................ ................................ ................................ .. 13-15 13-13 typical baud rates examples of console uart ................................ ................... 13-16 13-14 cuchar 1, 2 registers ................................ ................................ ........................ 13-17 14-1 high-speed uart 0 special registers overview ................................ .................. 14-3 14-2 high-speed uart 1 special registers overview ................................ .................. 14-3 14-3 high-speed uart control registers ................................ ................................ .... 14-4 14-4 high-speed uart control register description ................................ .................... 14-4 14-5 high-speed uart status registers ................................ ................................ ...... 14-9 14-6 high-speed uart status register description ................................ ...................... 14-9 14-7 hucon interrupt enable registers ................................ ................................ ........ 14-14 14-8 high-speed uart interrupt enable register description ................................ ....... 14-14 14-9 hutxbuf registers ................................ ................................ .............................. 14-16 14-10 high-speed uart transmit register description ................................ .................. 14-16 14-11 hurxbuf registers ................................ ................................ ............................. 14-17 14-12 high-speed uart receive register description ................................ ................... 14-17 14-13 hubrd0 and hubrd0 registers ................................ ................................ .......... 14-18 14-14 typical baud rates examp les of high-speed uart ................................ ............. 14-19 14-15 huchar1 registers ................................ ................................ ............................. 14-20 14-16 huchar2 registers ................................ ................................ ............................. 14-21 14-17 huabb registers ................................ ................................ ................................ .. 14-22 14-18 huabt registers ................................ ................................ ................................ .. 14-23 S3C2500B risc microcontroller xxxiii list of tables (concluded) table title page number number 15-1 i/o port special registers ................................ ................................ ...................... 15-2 15-2 iopmode1/2 registers ................................ ................................ .......................... 15-3 15-3 iopcon1/2 register ................................ ................................ .............................. 15-5 15-4 iopgdma register ................................ ................................ ................................ 15-8 15-5 iopextint register ................................ ................................ .............................. 15-9 15-6 iopextintpnd register ................................ ................................ ....................... 15-11 15-7 iopdata1/2 register ................................ ................................ ............................ 15-12 15-8 iopdrv1/2 register ................................ ................................ .............................. 15-12 16-1 S3C2500B internal interrupt sources ................................ ................................ ..... 16-2 16-2 S3C2500B external interrupt sources ................................ ................................ .... 16-3 16-3 intmod, extmod register ................................ ................................ .................. 16-3 16-4 intmask, extmask register ................................ ................................ .............. 16-5 16-5 interrupt priority register ................................ ................................ ........................ 16-8 16-6 intoffset_fiq, intoffset_irq register ................................ ....................... 16-9 16-7 index value of interrupt sources ................................ ................................ ............ 16-10 16-8 ipriorhi, ipriorlo register ................................ ................................ .............. 16-12 16-9 inttsthi, inttstlo register ................................ ................................ .............. 16-12 17-1 tmod register ................................ ................................ ................................ ...... 17-4 17-2 tdata0 - tdata5 registers ................................ ................................ ................. 17-6 17-3 tcnt0 - tcnt5 registers ................................ ................................ ..................... 17-7 17-4 timer interrupt clear registers ................................ ................................ ............... 17-8 17-5 wdt register ................................ ................................ ................................ ........ 17-9 17-6 watch dog timer timeout value ................................ ................................ ............. 17-10 18-1 absolute maximum ratings ................................ ................................ .................... 18-1 18-2 recommended operating conditions ................................ ................................ ..... 18-1 18-3 d.c electric characteristics ................................ ................................ .................... 18-2 18-4 operating frequency ................................ ................................ .............................. 18-4 18-5 clock ac timing specification ................................ ................................ ................. 18-4 18-6 ac electrical characteristics for S3C2500B ................................ ........................... 18-5 S3C2500B product overview 1- 1 1 product overview 1.1 overview samsung's S3C2500B 16/32-bit risc microcontroller is a cost-effective, high-performance microcontroller solution for ethernet-based systems, for example, soho router, internet gateway, wlan ap, etc. a variety of communication features is embedded into S3C2500B required in many communication areas, including two ethernet macs, three hdlcs and three tsas supporting iom2, two high speed uarts, a console uart, and usb. a security feature is also supported by des/3des accelerator. this highly integrated microcontroller enables customers to save system costs and increase performance over other 32-bit microcontroller. the S3C2500B is built based on an outstanding cpu core: the arm940t cached processor is a member of the arm9 thumb family of high-performance 32-bit system-on-a-chip processor solutions. it provides a complete high performance cpu subsystem, including arm9tdmi risc integer cpu, 4kb instruction/data caches, write buffer, and protection unit, with an amba bus interface. the arm9tdmi core within the arm940t executes both the 32-bit arm and 16-bit thumb instruction sets, allowing the user to trade off between high performance and high code density. it is binary compatible with arm7tdmi, arm10tdmi, and strong arm processors, and is supported by a wide range of tools, operating systems, and application software. the following integrated on-chip functions are described in detail in this user's manual : arm940t cached processor ethernet controller hdlc controller gdma controller uart controller i 2 c controller usb controller iom2 controller programmable i/o ports interrupt controller product overview S3C2500B 1- 2 1.2 features arm940t core processor fully 16/32-bit risc architecture. harvard cache architecture with separate 4kb instruction and data cache protection unit to partition memory and set individual protection attributes for each partition amba bus architecture up to 166mhz operating frequency memory controller 24-bit external address pins 2 banks for sdram with 16/32-bit external bus. 8 banks for flash/rom/sram/external i/o with 8/16/32-bit external bus. one external bus master with bus request/acknowledge pins ethernet controllers buffered dma (bdma) engine using burst mode bdma tx/rx buffers (256-byte/256-byte) mac tx/rx fifos (80-byte/16-byte) to support re-transmit after collision without dma request data alignment logic support for old and new media (compatible with existing 10m-bit/s networks) 10/100 mbps operation to increase price/performance options and to support phased conversions full ieee 802.3 compatibility for existing applications media independent interface (mii) or 7-wire interface station management (sta) signaling for external physical layer configuration and link negotiation on-chip cam (21 addresses) full-duplex mode for doubled bandwidth pause operation hardware support for full- duplex flow control long packet mode for specialized environments short packet mode for fast testing pad generation for ease of processing and reduced processing time hdlc controllers and three tsas four address station registers and one mask register for address search mode selectable crc/no-crc mode automatic crc generator pre-set digital pll block for clock recovery baud rate generator nrz/nrzi/fm/manchester data formats for tx/rx loop-back and auto-echo mode tx and rx fifos with 8-word (8 32-bit) depth data alignment logic hardware flow control embedded dma controller with buffer descriptor for tx/rx channel universal serial bus (usb) usb specification 1.1 compliant full speed 12 mbps operation with internal transceiver only a total of 5 endpoints: 1 control endpoint and 4 data endpoints that can support control, interrupt, bulk transaction. two data endpoints have 32-byte fifo, two data endpoints have 64-byte fifo. general dma support S3C2500B product overview 1- 3 1.2 features ( continue ) iom2 controller iom2 terminal mode support inter-device communication via ic channel tic bus access control monitor channel collision control optional signals such as bcl and strb bus deactivation/activation via c/i0 bus reversal universal asynchronous receiver transmitter (uart) programmable baud rates 32-byte transmit fifo and 32-byte receive fifo uart source clock selectable (internal clock : pclk2, external clock: ext_uclk) auto baud rate detection infra-red (ir) transmit/receive insertion of one or two stop bits per frame selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers parity checking des/3des accelerator des or triple des mode ecb or cbc mode encryption or decryption support general dma support general dma channels six gdma channels memory to memory data transfer memory to peripheral data transfer (high-speed uart, des, and usb controller) support for four external gdma requests from gdma request pins (xgdma_req0 - xgdma_req3). six programmable timers interval or toggle mode operation hardware watchdog timer useful for periodic reset or interrupts programmable interrupt controller 39 programmable interrupt sources 33 internal sources and 6 external sources programmable priority control programmable i/o port controller 64 programmable i/o ports individually configurable to input, output, or i/o mode for dedicated signals 6 external interrupt request 4 external gdma request 4 external gdma acknowledge 6 timer outputs 14 uart signals 22 hdlc signals product overview S3C2500B 1- 4 1.2 features ( continue ) i 2 c controller master mode operation only baud rate generator for serial clock four plls for system, core, usb and phy clock each pll0 for arm940t the input frequency is 10mhz. provide up to 166mhz output to arm940t pll1 for system clock the input frequency is 10mhz. provide up to 133mhz output to system pll2 for usb the input frequency is 10mhz provide 48mhz output to usb pll3 for phy the input frequency is 10mhz provide 20mhz or 25mhz output to external phy chip operating voltage range internal power: 1.8v 5% i/o power: 3.3v 5% operating temperature range -40 c ? 85 c package type 272 bga S3C2500B product overview 1- 5 1.3 block diagram 10/100 ethernet mac dma 10/100 ethernet mac dma memory controller 133 mhz ahb bus hdlc a dma tsa/ iom-2 hdlc b dma hdlc c dma apb bridge sys. bus arbiter six gdma des/ 3des wdt six timers clock gen. & reset drv. with 4 plls interrupt controller a h b i/f arm940t (166 mhz) 4kb d-cache 4kb d-cache high speed uart high speed uart console uart i 2 c usb 1.1 function gpios 2-bank sdram 8-bank flash/rom/ sram/ext i/o external bus master 10 mhz osc. 20 mhz or 25 mhz req/ack 133 mhz apb bus figure 1-1. S3C2500B block diagram product overview S3C2500B 1- 6 1.4 package diagram top view a1 ball pad corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a b c d e f g h j k l m n p r t u v w y figure 1-2. S3C2500B pin assignment diagram S3C2500B product overview 1- 7 1.5 pin assignment pin # pin name direction pin # pin name direction a1 gnd b11 addr17 o a2 phy_freq i b12 addr15 o a3 hnrts2/gpio59 i/o b13 addr11 o a4 htxd2/gpio56 i/o b14 addr8 o a5 hncts1/gpio52 i/o b15 addr5 o a6 hrxd1/gpio49 i/o b16 addr1 o a7 htxc0/fsc/gpio47 i/o b17 xdata27 i/o a8 hncts0/gpio44 i/o b18 xdata26 i/o a9 htxd0/du i/o b19 xdata23 i/o a10 addr20 o b20 xdata21 i/o a11 addr19 o c1 txd0_0/txd_10m o a12 addr16 o c2 mdc_0 o a13 addr12 o c3 phy_clko o a14 addr9 o c4 hndcd2/gpio61 i/o a15 addr6 o c5 hrxd2/gpio57 i/o a16 addr2 o c6 hrxc1/gpio54 i/o a17 xdata31 i/o c7 hndtr1/gpio50 i/o a18 xdata30 i/o c8 hrxc0/dcl/gpio46 i/o a19 xdata25 i/o c9 hndtr0/bcl/gpio42 i/o a20 xdata24 i/o c10 addr22 o b1 phy_clksel i c11 addr18 o b2 htxc2/gpio63 i/o c12 addr14 o b3 hrxc2/gpio62 i/o c13 addr10/ap o b4 hndtr2/gpio58 i/o c14 addr7 o b5 htxc1/gpio55 i/o c15 addr3 o b6 hnrts1/gpio51 i/o c16 addr0 o b7 htxd1/gpio48 i/o c17 xdata28 i/o b8 hndcd0/gpio45 i/o c18 xdata22 i/o b9 hrxd0/dd i/o c19 xdata20 i/o b10 addr21 o c20 xdata17 i/o product overview S3C2500B 1- 8 1.5 pin assignment ( continue) pin # pin name direction pin # pin name direction d1 txd0_1/loop10m o e19 xdata13 i/o d2 mdio_0 i/o e20 xdata10 i/o d3 col_0 i f1 rxd0_0/rxd_10m i d4 gnd f2 rx_clk_0 i d5 hncts2/gpio60 i/o f3 tx_err_0/pcomp_10m o d6 vdd1.8 f4 vdd1.8 d7 hndcd1/gpio53 i/o f17 vdd3.3 d8 gnd f18 xdata12 i/o d9 hnrts0/strb/gpio43 i/o f19 xdata9 i/o d10 addr23/ale o f20 xdata7 i/o d11 vdd1.8 g1 rxd0_2 i d12 addr13 o g2 rxd0_1 i d!3 gnd g3 vdd3.3 d14 addr4 o g4 crs_0 i d15 vdd1.8 g17 xdata11 i/o d16 xdata29 i/o g18 xdata8 i/o d17 gnd g19 xdata6 i/o d18 xdata19 i/o g20 xdata5 i/o d19 xdata16 i/o h1 rx_err_0 i d20 xdata14 i/o h2 rx_dv_0/link_10m i e1 tx_en_0 o h3 rxd0_3 i e2 txd0_3 o h4 gnd e3 txd0_2 o h17 gnd e4 tx_clk_0 i h18 xdata4 i/o e17 xdata18 i/o h19 xdata3 i/o e18 xdata15 i/o h20 xdata2 i/o S3C2500B product overview 1- 9 1.5 pin assignment ( continued) pin # pin name direction pin # pin name direction j1 vdd1.8_a l1 vdd1.8_a j2 usb_clksel i l2 vdd1.8 j3 usb_d- b l3 cpu_filter o j4 usb_d+ b l4 gnd j9 gnd l9 gnd j10 gnd l10 gnd j11 gnd l11 gnd j12 gnd l12 gnd j17 xdata1 i/o l17 vdd3.3 j18 xdata0 i/o l18 nwbe1/nbe1/dqm1 o j19 nsdcas o l19 nwbe0/nbe0/dqm0 o j20 nsdras o l20 nwbe2/nbe2/dqm2 o k1 gnd m1 vdd1.8_a k2 vdd1.8 m2 vdd1.8 k3 bus_filter o m3 phy_filter o k4 vdd1.8 m4 gnd k9 gnd m9 gnd k10 gnd m10 gnd k11 gnd m11 gnd k12 gnd m12 gnd k17 nsdcs1 o m17 nrcs5 o k18 nsdcs0 o m18 nrcs6 o k19 nsdwe/nwe16 o m19 nrcs7 o k20 nwbe3/nbe3/dqm3 o m20 noe o product overview S3C2500B 1- 10 1.5 pin assignment ( continued ) pin # pin name direction pin # pin name direction n1 vdd1.8_a t3 tx_err_1/pcomp_10m o n2 vdd1.8 t4 rxd1_0/rxd_10m i n3 usb_filter o t17 bus_freq2 i n4 gnd t18 cpu_freq2 i n17 gnd t19 xbmreq i n18 nrcs2 o t20 xbmack o n19 nrcs3 o u1 tx_en_1 o n20 nrcs4 o u2 crs_1 i p1 gnd u3 rxd1_1 i p2 mdc_1 o u4 gnd p3 col_1 i u5 usb_xclk i p4 txd1_1/loop_10m o u6 vdd3.3 p17 b0size1 i u7 hurxd1/gpio35 i/o p18 cke o u8 gnd p19 nrcs0 o u9 gpio0 i/o p20 nrcs1 o u10 vdd3.3 r1 mdio_1 i/o u11 xint2/gpio10 i/o r2 tx_clk_1 i u12 xgdma_req0/gpio14 i/o r3 txd1_2 o u13 gnd r4 vdd1.8 u14 timer2/gpio24 i/o r17 vdd3.3 u15 vdd3.3 r18 b0size0 i u16 tmode i r19 newait i u17 gnd r20 big i u18 bus_freq1 i t1 txd1_0/txd_10m o u19 bus_freq0 i t2 txd1_3 o u20 cpu_freq1 i S3C2500B product overview 1- 11 1.5 pin assignment ( continued ) pin # pin name direction pin # pin name direction v1 rx_clk_1 i w1 rxd1_3 i v2 rxd1_2 i w2 rx_err_1 i v3 rx_dv_1/link10m i w3 cutxd o v4 hutxd0/ gpio29 i/o w4 hurxd0/gpio28 i/o v5 uclk i w5 hunrts0/gpio32 i/o v6 hundcd0/gpio34 i/o w6 xclk i v7 hundtr1/gpio37 i/o w7 hundsr1/gpio38 i/o v8 huncts1/gpio40 i/o w8 hundcd1/gpio41 i/o v9 gpio1 i/o w9 gpio2 i/o v10 gpio5 i/o w10 gpio4 i/o v11 xint1/gpio9 i/o w11 xint0/gpio8 i/o v12 xint5/gpio13 i/o w12 xint4/gpio12 i/o v13 xgdma_req3/gpio17 i/o w13 xgdma_req2/gpio16 i/o v14 xgdma_ack3/gpio21 i/o w14 xgdma_ack1/gpio19 i/o v15 timer3/gpio25 i/o w15 timer0/gpio22 i/o v16 timer5/gpio27 i/o w16 timer4/gpio26 i/o v17 nreset i w17 scl i/o v18 tdi i w18 tck i v19 clkmod1 i w19 tdo o v20 cpu_freq0 i w20 clkmod0 i product overview S3C2500B 1- 12 1.5 pin assignment ( continued ) pin # pin name direction pin # pin name direction y1 curxd i y11 gpio7 i/o y2 clksel i y12 xint3/gpio11 i/o y3 hundtr0/gpio30 i/o y13 xgdma_req1/gpio15 i/o y4 hundsr0/gpio31 i/o y14 xgdma_ack0/gpio18 i/o y5 huncts0/gpio33 i/o y15 xgdma_ack2/gpio20 i/o y6 hutxd1/gpio36 i/o y16 timer1/gpio23 i/o y7 hunrts1/gpio39 i/o y17 gnd y8 hclko o y18 sda i/o y9 gpio3 i/o y19 tms i y10 gpio6 i/o y20 ntrst i S3C2500B product overview 1- 13 1.6 signal description table 1-1. S3C2500B signal descriptions group pin name pin type pad type description system config (20) xclk 1 i phic S3C2500B pll clock source. if clksel is low, pll output clock is used as the system clock. if clksel is high, xclk is used as the system clock. hclko 1 o phbst24 system clock output. the internal system clock is monitored via hclko. if sdram is used, this clock should be used sdram clock. clksel 1 i phic clock select for cpu pll and system pll. if clksel is low, cpu pll clock is used as arm940t source clock and system pll clock is used system clock source, depending on clkmod[1:0]. if clksel is high, xclk is used both clock sources. see figure 4-5. bus_filter 1 i poar50_abb pll filter pin for system pll. if the pll is used, 320pf capacitor should be connected between the pin and ground. phy_freq 1 i phic phy clock frequency select for phy pll. 0 = 20mhz, 1 = 25mhz phy_clksel 1 i phic clock select for phy pll if this pin is set to low, the phy pll generates clock depending on phy_freq state. the phy pll goes into power down mode with phy_clksel set to high. see figure 4-5. phy_filter 1 o poar50_abb pll filter pin for phy pll. if the pll is used, 320pf capacitor should be connected between the pin and ground. phy_clko 1 o phob8 phy clock out phy pll clock output can be monitored by phy_clko. this clock is used as the external phy source clock. however, some switches may cause a link failure when s3c2500?s phy source clock, phy_clko, is used. cpu_filter 1 o poar50_abb pll filter pin for system pll. if the pll is used, 320pf capacitor should be connected between the pin and ground. product overview S3C2500B 1- 14 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description system config (20) clkmod [1:0] 2 i phic the clkmod pin determines internal clock scheme of S3C2500B. when clkmod is ?00?, the nfast clock mode is defined. in this mode, the same clock is used as cpu clock and system clock. when clkmod is "11", the async clock mode is defined. in this mode, the cpu clock and system clock can operate independently as long as the cpu clock is faster than system clock. cpu_freq [2:0] 3 i phic cpu clock frequency selection. bus_freq [2:0] 3 i phic system bus clock frequency selection. nreset 1 i phis not reset. nreset is the global reset input for the S3C2500B and nreset must be held to "low" for at least 64 clock cycles for digital filtering. tmode 1 i phicd test mode. the tmode pin setting is interpreted as follows: 0 = normal operating mode 1 = chip test mode. big 1 i phicd big endian mode select pin when this pin state is ?0?, the S3C2500B operates in litte endian mode. when this pin state is ?1?, the S3C2500B operates in big endian mode. S3C2500B product overview 1- 15 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description memory interface (80) addr[23:0] addr[10]/ap 24 o phot20 address bus. the 24-bit address bus covers the full 16 m word address range of each rom/sram /flash and external i/o bank. in the sdram interface, addr[14:13] is always used as bank address of sdram devices. if sdram devices with 2 internal bank is used, addr[13] should be connected to the ba of sdram. if sdram devices with 4 internal bank is used, addr[14:13] should be connected to the ba[1:0] of sdram. addr[10]/ap is the auto precharge control pin. the auto precharge command is issued at the same time as burst read or burst write by asserting high on addr[10]/ap. xdata[31:0] 32 i/o phbsut20 external bi-directional 32bit data bus. the S3C2500B supports 8 bit, 16bit, 32bit bus with rom/sram/flash/ext io bank, but supports 16 bit or 32 bit bus with sdram bank. nsdcs[1:0] 2 o phot20 not chip select strobe for sdram. two sdram banks are supported. nsdras 1 o phot20 not row address strobe for sdram. nsdras signal is used for both sdram banks. nsdcas 1 o phot20 not column address strobe for sdram. nsdcas signal is used for both sdram banks. cke 1 o phob12 clock enable for sdram cke is clock enable signal for sdram. nsdwe/nwe16 1 o phot20 not write enable for sdram or 16 bit rom/sram. this signal is always used as write enable of sdram and is used as write enable of only 16-bit rom/sram/flash. (that is, it is not enabled for 8 bit memory) product overview S3C2500B 1- 16 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description memory interface (80) newait 1 i phicu not external wait signal. this signal is activated when an external i/o device or rom/sram/flash banks need more access cycles than those defined in the corresponding control register. nrcs[7:0] 8 o phot20 not rom/sram/flash/ external i/o chip select. the S3C2500B supports upt to 8 banks of rom/sram/flash/ external i/o. by controlling the nrcs signals, you can map cpu address into the physical memory banks. b0size[1:0] 2 i phic bank 0 data bus access size. bank0 is used for the boot program. you use these pins to set the size of the bank 0 data bus as follows: ?01? = byte, ?10? = half word, ?11? = word, and ?00? = reserved. noe 1 o phot20 not output enable. whenever a memory read access occurs, the noe output controls the output enable port of the specific memory device. nwbe[3:0]/ nbe[3:0]/ dqm[3:0] 4 o phot20 not write byte enable or dqm for sdram whenever a memory write access occurs, the nwbe output controls the write enable port of the specific memory device. dqm is data input/output mask signal for sdram. S3C2500B product overview 1- 17 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description memory interface (80) xbmreq 1 i phicd external master bus request. an external bus master uses this pin to request the external bus. when it activates the xbmreq, the S3C2500B drives the state of external bus pins to high impedance. this lets the external bus master take control of the external bus. when it has control, the external bus master assumes responsibity for sdram refresh operation. the xbmreq is deactivated when the external bus master releases the external bus. when this occurs, the S3C2500B can get the control of the bus and the xbmack goes ?low?. xbmack 1 o phob8 external bus acknowledge. tap control (5) tck 1 i phic jtag test clock. the jtag test clock shifts state information and test data into, and out of, the S3C2500B during jtag test operations. tms 1 i phicu jtag test mode select. this pin controls jtag test operations in the S3C2500B. this pin is internally connected pull-up. tdi 1 i phicu jtag test data in. the tdi level is used to serially shift test data and instructions into the S3C2500B during jtag test operations. this pin is internally connected pull-up. tdo 1 o phot12 jtag test data out. the tdo level is used to serially shift test data and instructions out of the S3C2500B during jtag test operations. ntrst 1 i phicu jtag not reset. asynchronous reset of the jtag logic. this pin is internally connected pull-up. product overview S3C2500B 1- 18 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description ethernet controller0 (18) mdc_0 1 o phob12 management data clock. the signal level at the mdc pin is used as a timing reference for data transfers that are controlled by the mdio signal. mdio_0 1 i/o phbcut12 management data i/o. when a read command is being executed, data that is clocked out of the phy is presented on this pin. when a write command is being executed, data that is clocked out of the controller is presented on this pin for the physical layer entity, phy. col_0 1 i phis collision detected/collision detected for 10m. col is asserted asynchronously with minimum delay from the start of a collision on the medium in mii mode. col_10m is asserted when a 10-mbit/s phy detects a collision. tx_clk_0 1 i phis transmit clock/transmit clock for 10m. the controller drives txd[3:0] and tx_en from the rising edge of tx_clk. in mii mode, the phy samples txd[3:0] and tx_en on the rising edge of tx_clk. for data transfers, txclk_10m is provided by the 10m-bit/s phy. txd0[3:0]/ txd_10m/ loop_10m 4 o phob12 transmit data/transmit data for 10m. transmit data is aligned on nibble boundaries. txd[0] corresponds to the first bit to be transmitted on the physical medium, which is the lsb of the first byte and the fifth bit of that byte during the next clock. txd_10m is shared with txd[0] and is a data line for transmitting to the 10m-bit/s phy. loop_10m is shared with txd[1] and is driven by the loop-back bit in the control register. S3C2500B product overview 1- 19 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description ethernet controller0 (18) tx_en_0 1 o phob4 transmit enable/transmit enable for 10m. tx_en provides precise framing for the data carried on txd[3:0]. this pin is active during the clock periods in which txd[3:0] contains valid data to be transmitted from the preamble stage through crc. when the controller is ready to transfer data, it asserts txen_10m. tx_err_0/ pcomp_10m 1 o phob4 transmit error/packet compression enable for 10m. tx_err is driven synchronously to tx_clk and sampled continuously by the physical layer entity, phy. if asserted for one or more tx_clk periods, tx_err causes the phy to emit one or more symbols which are not part of the valid data, or delimiter set located somewhere in the frame that is being transmitted. pcomp_10m is asserted immediately after the packet?s da field is received. pcomp_10m is used with the management bus of the dp83950 repeater interface controller (from national semiconductor). the mac can be programmed to assert pcomp if there is a cam match, or if there is not a match. the ric (repeater interface controller) uses this signal to compress (shorten) the packet received for management purposes and to reduce memory usage. (see the dp83950 data sheet, published by national semiconductor, for details on the ric management bus.) this pin is controlled by a special register, with which you can define the polarity and assertion method (cam match active or not match active) of the pcomp signal. product overview S3C2500B 1- 20 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description ethernet controller0 (18) crs_0 1 i phis carrier sense/carrier sense for 10m. crs is asserted asynchronously with minimum delay from the detection of a non- idle medium in mii mode. crs_10m is asserted when a 10-mbit/s phy has data to transfer. a 10-mbit/s transmission also uses this signal. rx_clk_0 1 i phis receive clock/receive clock for 10m. rx_clk is a continuous clock signal. its frequency is 25 mhz for 100-mbit/s operation, and 2.5 mhz for 10-mbit/s. rxd[3:0], rx_dv, and rx_err are driven by the phy off the falling edge of rx_clk, and sampled on the rising edge of rx_clk. to receive data, the rxclk_10 m clock comes from the 10mbit/s phy. rxd0[3:0]/ rxd_10m 4 i phis receive data/receive data for 10m. rxd is aligned on nibble boundaries. rxd[0] corresponds to the first bit received on the physical medium, which is the lsb of the byte in one clock period and the fifth bit of that byte in the next clock. rxd_10m is shared with rxd[0] and it is a line for receiving data from the 10-mbit/s phy. rx_dv_0/ link_10m 1 i phis receive data valid. phy asserts rx_dv synchronously, holding it active during the clock periods in which rxd[3:0] contains valid data received. phy asserts rx_dv no later than the clock period when it places the first nibble of the start frame delimiter (sfd) on rxd[3:0]. if phy asserts rx_dv prior to the first nibble of the sfd, then rxd[3:0] carries valid preamble symbols. link_10m is shared with rx_dv and used to convey the link status of the 10- mbit/s endec. the value is stored in a status register. S3C2500B product overview 1- 21 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description ethernet controller0 (18) rx_err_0 1 i phisd receive error. phy asserts rx_err synchronously whenever it detects a physical medium error (e.g., a coding violation). phy asserts rx_err only when it asserts rx_dv. ethernet controller1 (18) mdc_1 1 o phob12 management data clock. the signal level at the mdc pin is used as a timing reference for data transfers that are controlled by the mdio signal. mdio_1 1 i/o phbcut12 management data i/o. when a read command is being executed, data that is clocked out of the phy is presented on this pin. when a write command is being executed, data that is clocked out of the controller is presented on this pin for the physical layer entity, phy. col_1 1 i phis collision detected/collision detected for 10m. col is asserted asynchronously with minimum delay from the start of a collision on the medium in mii mode. col_10m is asserted when a 10-mbit/s phy detects a collision. tx_clk_1 1 i phis transmit clock/transmit clock for 10m. the controller drives txd[3:0] and tx_en from the rising edge of tx_clk. in mii mode, the phy samples txd[3:0] and tx_en on the rising edge of tx_clk. for data transfers, txclk_10m is provided by the 10m-bit/s phy. product overview S3C2500B 1- 22 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description ethernet controller1 (18) txd1[3:0]/ txd_10m/ loop_10m 4 o phob12 transmit data/transmit data for 10m. transmit data is aligned on nibble boundaries. txd[0] corresponds to the first bit to be transmitted on the physical medium, which is the lsb of the first byte and the fifth bit of that byte during the next clock. txd_10m is shared with txd[0] and is a data line for transmitting to the 10-mbit/s phy. loop_10m is shared with txd[1] and is driven by the loop-back bit in the control register. tx_en_1 1 o phob4 transmit enable/transmit enable for 10m. tx_en provides precise framing for the data carried on txd[3:0]. this pin is active during the clock periods in which txd[3:0] contains valid data to be transmitted from the preamble stage through crc. when the controller is ready to transfer data, it asserts txen_10m. S3C2500B product overview 1- 23 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description ethernet controller1 (18) tx_err_1/ pcomp_10m 1 o phob4 transmit error/packet compression enable for 10m. tx_err is driven synchronously to tx_clk and sampled continuously by the physical layer entity, phy. if asserted for one or more tx_clk periods, tx_err causes the phy to emit one or more symbols which are not part of the valid data, or delimiter set located somewhere in the frame that is being transmitted. pcomp_10m is asserted immediately after the packet?s da field is received. pcomp_10m is used with the management bus of the dp83950 repeater interface controller (from national semiconductor). the mac can be programmed to assert pcomp if there is a cam match, or if there is not a match. the ric (repeater interface controller) uses this signal to compress (shorten) the packet received for management purposes and to reduce memory usage. (see the dp83950 data sheet, published by national semiconductor, for details on the ric management bus.) this pin is controlled by a special register, with which you can define the polarity and assertion method (cam match active or not match active) of the pcomp signal. crs_1 1 i phis carrier sense/carrier sense for 10m. crs is asserted asynchronously with minimum delay from the detection of a non- idle medium in mii mode. crs_10m is asserted when a 10m-bit/s phy has data to transfer. a 10m-bit/s transmission also uses this signal. product overview S3C2500B 1- 24 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description ethernet controller1 (18) rx_clk_1 1 i phis receive clock/receive clock for 10m. rx_clk is a continuous clock signal. its frequency is 25 mhz for 100-mbit/s operation, and 2.5 mhz for 10-mbit/s. rxd[3:0], rx_dv, and rx_err are driven by the phy off the falling edge of rx_clk, and sampled on the rising edge of rx_clk. to receive data, the rxclk_10 m clock comes from the 10m-bit/s phy. rxd1[3:0]/ rxd_10m 4 i phis receive data/receive data for 10m. rxd is aligned on nibble boundaries. rxd[0] corresponds to the first bit received on the physical medium, which is the lsb of the byte in one clock period and the fifth bit of that byte in the next clock. rxd_10m is shared with rxd[0] and it is a line for receiving data from the 10m-bit/s phy. rx_dv_1 link_10m 1 i phis receive data valid. phy asserts rx_dv synchronously, holding it active during the clock periods in which rxd[3:0] contains valid data received. phy asserts rx_dv no later than the clock period when it places the first nibble of the start frame delimiter (sfd) on rxd[3:0]. if phy asserts rx_dv prior to the first nibble of the sfd, then rxd[3:0] carries valid preamble symbols. link_10m is shared with rx_dv and used to convey the link status of the 10- mbit/s endec. the value is stored in a status register. rx_err_1 1 i phisd receive error. phy asserts rx_err synchronously whenever it detects a physical medium error (e.g., a coding violation). phy asserts rx_err only when it asserts rx_dv. S3C2500B product overview 1- 25 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description hdlc0 (8) htxd0/du 1 i/o phbsud4 iom2 data upstream. open drain output and schmit trigger input. hdlc ch-0 transmit data. the serial data output from the transmitter is encoded in nrz/nrzi/ fm/manchester data format. hrxd0/dd 1 i/o phbsud4 iom2 data down stream. open drain output and schmit trigger input. hdlc ch-0 receive data. the serial data input should be coded in nrz/nrzi/fm/manchester data form at. the data should not exceed the rate of the S3C2500B internal master clock. hndtr0/bcl/ gpio42 1 i/o phbst8 iom2 bit clock, 768 khz. hdlc ch-0 data terminal ready. ndtr0 output indicates that the data terminal device is ready for transmis sion and reception. general i/o port. hnrts0/strb/ gpio43 1 i/o phbst8 iom2 data strobe. 8 khz programable signal for selecting an 8-bit timeslot or 16 bit timeslot. hdlc ch-0 request to send. the nrts0 output is controlled by the tx request to send control bit. when the txrts bit is set to ?1? , the nrts output is driven log. when the txrts bit is clear to ?0? , the nrts output remains still low until 1) when the sending frame is reached to end, and 2) when there is no more data in the txfifo for sending a new frame. general i/o port. product overview S3C2500B 1- 26 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description hdlc0 (8) hncts0/ gpio44 1 i/o phbst8 hdlc ch-0 clear to send. the S3C2500B stores each transition of ncts to ensure that its occurrence will be acknowledged by the system. general i/o port. hndcd0/ gpio45 1 i/o phbst8 hdlc ch-0 data carrier detected. a high level on this pin resets and inhibits the receiver operation. data from a previous frame that may remain in the rxfifo is retained. the pin state of transition is stored by the register. general i/o port. hrxc0/dcl/ gpio46 1 i/o phbst8 iom2 data clock. hdlc ch-0 receiver clock. when this clock input is used as the receiver clock, the receiver samples the data on the positive or negedge of hrxc0 clock. this can be determined by s/w selection. this clock can be the source clock of the receiver, the baud rate generator, or the dpll. general i/o port. htxc0/fsc/ gpio47 1 i/o phbst8 iom2 frame syncronization clock. hdlc ch-0 transmitter clock. when this clock input is used as the transmitter clock, the transmitter shifts data on the positive or negative transition of the htxc0 clock input. this can be determined by s/w selection. if you don?t use htxc0 as the transmitter clock, you can use it as an output pin for monitoring internal clock such as the transmitter clock, receiver clock, and baud rate generator output clocks. general i/o port. S3C2500B product overview 1- 27 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description hdlc1 (8) htxd1/gpio48 1 i/o phbst16 hdlc ch-1 transmit data. see the htxd0 description general i/o port. hrxd1/gpio49 1 i/o phbst8 hdlc ch-1 receive data. see the hrxd0 description general i/o port. hndtr1/gpio50 1 i/o phbst16 hdlc ch-1 data terminal ready. see the hndtr0 description general i/o port. hnrts1/gpio51 1 i/o phbst16 hdlc ch-1 request to send. see the hnrts0 description general i/o port. hncts1/gpio52 1 i/o phbst8 hdlc ch-1 clear to send. see the hncts0 description general i/o port. hndcd1/gpio53 1 i/o phbst8 hdlc ch-1 data carrier detected. see the hndcd0 description general i/o port. hrxc1/gpio54 1 i/o phbst8 hdlc ch-1 receiver clock. see the hrxc0 description general i/o port. htxc1/gpio55 1 i/o phbst8 hdlc ch-1 transmitter clock. see the htxc0 description general i/o port. hdlc2 (8) htxd2/gpio56 1 i/o phbst8 hdlc ch-2 transmit data. see the htxd0 description general i/o port. hrxd2/gpio57 1 i/o phbst8 hdlc ch-2 receive data. see the hrxd0 description general i/o port. hndtr2/gpio58 1 i/o phbst8 hdlc ch-2 data terminal ready. see the hndtr0 description general i/o port. hnrts2/gpio59 1 i/o phbst8 hdlc ch-2 request to send. see the hnrts0 description general i/o port. hncts2/gpio60 1 i/o phbst8 hdlc ch-2 clear to send. see the hncts0 description general i/o port. product overview S3C2500B 1- 28 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description hdlc2 (8) hndcd2/ gpio61 1 i/o phbst8 hdlc ch-2 data carrier detected. see the hndcd0 description general i/o port hrxc2/ gpio62 1 i/o phbst8 hdlc ch-2 receiver clock. see the hrxc0 description general i/o port htxc2/ gpio63 1 i/o phbst8 hdlc ch-2 transmitter clock. see the htxc0 description general i/o port usb usb_d+ 1 b pbusbfs internal usb transceiver differential i/o (5) usb_d- 1 b pbusbfs internal usb transceiver differential i/o usb_xclk 1 i phic usb clock source input. usb_clksel 1 i phic usb clock select. when usb_clksel is ?0? , usb pll output is used as the usb clock. when usb_clksel is ?1? , the usb_xclk is usedas the usb clock. see figure 4-5. usb_filter 1 o poar50_abb filter for usb pll if the pll is used, 320pf capacitor should be connected between the pin and ground. cuart curxd 1 i phis console uart receive data. (2) cutxd 1 o phob8 console uart transmit data. huart0 uclk 1 i phis huart external clock for huart0/huart1 (7) hurxd0/ gpio28 1 i/o phbst8 huart0 receive data. hurxd0 is the huart0 input signal for receiving serial data. general i/o port hutxd0/ gpio29 1 i/o phbst8 huart0 transmit data. hutxd0 is the huart0 output signal for transmitting serial data. general i/o port hundtr0/ gpio30 1 i/o phbst8 not huart0 data terminal ready.. this output signals the host (or peripheral) that huart0 is ready to transmit or receive serial data. general i/o port S3C2500B product overview 1- 29 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description huart0 (7) hundsr0/ gpio31 1 i/o phbst8 not huart0 data set ready. this input signals in the huart0 that the peripheral (or host) is ready to transmit or receive serial data general i/o port hunrts0/ gpio32 1 i/o phbst8 not request to send. this pin output state goes low or high according to the transmit data is in tx buffer or tx fifo when hardware flow control bit value set to one in huart0 control register. if tx buffer or tx fifo has data to send, this pin state goes low. if hardware flow control bit is zero, this pin output can be controlled directly by huart0 control register. general i/o port huncts0/ gpio33 1 i/o phbst8 not clear to send this input pin function controlled by hardware flow control bit value in huart0 control register. if hardware flow control bit set to one, huart0 can transmit the transmitting data only when this pin state is active. general i/o port hundcd0/ gpio34 1 i/o phbst8 not data carrier detect. this input pin function is determined by hardware flow control bit value in huart control register. if hardware flow control bit set to one, huart0 can receive the receiving data only when this pin state is active. general i/o port huart1 (7) hurxd1/ gpio35 1 i/o phbst8 huart1 receive data. see hurxd0 description general i/o port hutxd1/ gpio36 1 i/o phbst8 huart1 transmit data. see hutxd0 description general i/o port product overview S3C2500B 1- 30 table 1-1. S3C2500B signal descriptions (continue) group pin name pin type pad type description huart1 (7) hundtr1/ gpio37 1 i/o phbst8 not huart1 data terminal ready.. see hundtr0description general i/o port hundsr1/ gpio38 1 i/o phbst8 not huart1 data set ready. see hundsr0 description general i/o port hunrts1/ gpio39 1 i/o phbst8 not request to send see hunrts0 description general i/o port huncts1/ gpio40 1 i/o phbst8 not clear to send see huncts0 description general i/o port hundcd1/ gpio41 1 i/o phbst8 not data carrier detected see hundcd0 description general i/o port gpio included xint xgdma_ req xgdma_ ack timer gpio[7:0] 8 i/o phbst8 general i/o ports xint[5:0]/ gpio[13:8] 6 i/o phbst8 external interrupt requests/general i/o ports xgdma_req[3:0]/ gpio[17:14] 4 i/o phbst8 external dma requests for gdma/general i/o ports xgdma_ack[3:0]/ gpio[21:18] 4 i/o phbst8 external dma acknowledge from gdma/general i/o ports timer0/gpio[22] 1 i/o phbst8 timer0 out/general i/o port timer1/gpio[23] 1 i/o phbst8 timer1 out/general i/o port timer2/gpio[24] 1 i/o phbst8 timer2 out/general i/o port timer3/gpio[25] 1 i/o phbst8 timer3 out/general i/o port timer4/gpio[26] 1 i/o phbst8 timer4 out/general i/o port timer5/gpio[27] 1 i/o phbst8 timer5 out/general i/o port i 2 c (2) scl 1 i/o phbcd8 i 2 c serial clock sda 1 i/o phbcd8 i 2 c serial data note: total number of signal pins = 217 S3C2500B product overview 1- 31 1.7 pad type table 1-2. S3C2500B pad type and feature pad type type current drive cell type feature slew rate control phic i ? lvcmos level 3.3v ? phicd i ? lvcmos level 3.3v ? phicu i ? lvcmos level 3.3v pull-up resistor ? phis i ? lvcmos schmitt trigger 3.3v ? phisd i ? lvcmos schmitt trigger 3.3v pull-down resister ? poar50_abb o ? analog output with seperate bulk bias ? phob4 o 4ma normal buffer phob12 o 12ma normal buffer phot12 o 12ma tri-state buffer ? phot20 o 20ma tri-state buffer ? phbcut12 i/o 12ma lvcmos level tri-state buffer 3.3v pull-up resistor ? phbsud4 i/o 4sm lvcmos schmit trigger level tri-state buffer 3.3 pull-up resister phbst8 i/o 8ma lvcmos schmit trigger level tri-state buffer 3.3v phbst16 i/o 16ma lvcmos schmit trigger leve tri-state buffer 3.3v phbst24 i/o 24ma lvcmos schmit trigger level tri-state buffer 3.3v phbsut20 i/o 20ma lvcmos schmit trigger level tri-state buffer 3.3v pull-up resistor phbcd8 i/o 8ma lvcmos level open drain buffer 3.3v ? pbusbfs i/o 6ma usb buffer ? note : for the detail information about the pad type, ?input/output cells of the std130/mdl130 0.18 m m 3.3v standard cell library data book? which is produced by samsung electronics co., ltd, asic team. product overview S3C2500B 1- 32 1.8 special registers table 1-3. S3C2500B system configuration registers address r/w description reset value syscfg 0xf0000000 r/w system configuration register ? pdcode 0xf0000004 r product code and revision number register 0x25000000 clkcon 0xf0000008 r/w system clock control register 0x00000000 pclkdis 0xf000000c r/w peripheral clock disable register 0x00000000 clkst 0xf0000010 r clock status register hprif 0xf0000014 r/w ahb bus master fixed priority register 0x00543210 hprir 0xf0000018 r/w ahb bus master round-robin priority register 0x00000000 cpll 0xf000001c r/w core pll configuration register 0x0001039e spll 0xf0000020 r/w system bus pll configuration register 0x00010370 upll 0xf0000024 r/w usb pll configuration register 0x00010328 ppll 0xf0000028 r/w phy pll configuration register 0x000103111 table 1-4. S3C2500B memory controller registers address r/w description reset value b0con 0xf0010000 r/w bank 0 control register 0xc514e488 b1con 0xf0010004 r/w bank 1 control register 0xc514e488 b2con 0xf0010008 r/w bank 2 control register 0xc514e488 b3con 0xf001000c r/w bank 3 control register 0xc514e488 b4con 0xf0010010 r/w bank 4 control register 0xc514e488 b5con 0xf0010014 r/w bank 5 control register 0xc514e488 b6con 0xf0010018 r/w bank 6 control register 0xc514e488 b7con 0xf001001c r/w bank 7 control register 0xc514e488 muxbcon 0xf0010020 r/w muxed bus control register 0x006db6db waitcon 0xf0010024 r/w wait control register 0x00000000 table 1-5. S3C2500B sdram controller registers address r/w description reset value cfgreg 0xf0020000 r/w sdram configuration register 0x00099f0c cmdreg 0xf0020004 r/w sdram command register 0x00000000 refreg 0xf0020008 r/w refresh timer register 0x00000020 wbtoreg 0xf002000c r/w write buffer time-out register 0x00000000 S3C2500B product overview 1- 33 table 1-6. S3C2500B iic controller registers address r/w description reset value iiccon 0xf00f0000 r/w control status register 0x00000000 iicbuf 0xf00f0004 r/w shift buffer register undefined iicps 0xf00f0008 r/w prescaler register 0x00000000 iiccnt 0xf00f000c r/w prescaler counter register 0x00000000 iicpnd 0xf00f0010 r/w interrupt pending register 0x00000000 table 1-7. S3C2500B ethernet controller 0 registers address r/w description reset value bdmatxcona 0xf00a0000 r/w buffered dma transmit control register 0x00000000 bdmarxcona 0xf00a0004 r/w buffered dma receive control register 0x00000000 bdmatxdptra 0xf00a0008 r/w transmit buffer descriptor start address 0x00000000 bdmarxdptra 0xf00a000c r/w receive buffer descriptor start address 0x00000000 btxbdcnta 0xf00a0010 r/w bdma tx buffer descriptor counter 0x00000000 brxbdcnta 0xf00a0014 r/w bdma rx buffer descriptor counter 0x00000000 bmtxintena 0xf00a0018 r/w bdma/mac tx interrupt enable register 0x00000000 bmrxintena 0xf00a001c r/w bdma/mac rx interrupt enable register 0x00000000 bmtxstata 0xf00a0020 r/w bdma/mac tx status register 0x00000000 bmrxstata 0xf00a0024 r/w bdma/mac rx status register 0x00000000 bdmarxlena 0xf00a0028 r/w receive frame size 0x00000000 cftxstata 0xf00a0030 r transmit control frame status 0x00000000 maccona 0xf00b0000 r/w mac control 0x00000000 camcona 0xf00b0004 r/w cam control 0x00000000 mactxcona 0xf00b0008 r/w transmit control 0x00000000 mactxstata 0xf00b000c r/w transmit status 0x00000000 macrxcona 0xf00b0010 r/w receive control 0x00000000 macrxstata 0xf00b0014 r/w receive status 0x00000000 stadataa 0xf00b0018 r/w station management data 0x00000000 stacona 0xf00b001c r/w station management control and address 0x00006000 camena 0xf00b0028 r/w cam enable 0x00000000 misscnta 0xf00b003c r(clr)/w missed error count 0x00000000 pzcnta 0xf00b0040 r pause count 0x00000000 rmpzcnta 0xf00b0044 r remote pause count 0x00000000 cama 0xf00b0080- 0xf00b00fc w cam content (32 words) undefined product overview S3C2500B 1- 34 table 1-8. S3C2500B ethernet controller 1 registers address r/w description reset value bdmatxconb 0xf00c0000 r/w buffered dma transmit control register 0x00000000 bdmarxconb 0xf00c0004 r/w buffered dma receive control register 0x00000000 bdmatxdptrb 0xf00c0008 r/w transmit buffer descriptor start address 0x00000000 bdmarxdptrb 0xf00c000c r/w receive buffer descriptor start address 0x00000000 btxbdcntb 0xf00c0010 r/w bdma tx buffer descriptor counter 0x00000000 brxbdcntb 0xf00c0014 r/w bdma rx buffer descriptor counter 0x00000000 bmtxintenb 0xf00c0018 r/w bdma/mac tx interrupt enable register 0x00000000 bmrxintenb 0xf00c001c r/w bdma/mac rx interrupt enable register 0x00000000 bmtxstatb 0xf00c0020 r/w bdma/mac tx status register 0x00000000 bmrxstatb 0xf00c0024 r/w bdma/mac rx status register 0x00000000 bdmarxlenb 0xf00c0028 r/w receive frame size 0x00000000 cftxstatb 0xf00c0030 r transmit control frame status 0x00000000 macconb 0xf00d0000 r/w mac control 0x00000000 camconb 0xf00d0004 r/w cam control 0x00000000 mactxconb 0xf00d0008 r/w transmit control 0x00000000 mactxstatb 0xf00d000c r/w transmit status 0x00000000 macrxconb 0xf00d0010 r/w receive control 0x00000000 macrxstatb 0xf00d0014 r/w receive status 0x00000000 stadatab 0xf00d0018 r/w station management data 0x00000000 staconb 0xf00d001c r/w station management control and address 0x00006000 camenb 0xf00d0028 r/w cam enable 0x00000000 misscntb 0xf00d003c r(clr)/w missed error count 0x00000000 pzcntb 0xf00d0040 r pause count 0x00000000 rmpzcntb 0xf00d0044 r remote pause count 0x00000000 camb 0xf00d0080- 0xf00d00fc w cam content (32 words) undefined S3C2500B product overview 1- 35 table 1-9. S3C2500B hdlc controller 0 registers address r/w description reset value hmode 0 f0100000 r/w hdlc mode register 0 00000000 hcon 0 f0100004 r/w hdlc control register 0 00000000 hstat 0 f0100008 r/w hdlc status register 0 00000000 hinten 0 f010000c r/w hdlc interrupt enable register 0 00000000 htxfifoc (frame continue) 0 f0100010 w htxfifo frame continue register ? htxfifot (frame terminate) 0 f0100014 w htxfifo frame terminate register ? hrxfifo 0 f0100018 r hrxfifo entry register 0 00000000 hbrgtc 0 f010001c r/w hdlc brg time constant register 0 00000000 hprmb 0 f0100020 r/w hdlc preamble register 0 00000000 hsar0 0 f0100024 r/w hdlc station address 0 0 00000000 hsar1 0 f0100028 r/w hdlc station address 1 0 00000000 hsar2 0 f010002c r/w hdlc station address 2 0 00000000 hsar3 0 f0100030 r/w hdlc station address 3 0 00000000 hmask 0 f0100034 r/w hdlc mask register 0 00000000 hdmatxptr 0 f0100038 r/w dma tx buffer descriptor pointer 0 ffffffff hdmarxptr 0 f010003c r/w dma rx buffer descriptor pointer 0 ffffffff hmflr 0 f0100040 r/w maximum frame length register 0 xxxx0000 hrbsr 0 f0100044 r/w receive buffer size register 0 xxxx0000 hsync 0xf0100048 r/w hdlc sync register 0xxxxxxx7e htxbdcnt 0 f01000c0 r tx buffer descriptor count register 0 xxxxx000 hrxbdcnt 0 f01000c4 r rx buffer descriptor count register 0 xxxxx000 htxmaxbdcnt 0 f01000c8 r/w tx buffer descriptor maximum count register 0 xxxxxfff hrxmaxbdcnt 0 f01000cc r/w rx buffer descriptor maximum count register 0 xxxxxfff tcon 0 f010004c r/w transparent control register 0 xxxx0000 product overview S3C2500B 1- 36 table 1-10. S3C2500B hdlc controller 1 registers address r/w description reset value hmode 0 f0110000 r/w hdlc mode register 0 00000000 hcon 0 f0110004 r/w hdlc control register 0 00000000 hstat 0 f011f0008 r/w hdlc status register 0 00000000 hinten 0 f011f000c r/w hdlc interrupt enable register 0 00000000 htxfifoc (frame continue) 0 f0110010 w htxfifo frame continue register ? htxfifot (frame terminate) 0 f0110014 w htxfifo frame terminate register ? hrxfifo 0 f0110018 r hrxfifo entry register 0 00000000 hbrgtc 0 f011001c r/w hdlc brg time constant register 0 00000000 hprmb 0 f0110020 r/w hdlc preamble register 0 00000000 hsar0 0 f0110024 r/w hdlc station address 0 0 00000000 hsar1 0 f0110028 r/w hdlc station address 1 0 00000000 hsar2 0 f011002c r/w hdlc station address 2 0 00000000 hsar3 0 f0110030 r/w hdlc station address 3 0 00000000 hmask 0 f0110034 r/w hdlc mask register 0 00000000 hdmatxptr 0 f0110038 r/w dma tx buffer descriptor pointer 0 ffffffff hdmarxptr 0 f011003c r/w dma rx buffer descriptor pointer 0 ffffffff hmflr 0 f0110040 r/w maximum frame length register 0 xxxx0000 hrbsr 0 f0110044 r/w receive buffer size register 0 xxxx0000 hsync 0xf0110048 r/w hdlc sync register 0xxxxxxx7e htxbdcnt 0 f01100c0 r tx buffer descriptor count register 0 xxxxx000 hrxbdcnt 0 f01100c4 r rx buffer descriptor count register 0 xxxxx000 htxmaxbdcnt 0 f01100c8 r/w tx buffer descriptor maximum count register 0 xxxxxfff hrxmaxbdcnt 0 f01100cc r/w rx buffer descriptor maximum count register 0 xxxxxfff tcon 0 f011004c r/w transparent control register 0 xxxx0000 S3C2500B product overview 1- 37 table 1-11. S3C2500B hdlc controller 2 registers address r/w description reset value hmode 0 f0120000 r/w hdlc mode register 0 00000000 hcon 0 f0120004 r/w hdlc control register 0 00000000 hstat 0 f0120008 r/w hdlc status register 0 00000000 hinten 0 f012000c r/w hdlc interrupt enable register 0 00000000 htxfifoc (frame continue) 0 f0120010 w htxfifo frame continue register ? htxfifot (frame terminate) 0 f0120014 w htxfifo frame terminate register ? hrxfifo 0 f0120018 r hrxfifo entry register 0 00000000 hbrgtc 0 f012001c r/w hdlc brg time constant register 0 00000000 hprmb 0 f0120020 r/w hdlc preamble register 0 00000000 hsar0 0 f0120024 r/w hdlc station address 0 0 00000000 hsar1 0 f0120028 r/w hdlc station address 1 0 00000000 hsar2 0 f012002c r/w hdlc station address 2 0 00000000 hsar3 0 f0120030 r/w hdlc station address 3 0 00000000 hmask 0 f0120034 r/w hdlc mask register 0 00000000 hdmatxptr 0 f0120038 r/w dma tx buffer descriptor pointer 0 ffffffff hdmarxptr 0 f012003c r/w dma rx buffer descriptor pointer 0 ffffffff hmflr 0 f0120040 r/w maximum frame length register 0 xxxx0000 hrbsr 0 f0120044 r/w receive buffer size register 0 xxxx0000 hsync 0xf0120048 r/w hdlc sync register 0xxxxxxx7e htxbdcnt 0 f01200c0 r tx buffer descriptor count register 0 xxxxx000 hrxbdcnt 0 f01200c4 r rx buffer descriptor count register 0 xxxxx000 htxbdmaxcnt 0 f01200c8 r/w tx buffer descriptor maximum count register 0 xxxxxfff hrxbdmaxcnt 0 f01200cc r/w rx buffer descriptor maximum count register 0 xxxxxfff tcon 0 f012004c r/w transparent control register 0 xxxx0000 product overview S3C2500B 1- 38 table 1-12. S3C2500B iom2 controller register address r/w description reset value iom2con 0xf0130000 r/w control register 0x00000000 iom2stat 0xf0130004 r/w status register 0x00000080 iom2inten 0xf0130008 r/w interrupt enable register 0x00000000 iom2tba 0xf013000c r/w tic bus address 0x00000007 iom2ictd 0xf0130010 r/w ic channel tx buffer 0x000000ff iom2icrd 0xf0130014 r/w ic channel rx buffer 0x00000000 iom2citd0 0xf0130018 r/w c/i0 channel tx buffer 0x0000000f iom2cird0 0xf013001c r/w c/i0 channel rx buffer 0x00000000 iom2citd1 0xf0130020 r/w c/i1 channel tx buffer 0x0000003f iom2cird1 0xf0130024 r/w c/i1 channel rx buffer 0x00000000 iom2mtd 0xf0130028 r/w monitor channel tx buffer 0x000000ff iom2mrd 0xf013002c r/w monitor channel rx buffer 0x000000ff tsaacon 0xf0130030 r/w tsa a control register 0x00000000 tsabcon 0xf0130034 r/w tsa b control register 0x00000000 tsaccon 0xf0130038 r/w tsa c control register 0x00000000 iom2strb 0xf013003c r/w iom2 strobe set register 0x00000000 S3C2500B product overview 1- 39 table 1-13. S3C2500B usb controller register address r/w description reset value usbfa 0xf00e0000 r/w usb function address register 0x00000000 usbpm 0xf00e0004 r/w usb power management register 0x00000000 usbintr 0xf00e0008 r/w usb interrupt register 0x00000000 usbintre 0xf00e000c r/w usb interrupt enable register 0x00000000 usbfn 0xf00e0010 r usb frame number register 0x00000000 usbdisconn 0xf00e0014 r/w usb disconnect timer register 0x00000001 usbep0csr 0xf00e0018 r/w usb endpoint 0 common status register 0x00000001 usbep1csr 0xf00e001c r/w usb endpoint 1 common status register 0x00000401 usbep2csr 0xf00e0020 r/w usb endpoint 2 common status register 0x00000401 usbep3csr 0xf00e0024 r/w usb endpoint 3 common status register 0x00000401 usbep4csr 0xf00e0028 r/w usb endpoint 4 common status register 0x00000401 0xf00e002c reserved usbwcep0 0xf00e0030 r/w usb write count register for endpoint 0 0x00000000 usbwcep1 0xf00e0034 r/w usb write count register for endpoint 1 0x00000000 usbwcep2 0xf00e0038 r/w usb write count register for endpoint 2 0x00000000 usbwcep3 0xf00e003c r/w usb write count register for endpoint 3 0x00000000 usbwcep4 0xf00e0040 r/w usb write count register for endpoint 4 0x00000000 0xf00e0044- 0xf00e007c reserved usbep0 0xf00e0080 r/w usb endpoint 0 fifo undefined usbep1 0xf00e0084 r[w] usb endpoint 1 fifo undefined usbep2 0xf00e0088 r[w] usb endpoint 2 fifo undefined usbep3 0xf00e008c r[w] usb endpoint 3 fifo undefined usbep4 0xf00e0090 r[w] usb endpoint 4 fifo undefined product overview S3C2500B 1- 40 table 1-14. S3C2500B des controller registers address r/w description reset value descon 0xf0090000 r/w des/3des control register 0 00000000 dessta 0xf0090004 r des/3des status register 0x00000231 desint 0xf0090008 r/w des/3des interrupt enable register 0x00000000 desrun 0xf009000c w des/3des run enable register 0x00000000 deskey1l 0xf0090010 r/w key 1 left half 0x00000000 deskey1r 0xf0090014 r/w key 1 right half 0x00000000 deskey2l 0xf0090018 r/w key 2 left half 0x00000000 deskey2r 0xf009001c r/w key 2 right half 0x00000000 deskey3l 0xf0090020 r/w key 3 left half 0x00000000 deskey3r 0xf0090024 r/w key 3 right half 0x00000000 desivl 0xf0090028 r/w iv left half 0x00000000 desivr 0xf009002c r/w iv right half 0x00000000 desinfifo 0xf0090030 w des/3des input fifo 0xxxxxxxxx desoutfifo 0xf0090034 r des/3des output fifo 0xxxxxxxxx S3C2500B product overview 1- 41 table 1-15. S3C2500B gdma controller registers address r/w description reset value dpric 0xf0051000 r/w gdma priority configuration register 0x00000000 dprif 0xf0052000 r/w gdma programmable priority register for fixed 0x00543210 dprir 0xf0053000 r/w gdma programmable priority register for round- robin 0x00000000 dcon0 0xf0050000 r/w gdma channel 0 control register 0x00000000 dsar0 0xf0050004 r/w gdma channel 0 source address register 0x00000000 ddar0 0xf0050008 r/w gdma channel 0 destination address register 0x00000000 dtcr0 0xf005000c r/w gdma channel 0 transfer count register 0x00000000 drer0 0xf0050010 w gdma channel 0 run enable register 0x00000000 dipr0 0xf0050014 r/wc gdma channel 0 interrupt pending register 0x00000000 dcon1 0xf0050020 r/w gdma channel 1 control register 0x00000000 dsar1 0xf0050024 r/w gdma channel 1 source address register 0x00000000 ddar1 0xf0050028 r/w gdma channel 1 destination address register 0x00000000 dtcr1 0xf005002c r/w gdma channel 1 transfer count register 0x00000000 drer1 0xf0050030 w gdma channel 1 run enable register 0x00000000 dipr1 0xf0050034 r/wc gdma channel 1 interrupt pending register 0x00000000 dcon2 0xf0050040 r/w gdma channel 2 control register 0x00000000 dsar2 0xf0050044 r/w gdma channel 2 source address register 0x00000000 ddar2 0xf0050048 r/w gdma channel 2 destination address register 0x00000000 dtcr2 0xf005004c r/w gdma channel 2 transfer count register 0x00000000 drer2 0xf0050050 w gdma channel 2 run enable register 0x00000000 dipr2 0xf0050054 r/wc gdma channel 2 interrupt pending register 0x00000000 dcon3 0xf0050060 r/w gdma channel 3 control register 0x00000000 dsar3 0xf0050064 r/w gdma channel 3 source address register 0x00000000 ddar3 0xf0050068 r/w gdma channel 3 destination address register 0x00000000 dtcr3 0xf005006c r/w gdma channel 3 transfer count register 0x00000000 drer3 0xf0050070 w gdma channel 3 run enable register 0x00000000 dipr3 0xf0050074 r/wc gdma channel 3 interrupt pending register 0x00000000 dcon4 0xf0050080 r/w gdma channel 4 control register 0x00000000 dsar4 0xf0050084 r/w gdma channel 4 source address register 0x00000000 ddar4 0xf0050088 r/w gdma channel 4 destination address register 0x00000000 dtcr4 0xf005008c r/w gdma channel 4 transfer count register 0x00000000 product overview S3C2500B 1- 42 table 1-15. S3C2500B gdma controller (continued) registers address r/w description reset value drer4 0xf0050090 w gdma channel 4 run enable register 0x00000000 dipr4 0xf0050094 r/wc gdma channel 4 interrupt pending register 0x00000000 dcon5 0xf00500a0 r/w gdma channel 5 control register 0x00000000 dsar5 0xf00500a4 r/w gdma channel 5 source address register 0x00000000 ddar5 0xf00500a8 r/w gdma channel 5 destination address register 0x00000000 dtcr5 0xf00500ac r/w gdma channel 5 transfer count register 0x00000000 drer5 0xf00500b0 w gdma channel 5 run enable register 0x00000000 dipr5 0xf00500b4 r/wc gdma channel 5 interrupt pending register 0x00000000 table 1-16. S3C2500B console uart controller register address r/w description reset value cucon 0xf0060000 r/w console uart control register 0x00000000 custat 0xf0060004 r/w console uart status register 0x00060800 cuint 0xf0060008 r/w console uart interrupt enable register 0x00000000 cutxbuf 0xf006000c w console uart transmit data register ? curxbuf 0xf0060010 r console uart receive data register ? cubrd 0xf0060014 r/w console uart baud rate divisor register 0x0000 cuchar1 0xf0060018 r/w console uart control character register 1 0x00000000 cuchar2 0xf006001c r/w console uart control character register 2 0x00000000 table 1-17. S3C2500B high-speed uart controller 0 register address r/w description reset value hucon 0xf0070000 r/w high-speed uart control register 0x00000000 hustat 0xf0070004 r/w high-speed uart status register ? huint 0xf0070008 r/w high-speed uart interrupt enable register 0x00000000 hutxbuf 0xf007000c w high-speed uart transmit data register ? hurxbuf 0xf0070010 r high-speed uart receive data register ? hubrd 0xf0070014 r/w high-speed uart baud rate divisor register 0x00000000 huchar1 0xf0070018 r/w high-speed uart control character register 1 0x00000000 huchar2 0xf007001c r/w high-speed uart control character register 2 0x00000000 huabb 0xf0070100 r/w high-speed uart autobaud boundary register 0x1f0f0703 huabt 0xf0070104 r/w high-speed uart autobaud table register 0x170b0502 S3C2500B product overview 1- 43 table 1-18. S3C2500B high speed uart controller 1 register address r/w description reset value hucon 0xf0080000 r/w high-speed uart control register 0x00000000 hustat 0xf0080004 r/w high-speed uart status register ? huint 0xf0080008 r/w high-speed uart interrupt enable register 0x00000000 hutxbuf 0xf008000c w high-speed uart transmit data register ? hurxbuf 0xf0080010 r high-speed uart receive data register ? hubrd 0xf0080014 r/w high-speed uart baud rate divisor register 0x00000000 huchar1 0xf0080018 r/w high-speed uart control character register 1 0x00000000 huchar2 0xf008001c r/w high-speed uart control character register 2 0x00000000 huabb 0xf0080100 r/w high-speed uart autobaud boundary register 0x1f0f0703 huabt 0xf0080104 r/w high-speed uart autobaud table register 0x170b0502 table 1-19. S3C2500B i/o port controller register address r/w description reset value iopmode1 0xf0030000 r/w i/o port mode select lower register for port 0 to 31 0xf003ffff iopmode2 0xf0030004 r/w i/o port mode select upper register for port 32 to 63 0xffffffff iopcon1 0xf0030008 r/w i/o port function control register for port 0 to 31 0x0fffff00 iopcon2 0xf003000c r/w i/o port select function control register for port 32 to 63 0x00000000 iopgdma 0xf0030010 r/w i/o port special function register for gdma 0x00000000 iopextint 0xf0030014 r/w i/o port special function register for external interrupt 0x00000000 iopextintpnd 0xf0030018 r/w i/o port external interrupt clear register 0x00000000 iopdata1 0xf003001c r/w i/o port data register for port 0 to 31 undefined iopdata2 0xf0030020 r/w i/o port data register for port 32 to 63 undefined iopdrv1 0xf0030024 r/w i/o port drive control register for port 0 to 31 0x00000000 iopdrv2 0xf0030028 r/w i/o port drive control register for port 32 to 63 0x00000000 product overview S3C2500B 1- 44 table 1-20. S3C2500B interrupt controller register address r/w description reset value intmod 0xf0140000 r/w internal interrupt mode register 0x00000000 extmod 0xf0140004 r/w external interrupt mode register 0x00000000 intmask 0xf0140008 r/w internal interrupt mask register 0xffffffff extmask 0xf014000c r/w external interrupt mask register 0x8000007f intprior0 0xf0140020 r/w interrupt priority register 0 0x03020100 intprior1 0xf0140024 r/w interrupt priority register 1 0x07060504 intprior2 0xf0140028 r/w interrupt priority register 2 0x0b0a0908 intprior3 0xf014002c r/w interrupt priority register 3 0x0f0e0d0c intprior4 0xf0140030 r/w interrupt priority register 4 0x13121110 intprior5 0xf0140034 r/w interrupt priority register 5 0x17161514 intprior6 0xf0140038 r/w interrupt priority register 6 0x1b1a1918 intprior7 0xf014003c r/w interrupt priority register 7 0x1f1e1d1c intprior8 0xf0140040 r/w interrupt priority register 8 0x23222120 intprior9 0xf0140044 r/w interrupt priority register 9 0x00262524 intoffset_fiq 0xf0140018 r fiq interrupt offset register 0x00000027 intoffset_irq 0xf014001c r irq interrupt offset register 0x00000027 ipriorhi 0xf0140010 r high bits, 38-32 bit, interrupt by priority register 0x00000000 ipriorlo 0xf0140014 r low bits, 31-0 bit, interrupt by priority register 0x00000000 inttsthi 0xf0140048 r high bits, 38-7 bit, interrupt test register 0x00000000 inttstlo 0xf014004c r low bits, 6-0 bit, interrupt test register 0x00000000 S3C2500B product overview 1- 45 table 1-21. S3C2500B timer controller register address r/w description reset value tmod 0xf0040000 r/w timer mode register 0x00000000 tic 0xf0040004 r/w timer interrupt clear 0x00000000 wdt 0xf0040008 r/w watchdog timer register 0x00000000 tdata0 0xf0040010 r/w timer 0 data register 0x00000000 tcnt0 0xf0040014 r/w timer 0 count register 0xffffffff tdata1 0xf0040018 r/w timer 1 data register 0x00000000 tcnt1 0xf004001c r/w timer 1 count register 0xffffffff tdata2 0xf0040020 r/w timer 2 data register 0x00000000 tcnt2 0xf0040024 r/w timer 2 count register 0xffffffff tdata3 0xf0040028 r/w timer 3 data register 0x00000000 tcnt3 0xf004002c r/w timer 3 count register 0xffffffff tdata4 0xf0040030 r/w timer 4 data register 0x00000000 tcnt4 0xf0040034 r/w timer 4 count register 0xffffffff tdata5 0xf0040038 r/w timer 5 data register 0x00000000 tcnt5 0xf004003c r/w timer 5 count register 0xffffffff product overview S3C2500B 1- 46 notes S3C2500B programme r s model 2- 1 2 programmer s model 2.1 overview S3C2500B was developed using the advanced arm9tdmi core designed by advanced risc machines, ltd. ? processor operating states from the programmer s point of view, the arm9tdmi can be in one of two states: ? arm state which executes 32-bit, word-aligned arm instructions. ? thumb state which operates with 16-bit, half-word-aligned thumb instructions. in this state, the pc uses bit 1 to select between alternate half-words. note transition between these two states does not affect the processor mode or the contents of the registers. 2.2 switching state 2.2.1 entering thumb state entry into thumb state can be achieved by executing a bx instruction with the state bit (bit 0) set in the operand register. transition to thumb state will also occur automatically on return from an exception (irq, fiq, undef, abort, swi etc.), if the exception was entered with the processor in thumb state. 2.2.2 entering arm state entry into arm state happens: 1. on execution of the bx instruction with the state bit clear in the operand register. 2. on the processor taking an exception (irq, fiq, reset, undef, abort, swi etc.). in this case, the pc is placed in the exception mode s link register, and execution commences at the exception s vector address. programmer s model S3C2500B 2- 2 2.3 memory formats arm9tdmi views memory as a linear collection of bytes numbered upwards from zero. bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. arm9tdmi can treat words in memory as being stored either in big-endian or little-endian format. 2.3.1 big-endian format in big-endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. byte 0 of the memory system is therefore connected to data lines 31 through 24. 31 8 4 0 23 9 5 1 10 6 2 11 7 3 8 7 0 4 0 8 higher address lower address word address most significant byte is at lowest address. word is addressed by byte address of most significant byte. 24 15 16 figure 2-1. big-endian addresses of bytes within words note the data locations in the external memory are different with figure 2-1 in the S3C2500B. please refer to the chapter 4, system manager. 2.3.2 little-endian format in little-endian format, the lowest numbered byte in a word is considered the word s least significant byte, and the highest numbered byte the most significant. byte 0 of the memory system is therefore connected to data lines 7 through 0. 31 23 8 7 0 4 0 8 higher address lower address word address least significant byte is at lowest address. word is addressed by byte address of least significant byte. 24 15 16 8 4 0 9 5 1 10 6 2 11 7 3 figure 2-2. little-endian addresses of bytes words S3C2500B programme r s model 2- 3 2.4 instruction length instructions are either 32 bits long (in arm state) or 16 bits long (in thumb state). 2.5 data types arm9tdmi supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. words must be aligned to four- byte boundaries and half words to two-byte boundaries. 2.6 operating modes arm9tdmi supports seven modes of operation: user (usr): the normal arm program execution state fiq (fiq): designed to support a data transfer or channel process irq (irq): used for general-purpose interrupt handling supervisor (svc): protected mode for the operating system abort mode (abt): entered after a data or instruction prefetch abort system (sys): a privileged user mode for the operating system undefined (und): entered when an undefined instruction is executed mode changes may be made under software control, or may be brought about by external interrupts or exception processing. most application programs will execute in user mode. the non-user modes known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources. programmer s model S3C2500B 2- 4 2.7 registers arm9tdmi has a total of 37 registers-31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. the processor state and operating mode dictate which registers are available to the programmer. 2.7.1 the arm state register set in arm state, 16 general registers and one or two status registers are visible at any one time. in privileged (non- user) modes, mode-specific banked registers are switched in. figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle. the arm state register set contains 16 directly accessible registers: r0 to r15. all of these except r15 are general-purpose, and may be used to hold either data or address values. in addition to these, there is a seventeenth register used to store status information. register 14 is used as the subroutine link register. this receives a copy of r15 when a branch and link (bl) instruction is executed. at all other times it may be treated as a general-purpose register. the corresponding banked registers r14_svc, r14_irq, r14_fiq, r14_abt and r14_und are similarly used to ho ld the return values of r15 when interrupts and exceptions arise, or when branch and link instructions are executed within interrupt or exception routines. register 15 holds the program counter (pc). in arm state, bits [1:0] of r15 are zero and bits [31:2] contain the pc. in thumb state, bit [0] is zero and bits [31:1] contain the pc. register 16 is the cpsr (current program status register). this contains condition code flags and the current mode bits. fiq mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). in arm state, many fiq handlers do not need to save any registers. user, irq, supervisor, abort and undefined each have two banked registers mapped to r13 and r14, allowing each of these modes to have a private stack pointer and link registers. S3C2500B programme r s model 2- 5 cpsr cpsr spsr_fiq cpsr spsr_svc cpsr spsr_abt cpsr spsr_irq cpsr spsr_und system & user fiq supervisor about irq undefined arm state program status register = banked register arm state general registers and program counter r0 r1 r2 r3 r4 r5 r6 r7 r10 r8 r9 r11 r12 r15 (pc) r13_und r14_und r0 r1 r2 r3 r4 r5 r6 r7 r10 r8 r9 r11 r12 r15 (pc) r13_irq r14_irq r0 r1 r2 r3 r4 r5 r6 r7 r10 r8 r9 r11 r12 r15 (pc) r13_abt r14_abt r10 r8 r9 r11 r12 r15 (pc) r13_svc r14_svc r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (pc) figure 2-3. register organization in arm state programmer s model S3C2500B 2- 6 2.7.2 the thumb state register set the thumb state register set is a subset of the arm state set. the programmer has direct access to eight general registers, r0?r7, as well as the program counter (pc), a stack pointer register (sp), a link register (lr), and the cpsr. there are banked stack pointers, link registers and saved process status registers (spsrs) for each privileged mode. this is shown in figure 2-4. cpsr cpsr spsr_fiq cpsr spsr_svc cpsr spsr_abt cpsr spsr_irq cpsr spsr_und system & user fiq supervisor about irq undefined thumb state program status registers = banked register thumb state general registers and program counter r0 r1 r2 r3 r4 r5 r6 r7 sp lr pc sp_fiq lr_fiq r0 r1 r2 r3 r4 r5 r6 r7 pc sp_svg lr_svc r0 r1 r2 r3 r4 r5 r6 r7 pc sp_abt lr_abt r0 r1 r2 r3 r4 r5 r6 r7 pc sp_irq lr_irq r0 r1 r2 r3 r4 r5 r6 r7 pc sp_und lr_und r0 r1 r2 r3 r4 r5 r6 r7 pc figure 2-4. register organization in thumb state S3C2500B programme r s model 2- 7 2.7.3 the relationship between arm and thumb state registers the thumb state registers relate to the arm state registers in the following way: ? thumb state r0?r7 and arm state r0?r7 are identical ? thumb state cpsr and spsrs and arm state cpsr and spsrs are identical ? thumb state sp maps onto arm state r13 ? thumb state lr maps onto arm state r14 the thumb state program counter maps onto the arm state program counter (r15) this relationship is shown in figure 2-5. r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r5 r6 r7 r8 r9 r10 r11 r12 stack pointer (r13) link register (r14) program counter (r15) cpsr spsr stack pointer (sp) link register (lr) program counter (pc) cpsr spsr thumb state arm state lo-registers hi-registers r4 figure 2-5. mapping of thumb state registers onto arm state registers programmer s model S3C2500B 2- 8 2.7.4 accessing hi-registers in thumb state in thumb state, registers r8?r15 (the hi registers) are not part of the standard register set. however, the assembly language programmer has limited access to them, and can use them for fast temporary storage. a value may be transferred from a register in the range r0?r7 (a lo register) to a hi register, and from a hi register to a lo register, using special variants of the mov instruction. hi register values can also be compared against or added to lo register values with the cmp and add instructions. for more information, refer to figure 3-34. 2.8 the program status registers the arm9tdmi contains a current program status register (cpsr), plus five saved program status registers (spsrs) for use by exception handlers. these register s functions are: ? hold information about the most recently performed alu operation ? control the enabling and disabling of interrupts ? set the processor operating mode the arrangement of bits is shown in figure 2-6. n z c v . . . . . . i f t m4 m3 m2 m1 m0 31 30 29 28 27 26 25 24 8 7 6 5 4 3 2 1 0 condition code flags (reserved) control bits overflow carry/borrow/extend zero negative/less than mode bits state bit fiq disable frq disable figure 2-6. program status register format S3C2500B programme r s model 2- 9 2.8.1 the condition code flags the n, z, c and v bits are the condition code flags. these may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. in arm state, all instructions may be executed conditionally: see table 3-2 for details. in thumb state, only the branch instruction is capable of conditional execution: see figure 3-46 for details. 2.8.2 the control bits the bottom 8 bits of a psr (incorporating i, f, t and m[4:0]) are known collectively as the control bits. these will change when an exception arises. if the processor is operating in a privileged mode, they can also be manipulated by software. the t bit this reflects the operating state. when this bit is set, the processor is executing in thumb state, otherwise it is executing in arm state. this is reflected on the tbit external signal. note that the software must never change the state of the tbit in the cpsr. if this happens, the processor will enter an unpredictable state. interrupt disable bits the i and f bits are the interrupt disable bits. when set, these disable the irq and fiq interrupts respectively. the mode bits the m4, m3, m2, m1 and m0 bits (m[4:0]) are the mode bits. these determine the processor s operating mode, as shown in table 2-1. not all combinations of the mode bits define a valid processor mode. only those explicitly described shall be used. the user should be aware that if any illegal value is programmed into the mode bits, m[4:0], then the processor will enter an unrecoverable state. if this occurs, reset should be applied. programmer s model S3C2500B 2- 10 table 2-1. psr mode. bit values m[4:0] mode visible thumb state registers visible arm state registers 10000 user r7..r0, lr, sp pc, cpsr r14..r0, pc, cpsr 10001 fiq r7..r0, lr_fiq, sp_fiq pc, cpsr, spsr_fiq r7..r0, r14_fiq..r8_fiq, pc, cpsr, spsr_fiq 10010 irq r7..r0, lr_irq, sp_irq pc, cpsr, spsr_irq r12..r0, r14_irq..r13_irq, pc, cpsr, spsr_irq 10011 supervisor r7..r0, lr_svc, sp_svc, pc, cpsr, spsr_svc r12..r0, r14_svc..r13_svc, pc, cpsr, spsr_svc 10111 abort r7..r0, lr_abt, sp_abt, pc, cpsr, spsr_abt r12..r0, r14_abt..r13_abt, pc, cpsr, spsr_abt 11011 undefined r7..r0 lr_und, sp_und, pc, cpsr, spsr_und r12..r0, r14_und..r13_und, pc, cpsr 11111 system r7..r0, lr, sp pc, cpsr r14..r0, pc, cpsr reserved bits the remaining bits in the psrs are reserved. when changing a psr s flag or control bits, you must ensure that these unused bits are not altered. also, your program should not rely on them containing specific values, since in future processors they may read as one or zero. S3C2500B programme r s model 2- 11 2.9 exceptions exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. it is possible for several exceptions to arise at the same time. if this happens, they are dealt with in a fixed order. see exception priorities on page 2-15. 2.9.1 action on entering an exception when handling an exception, the arm9tdmi: 1. preserves the address of the next instruction in the appropriate link register. if the exception has been entered from arm state, then the address of the next instruction is copied into the link register (that is, current pc + 4 or pc + 8 depending on the exception. see table 2-2 on for details). if the exception has been entered from thumb state, then the value written into the link register is the current pc offset by a value such that the program resumes from the correct place on return from the exception. this means that the exception handler need not determine which state the exception was entered from. for example, in the case of swi, movs pc, r14_svc will always return to the next instruction regardless of whether the swi was executed in arm or thumb state. 2. copies the cpsr into the appropriate spsr 3. forces the cpsr mode bits to a value which depends on the exception 4. forces the pc to fetch the next instruction from the relevant exception vector it may also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. if the processor is in thumb state when an exception occurs, it will automatically switch into arm state when the pc is loaded with the exception vector address. 2.9.2 action on leaving an exception on completion, the exception handler: 1. moves the link register, minus an offset where appropriate, to the pc. (the offset will vary depending on the type of exception.) 2. copies the spsr back to the cpsr 3. clears the interrupt disable flags, if they were set on entry note an explicit switch back to thumb state is never needed, since restoring the cpsr from the spsr automatically sets the t bit to the value it held immediately prior to the exception. programmer s model S3C2500B 2- 12 2.9.3 exception entry/exit summary table 2-2 summarizes the pc value preserved in the relevant r14 on exception entry, and the recommended instruction for exiting the exception handler. table 2-2. exception entry/exit return instruction previous state notes arm r14_x thumb r14_x bl mov pc, r14 pc + 4 pc + 2 1 swi movs pc, r14_svc pc + 4 pc + 2 1 udef movs pc, r14_und pc + 4 pc + 2 1 fiq subs pc, r14_fiq, #4 pc + 4 pc + 4 2 irq subs pc, r14_irq, #4 pc + 4 pc + 4 2 pabt subs pc, r14_abt, #4 pc + 4 pc + 4 1 dabt subs pc, r14_abt, #8 pc + 8 pc + 8 3 reset na ? ? 4 notes: 1. where pc is the address of the bl/swi/undefined instruction fetch which had the prefetch abort. 2. where pc is the address of the instruction which did not get executed since the fiq or irq took priority. 3. where pc is the address of the load or store instruction which generated the data abort. 4. the value saved in r14_svc upon reset is unpredictable. 2.9.4 fiq the fiq (fast interrupt request) exception is designed to support a data transfer or channel process, and in arm state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context switching). fiq is externally generated by taking the nfiq input low. this input can except either synchronous or asynchronous transitions, depending on the state of the isync input signal. when isync is low, nfiq and nirq are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow. irrespective of whether the exception was entered from arm or thumb state, a fiq handler should leave the interrupt by executing subs pc,r14_fiq,#4 fiq may be disabled by setting the cpsr's f flag (but note that this is not possible from user mode). if the f flag is clear, arm9tdmi checks for a low level on the output of the fiq synchroniser at the end of each instruction. S3C2500B programme r s model 2- 13 2.9.5 irq the irq (interrupt request) exception is a normal interrupt caused by a low level on the nirq input. irq has a lower priority than fiq and is masked out when a fiq sequence is entered. it may be disabled at any time by setting the i bit in the cpsr, though this can only be done from a privileged (non-user) mode. irrespective of whether the exception was entered from arm or thumb state, an irq handler should return from the interrupt by executing subs pc,r14_irq,#4 2.9.6 abort an abort indicates that the current memory access cannot be completed. it can be signalled by the external abort input. arm9tdmi checks for the abort exception during memory access cycles. there are two types of abort: ? prefetch abort: occurs during an instruction prefetch. ? data abort: occurs during a data access. if a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. if the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place. if a data abort occurs, the action taken depends on the instruction type: ? single data transfer instructions (ldr, str) write back modified base registers: the abort handler must be aware of this. ? the swap instruction (swp) is aborted as though it had not been executed. ? block data transfer instructions (ldm, stm) complete. if write-back is set, the base is updated. if the instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. all register overwriting is prevented after an abort is indicated, which means in particular that r15 (always the last register to be transferred) is preserved in an aborted ldm instruction. the abort mechanism allows the implementation of a demand paged virtual memory system. in such a system the processor is allowed to generate arbitrary addresses. when the data at an address is unavailable, the memory management unit (mmu) signals an abort. the abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. the application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort. after fixing the reason for the abort, the handler should execute the following irrespective of the state (arm or thumb): subs pc,r14_abt,#4 ; for a prefetch abort, or subs pc,r14_abt,#8 ; for a data abort this restores both the pc and the cpsr, and retries the aborted instruction. programmer s model S3C2500B 2- 14 2.9.7 software interrupt the software interrupt instruction (swi) is used for entering supervisor mode, usually to request a particular supervisor function. a swi handler should return by executing the following irrespective of the state (arm or thumb): mov pc,r14_svc this restores the pc and cpsr, and returns to the instruction following the swi. note nfiq, nirq, isync, lock, bigend, and abort pins exist only in the arm9tdmi cpu core. 2.9.8 undefined instruction when arm9tdmi comes across an instruction which it cannot handle, it takes the undefined instruction trap. this mechanism may be used to extend either the thumb or arm instruction set by software emulation. after emulating the failed instruction, the trap handler should execute the following irrespective of the state (arm or thumb): movs pc,r14_und this restores the cpsr and returns to the instruction following the undefined instruction. 2.10 exception vectors the following table shows the exception vector addresses. table 2-3. exception vectors address exception mode in entry 0x00000000 reset supervisor 0x00000004 undefined instruction undefined 0x00000008 software interrupt supervisor 0x0000000c abort (prefetch) abort 0x00000010 abort (data) abort 0x00000014 reserved reserved 0x00000018 irq irq 0x0000001c fiq fiq S3C2500B programme r s model 2- 15 2.10.1 exception priorities when multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: highest priority: 1. reset 2. data abort 3. fiq 4. irq 5. prefetch abort lowest priority: 6. undefined instruction, software interrupt. 2.10.2 not all exceptions can occur at once: undefined instruction and software interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decoding of the current instruction. if a data abort occurs at the same time as a fiq, and fiqs are enabled (ie the cpsr's f flag is clear), arm9tdmi enters the data abort handler and then immediately proceeds to the fiq vector. a normal return from fiq will cause the data abort handler to resume execution. placing data abort at a higher priority than fiq is necessary to ensure that the transfer error does not escape detection. the time for this exception entry should be added to worst-case fiq latency calculations. programmer s model S3C2500B 2- 16 2.11 interrupt latencies the worst case latency for fiq, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser ( tsyncmax if asynchronous), plus the time for the longest instruction to complete ( tldm , the longest instruction is an ldm which loads all the registers including the pc), plus the time for the data abort entry ( texc ), plus the time for fiq entry ( tfiq ). at the end of this time arm9tdmi will be executing the instruction at 0x1c. tsyncmax is 3 processor cycles, tldm is 20 cycles, texc is 3 cycles, and tfiq is 2 cycles. the total time is therefore 28 processor cycles. this is just over 1.4 microseconds in a system which uses a continuous 20 mhz processor clock. the maximum irq latency calculation is similar, but must allow for the fact that fiq has higher priority and could delay entry into the irq handling routine for an arbitrary length of time. the minimum latency for fiq or irq consists of the shortest time the request can take through the synchroniser (tsyncmin) plus tfiq . this is 4 processor cycles. 2.12 reset when the nreset signal goes low, arm9tdmi abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. when nreset goes high again, arm9tdmi: 1. overwrites r14_svc and spsr_svc by copying the current values of the pc and cpsr into them. the value of the saved pc and spsr is not defined. 2. forces m[4:0] to 10011 (supervisor mode), sets the i and f bits in the cpsr, and clears the cpsr's t bit. 3. forces the pc to fetch the next instruction from address 0x00. 4. execution resumes in arm state. S3C2500B programme r s model 2- 17 2.13 introduction for arm940t the arm940t cached processor macrocell is a member of the arm9 thumb family of high-performance 32-bit system-on-a-chip processor solutions. it is targeted at a wide range of embedded control applications where high performance, low system cost, small die size, and low power are key considerations. the arm940t processor macrocell provides a complete high performance cpu subsystem, including arm9tdmi risc integer cpu, caches, write buffer, and protection unit, with an amba asb bus interface. providing a complete high-frequency cpu subsystem frees the system-on-a-chip designer to concentrate on design issues unique to their system. the arm9tdmi core within the arm940t macrocell executes both the 32-bit arm and 16-bit thumb instruction sets, allowing the user to trade off between high performance and high code density. it is binary compatible with arm7tdmi, arm10tdmi, and strongarm processors, and is supported by a wide range of tools, operating systems, and application software. the arm940t processor macrocell is designed to be integrated into larger chips. it supports embeddedice software and hardware debug and efficient production test when embedded in larger devices. the advanced microcontroller bus architecture (amba) provides a high performance 32-bit system bus (asb) and a low power peripheral bus (apb). the asb is re-used to provide a channel for production test vectors with low silicon and pin overhead. the asb is a multi-master on-chip bus interface designed specifically to address the needs of system- on-a-chip designs. the embeddedice software and hardware debug features of the arm940t macrocell are accessed via a standard 5-pin jtag port, and are supported by arm's software development toolkit and multi-ice interface hardware. the embeddedice features allow software download and debug of the final production system with no cost overhead (there is no monitor code or other use of target resident ram or rom). the arm940t processor has a harvard cache architecture with separate 4kb instruction and 4kb data caches, each with a 4-word line length. a protection unit allows 8 regions of memory to be defined, each with individual cache and write buffer configurations and access permissions. the cache system is software configurable to provide highest average performance or to meet the needs of real-time systems. software configurable options include: random or round robin replacement algorithm write-through or write-back cache operation (independently selectable for each memory region) cache locking with granularity 1/64 th of cache size. overall, the cache and write buffers improve cpu performance and minimize accesses to the amba bus and to any off-chip memory, thus reducing overall system power consumption. the arm940t includes support for coprocessors, allowing a floating point unit or other application specific hardware acceleration to be added. to minimize die size and power consumption the arm940t does not provide virtual to physical address mapping as this is not required in most embedded applications. for systems requiring virtual memory capability, arm provides an alternative product, the arm920t cached processor macrocell. the arm940t also features a trackingice mode which allows an approach similar to a conventional ice mode of operation. programmer s model S3C2500B 2- 18 2.14 arm940t block diagram coprocessor interface protection unit cp15 arm9tdmi processor core (integral embeddedice) amba interface instruction cache 4k i cache control data cache 4k d cache control cpid[31:0] cpdin[31:0] cpdout[31:0] ba[31:0] bcontrol bd[31:0] da[31:0] dd[31:0] ia[31:0] id[31:0] jtag interface[4:0] figure 2-7. arm940t block diagram S3C2500B programme r s model 2- 19 2.15 about the arm940t programmer's model the arm940t cached processor macrocell includes the arm9tdmi microprocessor core, instruction and data caches, a write-buffer, and a protection unit for defining the attributes of regions of memory. the arm940t incorporates two coprocessors: cp14 which allows software access to the debug communications channel cp15 which allows configuration of the caches, protection unit, and other system options such as big or little endian operation. the arm940t also features an external coprocessor interface which allows the attachment of a closely coupled coprocessor on the same chip, for example, a floating point unit. the programmer's model of the arm940t consists of the programmer's model of the arm9tdmi with the following additions and modifications: memory accesses for instruction fetches and data loads and stores may be cached or buffered. cache and write buffer configuration and operation is described in detail in following chapters. the registers defined in cp14 are accessible with mcr and mrc instructions. these are described in debug communications channel on page 8-46. the registers defined in cp15 are accessible with mcr and mrc instructions. these are described in arm940t cp15 registers on page 2-5. registers and operations provided by any coprocessors attached to the external coprocessor interface will be accessible with appropriate coprocessor instructions. the arm9tdmi processor core implements arm architecture v4t, and so executes the arm 32-bit instruction set and the compressed thumb 16-bit instruction set. the programmer's model is fully described in the arm architecture reference manual. the arm v4t architecture specifies a small number of implementation options. the options selected in the arm9tdmi implementation are listed in table 2-4. for comparison, the options selected for the arm9tdmi implementation are also shown. table 2-4. arm9tdmi implementation option processor core arm architecture data abort mode value stored by direct str, strt, stm of pc arm7tdmi v4t base updatd address of inst + 12 arm9tdmi v4t base restored address of inst + 12 the arm9tdmi is code-compatible with the arm7tdmi, with two exceptions: the arm9tdmi implements the base restored data abort model, which significantly simplifies the software data abort handler. the arm9tdmi fully implements the instruction set extension spaces added to the arm (32-bit) instruction set in architecture v4 and v4t. these differences are explained in more detail below. programmer s model S3C2500B 2- 20 2.15.1 data abort model the base restored data abort model differs from the base updated data abort model implemented by arm7tdmi. the difference in the data abort model affects only a very small section of operating system code, the data abort handler. it does not affect user code. with the base restored data abort model, when a data abort exception occurs during the execution of a memory access instruction, the base register is always restored by the processor hardware to the value the register contained before the instruction was executed. this removes the need for the data abort handler to unwind any base register update which may have been specified by the aborted instruction. the base restored data abort model significantly simplifies the software data abort handler. 2.15.2 instruction set extension spaces all arm processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception. that is, arm instructions with opcode[27:25] = 0b011 and opcode[4] = 1 are undefined on all arm processors including the arm9tdmi and arm7tdmi. arm architecture v4 and v4t also introduced a number of instruction set extension spaces to the arm instruction set. these are: arithmetic instruction extension space control instruction extension space coprocessor instruction extension space load/store instruction extension space. instructions in these spaces are undefined (they cause an undefined instruction exception). the arm9tdmi fully implements all the instruction set extension spaces defined in arm architecture v4t as undefined instructions, allowing emulation of future instruction set additions. S3C2500B programme r s model 2- 21 2.16 arm940t cp15 registers 2.16.1 cp15 register map summary the arm940t incorporates cp15 for system control. the register map for c15 is shown in table 2-5. table 2-5. cp15 register map register function access 0 id code/cache type see note below 1 control read/write 2 cacheable see note below 3 write buffer control read/write 4 reseved undefined 5 protection region access permissions see note below 6 protection region base/size control see note below 7 cache operations write only. reads unpredictable 8 reserved undefined 9 cache lockdown read/write 10:14 reserved undefined 15 test not accessed in normal operations note: register locations 0, 2, 5, and 6 each provide access to more than one register. the register accessed depends upon the value of the opcode_2 field. see the register descriptions that follow for further information. 2.16.1.1 register 0: id code this is a read-only register which returns a 32-bit device id code. the id code register is accessed by reading cp15 register 0 with the opcode_2 field set to any value other than 1. for example: mrc p15, 0, rd, c0, c0,{0,2-7}; returns id register the contents of the id code are shown in table 2-6. table 2-6. id code register register bits function value 31:12 implementor 0x41 (identifies arm) 23:16 architecture version 0x2 15:4 part number 0x940 3:0 version 0x1 programmer s model S3C2500B 2- 22 2.16.1.2 register 0: cache type this is a read-only register which allows operating systems to establish how to perform operations such as cache cleaning and lockdown. future arm cached processors will contain this register, allowing rtos vendors to produce future-proof versions of their operating systems. the cache type register is accessed by reading cp15 register 0 with the opcode_2 field set to 1. for example: mrc p15, 0, rd, c0, c0, 1; returns cache type register the register contains information about the size and architecture of the caches. the format of the register is shown in table 2-7. table 2-7. cache type register format register bits meaning value 31:29 reserved 000 28:25 cache type 0111 24 harvard/unified 1 (defines harvard cache) 23:21 reserved 000 20:18 dcache size 011 (defines 4kb) 17:15 dcache associativity 110 (defines 64 way) 14 dcache base size 0 (defines 1x base parameters) 13:12 dcache words per line 01 (defines 4 words per line) 11:9 reserved 000 8:6 icache size 011 (defines 4kb) 5:3 icache associativity 110 (defines 64 way) 2 icache base size 0 (defines 1x base parameters) 1:0 icache words per line 01 (defines 4 words per line) S3C2500B programme r s model 2- 23 2.16.1.3 register 1: control register this contains the global control bits of the arm940t. all reserved bits should either be written with zero or one, as indicated, or written using read-modify-write. the reserved bits have an unpredictable value when read. all defined bits in the control register are set to zero at reset. table 2-8. cp15 register 1 register bits functions 31 asynchronous clocking select (ia) 30 nfastbus select (nf) 29:14 reserved (should be zero) 13 alternate vectors select (v) 12 icache enable bit (1) 11:8 reserved (should be zero) 7 big-end bit (e) 6:3 reserved (should be one) 2 dcache enable bit (d) 1 reserved (should be zero) 0 protection unit enable (p) the bits in the control register have the following functions: bits 31:30 control the clocking mode of the processor, as shown in table 2-9. clocking modes are discussed in chapter5 clock modes. table 2-9. clocking modes clockin mode bit 31 bit 30 fastbus mode 0 0 reserved 1 0 synchronous 0 1 asynchronous 1 1 bit 13 selects the location of the vector table. during reset, the bit is cleared and the vector table is located at address 0x00000000. when bit 13 is set, the vector table is relocated to address 0xffff0000. bits 12 and 2 enable the caches (see chapter4 caches and write buffer). bit 7 selects the endian configuration of the arm940t. setting bit 7 selects a big-endian configuration . clearing bit 7 selects a little-endian configuration. bit 7 is cleared during reset. bit 0 enables the protection unit (see chapter4 caches and write buffer). programmer s model S3C2500B 2- 24 2.16.1.4 register 2: instruction and data cacheable registers this location provides access to two registers which contain the cacheable attributes for each of eight memory areas. the two registers provide individual control for the i and d address spaces. the opcode_2 field determines whether the instruction-or data-cacheable attributes are programmed: if the opcode_2 field = 0, the data-cacheable bits are programmed. for example: mcr p15,0,rd,c2,c0,0; write data-cacheable bits mrc p15,0,rd,c2,c0,0; read data-cacheable bits if the opcode_2 field = 1 the instruction-cacheable bits are programmed. for example: mcr p15,0,rd,c2,c0,1; write instruction cacheable bits mrc p15,0,rd,c2,c0,1; read instruction cacheable bits the format for the data and instruction cacheable bits is similar, as shown in table 2-10. setting a bit makes an area cacheable, clearing it makes it non-cacheable. all defined bits in the control register are set to zero at reset. table 2-10. cacheable register format register bits functions 7 cacheable bit (c_7) for area 7 6 cacheable bit (c_6) for area 6 5 cacheable bit (c_5) for area 5 4 cacheable bit (c_4) for area 4 3 cacheable bit (c_3) for area 3 2 cacheable bit (c_2) for area 2 1 cacheable bit (c_1) for area 1 0 cacheable bit (c_0) for area 0 S3C2500B programme r s model 2- 25 2.16.1.5 register 3: write buffer control register this register contains a write buffer control (bufferable) attribute bit for each of the eight areas of memory. each bit is used in conjunction with the cacheable bit to control write-buffer operation. for a description of buffer behavior, see the write buffer on page 4-11. setting a bit makes an area bufferable, clearing a bit makes an area unbuffered. for example: mcr p15,0,rd,c3,c0,0; write data-bufferable bits mrc p15,0,rd,c3,c0,0; read data-bufferable bits note the opcode_2 field should be 0 because the write buffer only operates on data regions. the following table, therefore, only applies to the dcache. all defined bits in the control register are set to zero at reset. table 2-11. write buffer control register register bits functions 7 write buffer control bit (b_d7) for data area 7 6 write buffer control bit (b_d6) for data area 6 5 write buffer control bit (b_d5) for data area 5 4 write buffer control bit (b_d4) for data area 4 3 write buffer control bit (b_d3) for data area 3 2 write buffer control bit (b_d2) for data area 2 1 write buffer control bit (b_d1) for data area 1 0 write buffer control bit (b_d0) for data area 0 2.16.1.6 register 5: instruction and data space protection registers these registers contain the access permission bits for the instruction and data protection regions. the opcode_2 field determines whether the instruction or data access permissions are programmed. if the opcode_2 field = 0, the data space bits are programmed. for example: mcr p15,0,rd,c5,c0,0; write data space access permissions mcr p15,0,rd,c5,c0,0; read data space access permissions if the opcode_2 field =1, the instruction space bits are programmed. for example: mcr p15,0,rd,c5,c0,1; write instruction space access permissions mrc p15,0,rd,c5,c0,1; read instruction space access permissions programmer s model S3C2500B 2- 26 each register contains the access permission bits, apn[1:0], for the eight areas of instruction or data memory, as shown in table 2-12. all defined bits in the control register are set to zero at reset. table 2-12. protection space register format register bits functions 15:14 ap7[1:0] bits of area 7 13:12 ap6[1:0] bits of area 6 11:10 ap5[1:0] bits of area 5 9:8 ap4[1:0] bits of area 4 7:6 ap3[1:0] bits of area 3 5:4 ap2[1:0] bits of area 2 3:2 ap1[1:0] bits of area 1 1:0 ap0[1:0] bits of area 0 the values of the iapn[1:0] and dapn[1:0] bits define the access permission for each area of memory. the encoding is shown in table 2-13. note on reset, the values of the iapn[1:0] and dapn[1:0] bits for all areas are undefined. however, as on reset, the protection unit is disabled and all areas are effectively set to no access. the protection space registers therefore, must be programmed before the protection unit is enabled. table 2-13. permission encoding i/dapn[1:0] permission 00 no access. 01 privileged mode access only. 10 privileged mode full access, user mode read only. 11 full access. S3C2500B programme r s model 2- 27 2.16.1.7 register 6: protection region base and size registers this register is used to define 16 programmable regions (eight instruction, eight data) in memory. these registers define the base and size of each of the eight areas of memory. individual control is provided for the instruction and data memory regions. the values are ignored when the protection unit is disabled. on reset, only the region enable bit for each region is reset to 0, all other bits are undefined. at least one instruction and data memory region must be programmed before the protection unit is enabled. the opcode_2 field defines whether the data or instruction protection regions are to be programmed. the crm field selects the region number. table 2-14. cp15 data protection region registers arm instruction protection region register mcr/mrc p15, 0, rd, c6, c7, 0 data memory region 7 mcr/mrc p15, 0, rd, c6, c6, 0 data memory region 6 mcr/mrc p15, 0, rd, c6, c5, 0 data memory region 5 mcr/mrc p15, 0, rd, c6, c4, 0 data memory region 4 mcr/mrc p15, 0, rd, c6, c3, 0 data memory region 3 mcr/mrc p15, 0, rd, c6, c2, 0 data memory region 2 mcr/mrc p15, 0, rd, c6, c1, 0 data memory region 1 mcr/mrc p15, 0, rd, c6, c0, 0 data memory region 0 table 2-15. cp15 instruction protection region registers arm instruction protection region register mcr/mrc p15, 0, rd, c6, c7, 1 instruction memory region 7 mcr/mrc p15, 0, rd, c6, c6, 1 instruction memory region 6 mcr/mrc p15, 0, rd, c6, c5, 1 instruction memory region 5 mcr/mrc p15, 0, rd, c6, c4, 1 instruction memory region 4 mcr/mrc p15, 0, rd, c6, c3, 1 instruction memory region 3 mcr/mrc p15, 0, rd, c6, c2, 1 instruction memory region 2 mcr/mrc p15, 0, rd, c6, c1, 1 instruction memory region 1 mcr/mrc p15, 0, rd, c6, c0, 1 instruction memory region 0 programmer s model S3C2500B 2- 28 each protection region register has the format shown in table 2-16. table 2-16. cp15 protection region register format register bit function 31:12 base address 11:6 unused 5:1 area size (see table 2-17) 0 region enable. reset to disable (0). the region base must be aligned to an area size boundary, where the area size is defined in its respective protection region register. the behavior is undefined if this is not the case. area sizes are given in table 2-17. table 2-17. area size encoding bit encoding area size bit encoding area size 00000 to 01010 reserved 10101 4mb 01011 4kb 10110 8mb 01100 8kb 10111 16mb 01101 16kb 11000 32mb 01110 32kb 11001 64mb 01111 64kb 11010 128mb 10000 128kb 11011 256mb 10001 256kb 11100 512mb 10010 512kb 11101 1gb 10011 1mb 11110 2gb 10100 2mb 11111 4gb 2.16.1.7.1 example base setting an 8kb size region aligned to the 8kb boundary at 0x00002000 (covering the address range 0x00002000? 0x00003fff) would be programmed to 0x00002019. S3C2500B programme r s model 2- 29 2.16.1.8 register 7: cache operations a write to this register can be used to perform the following operations: flush icache and dcache prefetch an icache line wait for interrupt drain the write buffer clean and flush the dcache. the arm940t uses a subset of the architecture v4 functions (defined in the arm architecture reference manual). the available operations are summarized in table 2-18 and described below. table 2-18. cache operations writing to register 7 arm instruction data protection region register mcr p15, 0, rd, c7, c5, 0 should be zero flush icache mcr p15, 0, rd, c7, c5, 2 index/segment flush icache single entry mcr p15, 0, rd, c7, c6, 0 should be zero flush dcache mcr p15, 0, rd, c7, c6, 2 index/segment flush dcache single entry mcr p15, 0, rd, c7, c10, 2 index/segment clean dcache single entry mcr p15, 0, rd, c7, c13, 1 address prefetch icache line mcr p15, 0, rd, c7, c14, 2 index/segment clean and flush dcache single entry mcr p15, 0, rd, c7, c8, 2 should be zero wait for interrupt mcr p15, 0, rd, c7, c10, 4 should be zero drain write buffer "should be zero" means the value transferred in the rd. a read from this register returns an unpredictable value. programmer s model S3C2500B 2- 30 2.16.1.8.1 index/segment format where the required value is an index/segment, the format is: table 2-19. cp15 register 7 index/segment data format rd bit position function 31:26 index 25:6 should be zero 5:4 segment 3:0 should be zero 2.16.1.8.2 icache prefetch data format for the icache prefetch operation, the data format is: table 2-20. cp15 register 7 prefetch address format rd bit position function 31:6 address bits 31:6 5:4 cache segment 3:0 should be zero 2.16.1.8.3 wait for interrupt this operation allows the arm940t to be placed in a low-power standby mode. when the operation is invoked, all clocks in the processor are frozen until either an interrupt or a debug request occurs. this function is invoked by a write to register 7. the following arm instruction causes this to occur: mcr p15, 0, rd, c7, c0, 4 the following instruction causes the same affect and has been added for backward compatibility with strongarm sa-1 mcr p15, 0, rd, c15, c8, 2 this stalls the processor, with internal clocks held high from the time that this instruction is executed until one of the signals nfiq, nirq, or edbgrq is asserted. also, if the debugger sets the debug request bit in the embeddedice unit control register, the wait-for-interrupt condition is terminated. in the case of nfiq and nirq, the processor is woken up regardless of whether the interrupts are enabled or disabled (that is, independent of the i and f bits in the processor cpsr). the debug related waking only occurs if dbgen is high, that is, only when debug is enabled. if the interrupts are enabled, the arm is guaranteed to take the interrupt before executing the instruction after the wait-for-interrupt. if debug request is used to wake up the system, the processor will enter debug-state before executing any further instructions. S3C2500B programme r s model 2- 31 2.16.1.8.4 drain write buffer this cp15 operation causes instruction execution to be stalled until the write buffer is emptied. this operation is useful in real time applications where the processor needs to be sure that a write to a peripheral has completed before program execution continues. an example would be where a peripheral in a bufferable region is the source of an interrupt. once the interrupt has been serviced, the request must be removed before interrupts can be re-enabled. this can be ensured if a drain write buffer operation separates the store to the peripheral and the enable interrupt functions. the drain write buffer function is invoked by a write to cp15 register 7 using the following arm instruction: mcr p15, 0, rd, c7, c10, 4 this stalls the processor core, with cpnwait asserted until any outstanding accesses in the write buffer have been completed (that is, until all data has been written to memory). 2.16.1.9 register 9: instruction and data lockdown registers these registers allow regions of the cache to be locked down. the opcode_2 field determines whether the instruction or data caches are programmed. if the opcode_2 field = 0, the data lockdown bits are programmed. for example: mcr/mrc p15, 0, rd, c9, c0, 0; data lockdown control if the opcode_2 field = 1, the instruction lockdown bits are programmed. for example: mcr/mrc p15, 0, rd, c9, c0, 1; instruction lockdown control the format of the registers, rd, transferred during this operation, is shown below: all defined bits in the control register are set to zero at reset. table 2-21. lockdown register format register bit function 31 load bit 30:6 reserved 5:0 cache index note: the segment number is not specified because cache lines are locked down across all four segments (16-word granularity). programmer s model S3C2500B 2- 32 2.16.1.10 register 15: test/debug register the dtrrobin and itrrobin bits set the respective caches into a pseudo round-robin replacement mode. all defined bits in the control register are set to zero at reset. table 2-22. cp15 register 15 register bit function 31:4 reserved 3 itrrobin 2 dtrrobin 1:0 reserved 2.16.1.11 reserved registers accessing a reserved register is unpredictable. S3C2500B instruction set 3- 1 3 instruction set 3.1 instruction set summay this chapter describes the arm instruction set and the thumb instruction set in the arm9tdmi core. 3.1.1 format summary the arm instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data processing/ psr transfer multiply multiply long single data swap branch and exchange halfword data transfer: register offset halfword data transfer: immediate offset block data transfer branch coprocessor data transfer coprocessor data operation coprocessor register transfer software interrupt undefined single data transfer cond 1 1 1 1 ignored by processor cond 1 1 1 0 crn rd cp opc l cp# cp# 1 crm cond 1 1 1 0 crn crd cp opc cp# cp# 0 crm cond 1 1 0 p u n w l rn crd cp# offset cond 1 0 1 l offset cond 1 0 0 p u s w l rn register list cond 0 1 1 1 cond 0 1 1 p u b w l rn rd offset cond 0 0 0 p u 1 w l rn rd offset 1 s h 1 offset cond 0 0 0 p u 0 w l rn rd 0 0 0 0 1 s h 1 rm cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 rn cond 0 0 0 1 0 b 0 0 rn rd rm 0 0 0 0 1 0 0 1 cond 0 0 0 0 1 u a s rdhi rnlo rn 1 0 0 1 rm cond 0 0 0 0 0 0 a s rd rn rs 1 0 0 1 rm cond 0 0 1 opcode s rn rd operand2 figure 3-1. arm instruction set format note some instruction codes are not defined but do not cause the undefined instruction trap to be taken, for instance a multiply instruction with bit 6 changed to a 1. these instructions should not be used, as their action may change in future arm implementations. instruction set s3c 2500b 3- 2 3.1.2 instruction summary table 3-1. the arm instruction set mnemonic instruction action adc add with carry rd: = rn + op2 + carry add add rd: = rn + op2 and and rd: = rn and op2 b branch r15: = address bic bit clear rd: = rn and not op2 bl branch with link r14: = r15, r15: = address bx branch and exchange r15: = rn, t bit: = rn[0] cdp coprocessor data processing (coprocessor-specific) cmn compare negative cpsr flags: = rn + op2 cmp compare cpsr flags: = rn - op2 eor exclusive or rd: = (rn and not op2) or (op2 and not rn) ldc load coprocessor from memory coprocessor load ldm load multiple registers stack manipulation (pop) ldr load register from memory rd: = (address) mcr move cpu register to coprocessor register crn: = rrn { S3C2500B instruction set 3- 3 table 3-1. the arm instruction set (continued) mnemonic instruction action orr or rd: = rn or op2 rsb reverse subtract rd: = op2 - rn rsc reverse subtract with carry rd: = op2 - rn-1 + carry sbc subtract with carry rd: = rn - op2-1 + carry stc store coprocessor register to memory address: = crn stm store multiple stack manipulation (push) str store register to memory : = rd sub subtract rd: = rn - op2 swi software interrupt os call swp swap register with memory rd: = [rn], [rn] := rm teq test bit-wise equality cpsr flags: = rn eor op2 tst test bits cpsr flags: = rn and op2 instruction set s3c 2500b 3- 4 3.2 the condition field in arm state, all instructions are conditionally executed according to the state of the cpsr condition codes and the instruction s condition field. this field (bits 31:28) determines the circumstances under which an instruction is to be executed. if the state of the c, n, z and v flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. there are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction s mnemonic. for example, a branch (b in assembly language) becomes beq for "branch if "equal", which means the branch will only be taken if the z flag is set. in practice, fifteen different conditions may be used: these are listed in table 3-2. the sixteenth (1111) is reserved, and must not be used. in the absence of a suffix, the condition field of most instructions is set to ?always" (suffix al). this means the instruction will always be executed regardless of the cpsr condition codes. table 3-2. condition code summary code suffix flags meaning 0000 eq z set equal 0001 ne z clear not equal 0010 cs c set unsigned higher or same 0011 cc c clear unsigned lower 0100 mi n set negative 0101 pl n clear positive or zero 0110 vs v set overflow 0111 vc v clear no overflow 1000 hi c set and z clear unsigned higher 1001 ls c clear or z set unsigned lower or same 1010 ge n equals v greater or equal 1011 lt n not equal to v less than 1100 gt z clear and (n equals v) greater than 1101 le z set or (n not equal to v) less than or equal 1110 al (ignored) always S3C2500B instruction set 3- 5 3.3 branch and exchange (bx) this instruction is only executed if the condition is true. the various conditions are defined in table 3-2. this instruction performs a branch by copying the contents of a general register, rn, into the program counter, pc. the branch causes a pipeline flush and refill from the address specified by rn. this instruction also permits the instruction set to be exchanged. when the instruction is executed, the value of rn[0] determines whether the instruction stream will be decoded as arm or thumb instructions. 31 24 27 19 15 8 7 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 cond rn 28 16 11 12 23 20 4 3 [3:0] operand register if bit0 of rn = 1, subsequent instructions decoded as thumb instructions if bit0 of rn =0, subsequent instructions decoded as arm instructions [31:28] condition field figure 3-2. branch and exchange instructions 3.3.1 instruction cycle times the bx instruction takes 2s + 1n cycles to execute, where s and n are defined as sequential (s-cycle) and non- sequential (n-cycle), respectively. 3.3.2 assembler syntax bx - branch and exchange. bx {cond} rn {cond} two character condition mnemonic. see table 3-2. rn is an expression evaluating to a valid register number. 3.3.3 using r15 as an operand if r15 is used as an operand, the behaviour is undefined. instruction set s3c 2500b 3- 6 examples adr r0, into_thumb + 1 ; generate branch target address ; and set bit 0 high - hence ; arrive in thumb state. bx r0 ; branch and change to thumb ; state. code16 ; assemble subsequent code as into_thumb ; thumb instructions adr r5, back_to_arm ; generate branch target to word aligned address ; - hence bit 0 is low and so change back to arm state. bx r5 ; branch and change back to arm state. align ; word align code32 ; assemble subsequent code as arm instructions back_to_arm S3C2500B instruction set 3- 7 3.4 branch and branch with link (b, bl) the instruction is only executed if the condition is true. the various conditions are defined table 3-2. the instruction encoding is shown in figure 3-3, below. 31 24 27 cond offset 28 23 [24] link bit 0 = branch 1 = branch with link [31:28] condition field 25 101 l 0 figure 3-3. branch instructions branch instructions contain a signed 2?s complement 24 bit offset. this is shifted left two bits, sign extended to 32 bits, and added to the pc. the instruction can therefore specify a branch of +/- 32mbytes. the branch offset must take account of the pre-fetch operation, which causes the pc to be 2 words (8 bytes) ahead of the current instruction. 3.4.1 the link bit branch with link (bl) writes the old pc into the link register (r14) of the current bank. the pc value written into r14 is adjusted to allow for the pre-fetch, and contains the address of the instruction following the branch and link instruction. note that the cpsr is not saved with the pc and r14[1:0] are always cleared. to return from a routine called by branch with link use mov pc,r14 if the link register is still valid or ldm rn!,{..pc} if the link register has been saved onto a stack pointed to by rn. 3.4.2 instruction cycle times branch and branch with link instructions take 2s + 1n incremental cycles, where s and n are defined as sequential (s-cycle) and internal (i-cycle). instruction set s3c 2500b 3- 8 3.4.3 assembler syntax items in {} are optional. items in < > must be present. b{l}{cond} S3C2500B instruction set 3- 9 3.5 data processing the data processing instruction is only executed if the condition is true. the conditions are defined in table 3-2. the instruction encoding is shown in figure 3-4. 31 24 27 19 15 cond operand2 28 16 11 12 21 [15:12] destination register 0 = branch 1 = branch with link [19:16] 1st operand register 0 = branch 1 = branch with link [20] set condition codes 0 = do not after condition codes 1 = set condition codes [24:21] operation code 0000 = and-rd: = op1 and op2 0001 = eor-rd: = op1 eor op2 0010 = sub-rd: = op1-op2 0011 = rsb-rd: = op2-op1 0100 = add-rd: = op1+op2 0101 = adc-rd: = op1+op2+c 0110 = sbc-rd: = op1-op2+c-1 0111 = rsc-rd: = op2-op1+c-1 1000 = tst-set condition codes on op1 and op2 1001 = teo-set condition codes on op1 eor op2 1010 = cmp-set condition codes on op1-op2 1011 = smn-set condition codes on op1+op2 1100 = orr-rd: = op1 or op2 1101 = mov-rd: =op2 1110 = bic-rd: = op1 and not op2 1111 = mvn-rd: = not op2 [25] immediate operand 0 = operand 2 is a register 1 = operand 2 is an immediate value [11:0] operand 2 type selection [31:28] condition field 26 25 00 l 20 opcode s rn rd 0 rotate shift rm [3:0] 2nd operand register [11:4] shift applied to rm 3 11 0 4 8 11 0 7 imm [7:0] unsigned 8 bit immediate value [11:8] shift applied to imm figure 3-4. data processing instructions instruction set s3c 2500b 3- 10 the instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. the first operand is always a register (rn). the second operand may be a shifted register (rm) or a rotated 8 bit immediate value (imm) according to the value of the i bit in the instruction. the condition codes in the cpsr may be preserved or updated as a result of this instruction, according to the value of the s bit in the instruction. certain operations (tst, teq, cmp, cmn) do not write the result to rd. they are used only to perform tests and to set the condition codes on the result and always have the s bit set. the instructions and their effects are listed in table 3-3. S3C2500B instruction set 3- 11 3.5.1 cpsr flags the data processing operations may be classified as logical or arithmetic. the logical operations (and, eor, tst, teq, orr, mov, bic, mvn) perform the logical action on all corresponding bits of the operand or operands to produce the result. if the s bit is set (and rd is not r15, see below) the v flag in the cpsr will be unaffected, the c flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is lsl #0), the z flag will be set if and only if the result is all zeros, and the n flag will be set to the logical value of bit 31 of the result. table 3-3. arm data processing instructions assembler mnemonic opcode action and 0000 operand1 and operand2 eor 0001 operand1 eor operand2 sub 0010 operand1 - operand2 rsb 0011 operand2 - operand1 add 0100 operand1 + operand2 adc 0101 operand1 + operand2 + carry sbc 0110 operand1 - operand2 + carry - 1 rsc 0111 operand2 - operand1 + carry - 1 tst 1000 as and, but result is not written teq 1001 as eor, but result is not written cmp 1010 as sub, but result is not written cmn 1011 as add, but result is not written orr 1100 operand1 or operand2 mov 1101 operand2 (operand1 is ignored) bic 1110 operand1 and not operand2 (bit clear) mvn 1111 not operand2 (operand1 is ignored) the arithmetic operations (sub, rsb, add, adc, sbc, rsc, cmp, cmn) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). if the s bit is set (and rd is not r15) the v flag in the cpsr will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. the c flag will be set to the carry out of bit 31 of the alu, the z flag will be set if and only if the result was zero, and the n flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed). instruction set s3c 2500b 3- 12 3.5.2 shifts when the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the shift field in the instruction. this field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). the amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than r15). the encoding for the different shift types is shown in figure 3-5. 0 [6:5] shift type 00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right [11:7] shift amount 5 bit unsigned integer [6:5] shift typ e 00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right [11:8] shift register shift amount specified in bottom-byte of rs 4 5 6 7 11 1 4 5 6 7 11 8 0 rs figure 3-5. arm shift operations 3.5.2.1 instruction specified shift amount when the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. a logical shift left (lsl) takes the contents of rm and moves each bit by the specified amount to a more significant position. the least significant bits of the result are filled with zeros, and the high bits of rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the c bit of the cpsr when the alu operation is in the logical class (see above). for example, the effect of lsl #5 is shown in figure 3-6. 31 27 26 contents of rm value of operand 2 carry out 0 0 0 0 0 0 figure 3-6. logical shift left note lsl #0 is a special case, where the shifter carry out is the old value of the cpsr c flag. the contents of rm are used directly as the second operand. a logical shift right (lsr) is similar, but the contents of rm are moved to less significant positions in the result. lsr #5 has the effect shown in figure 3-7 . S3C2500B instruction set 3- 13 31 contents of rm value of operand 2 0 carry out 4 5 0 0 0 0 0 figure 3-7. logical shift right the form of the shift field which might be expected to correspond to lsr #0 is used to encode lsr #32, which has a zero result with bit 31 of rm as the carry output. logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert lsr #0 (and asr #0 and ror #0) into lsl #0, and allow lsr #32 to be specified. an arithmetic shift right (asr) is similar to logical shift right, except that the high bits are filled with bit 31 of rm instead of zeros. this preserves the sign in 2's complement notation. for example, asr #5 is shown in figure 3- 8. 31 contents of rm value of operand 2 0 carry out 4 5 30 figure 3-8. arithmetic shift right the form of the shift field which might be expected to give asr #0 is used to encode asr #32. bit 31 of rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of rm. the result is therefore all ones or all zeros, according to the value of bit 31 of rm. instruction set s3c 2500b 3- 14 rotate right (ror) operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. for example, ror #5 is shown in figure 3-9. the form of the shift field which might be expected to give ror #0 is 31 contents of rm value of operand 2 0 carry out 4 5 figure 3-9. rotate right used to encode a special function of the barrel shifter, rotate right extended ( rrx). this is a rotate right by one bit position of the 33 bit quantity formed by appending the cpsr c flag to the most significant end of the contents of rm as shown in figure 3-10. 31 contents of rm value of operand 2 0 1 carry out c in figure 3-10. rotate right extended S3C2500B instruction set 3- 15 3.5.2.2 register specified shift amount only the least significant byte of the contents of rs is used to determine the shift amount. rs can be any general register other than r15. if this byte is zero, the unchanged contents of rm will be used as the second operand, and the old value of the cpsr c flag will be passed on as the shifter carry output. if the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. if the value in the byte is 32 or more, the result will be a logical extension of the shift described above: 1. lsl by 32 has result zero, carry out equal to bit 0 of rm. 2. lsl by more than 32 has result zero, carry out zero. 3. lsr by 32 has result zero, carry out equal to bit 31 of rm. 4. lsr by more than 32 has result zero, carry out zero. 5. asr by 32 or more has result fi lled with and carry out equal to bit 31 of rm. 6. ror by 32 has result equal to rm, carry out equal to bit 31 of rm. 7. ror by n where n is greater than 32 will give the same result and carry out as ror by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above. note the zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction. instruction set s3c 2500b 3- 16 3.5.3 immediate operand rotates the immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. this value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. this enables many common constants to be generated, for example all powers of 2. 3.5.4 writing to r15 when rd is a register other than r15, the condition code flags in the cpsr may be updated from the alu flags as described above. when rd is r15 and the s flag in the instruction is not set the result of the operation is placed in r15 and the cpsr is unaffected. when rd is r15 and the s flag is set the result of the operation is placed in r15 and the spsr corresponding to the current mode is moved to the cpsr. this allows state changes which atomically restore both pc and cpsr. this form of instruction should not be used in user mode. 3.5.5 using r15 as an operand if r15 (the pc) is used as an operand in a data processing instruction the register is used directly. the pc value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. if the shift amount is specified in the instruction, the pc will be 8 bytes ahead. if a register is used to specify the shift amount the pc will be 12 bytes ahead. 3.5.6 teq, tst, cmp and cmn opcodes note teq, tst, cmp and cmn do not write the result of their operation but do set flags in the cpsr. an assembler should always set the s flag for these instructions even if this is not specified in the mnemonic. the teqp form of the teq instruction used in earlier arm processors must not be used: the psr transfer operations should be used instead. the action of teqp in the arm9tdmi is to move spsr_ S3C2500B instruction set 3- 17 3.5.7 instruction cycle times data processing instructions vary in the number of incremental cycles taken as follows: table 3-4. incremental cycle times processing type cycles normal data processing 1s data processing with register specified shift 1s + 1i data processing with pc written 2s + 1n data processing with register specified shift and pc written 2s + 1n + 1i note: s, n and i are as defined sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle) respectively. 3.6.8 assembler syntax ? mov,mvn (single operand instructions). instruction set s3c 2500b 3- 18 examples addeq r2,r4,r5 ; if the z flag is set make r2: = r4 + r5 teqs r4,#3 ; test r4 for equality with 3. ; (the s is in fact redundant as the ; assembler inserts it automatically.) sub r4,r5,r7,lsr r2 ; logical right shift r7 by the num ber in ; the bottom byte of r2, subtract result ; from r5, and put the answer into r4. mov pc,r14 ; return from subroutine. movs pc,r14 ; return from exception and restore cpsr ; from spsr_mode. S3C2500B instruction set 3- 19 3.6 psr transfer (mrs, msr) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the mrs and msr instructions are formed from a subset of the data processing operations and are implemented using the teq, tst, cmn and cmp instructions without the s flag set. the encoding is shown in figure 3-11. these instructions allow access to the cpsr and spsr registers. the mrs instruction allows the contents of the cpsr or spsr_ instruction set s3c 2500b 3- 20 mrs (transfer register contents or immediate value to psr flag bits only) cond source operand pd 101001111 31 22 27 28 11 12 21 23 i 10 00 26 25 24 0 cond 00000000 00010 pd 101001111 31 22 27 28 11 12 21 23 rm mrs (transfer register contents to psr) 4 3 0 cond 000000000000 00010 rd ps 001111 31 22 27 15 28 16 11 12 21 23 mrs (transfer psr contents to a register) 0 [3:0] source register [22] destination psr 0 = cpsr 1 = spsr_ S3C2500B instruction set 3- 21 3.6.2 reserved bits only twelve bits of the psr are defined in arm9tdmi (n, z, c, v, i, f, t & m[4:0]); the remaining bits are reserved for use in future versions of the processor. refer to figure 2-6 for a full description of the psr bits. to ensure the maximum compatibility between arm9tdmi programs and future processors, the following rules should be observed: ? the reserved bit s should be preserved when changing the value in a psr. ? programs should not rely on specific values from the reserved bits when checking the psr status, since they may read as one or zero in future processors. a read-modify-write strategy should therefore be used when altering the control bits of any psr register; this involves transferring the appropriate psr register to a general register using the mrs instruction, changing only the relevant bits and then transferring the modified value back to the psr register using the msr instruction. examples the following sequence performs a mode change: mrs r0,cpsr ; take a copy of the cpsr. bic r0,r0,#0x1f ; clear the mode bits. orr r0,r0,#new_mode ; select new mode msr cpsr,r0 ; write back the modified cpsr. when the aim is simply to change the condition code flags in a psr, a value can be written directly to the flag bits without disturbing the control bits. the following instruction sets the n, z, c and v flags: msr cpsr_flg,#0xf0000000 ; set all the fl ags regardless of their previous state ; (does not affect any control bits). no attempt should be made to write an 8 bit immediate value into the whole psr since such an operation cannot preserve the reserved bits. 3.6.3 instruction cycle times psr transfers take 1s incremental cycles, where s is defined as sequential (s-cycle). instruction set s3c 2500b 3- 22 3.6.4 assembler syntax ? mrs - transfer psr contents to a register mrs{cond} rd, S3C2500B instruction set 3- 23 3.7 multiply and multiply-accumulate (mul, mla) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-12. the multiply and multiply-accumulate instructions use an 8 bit booth's algorithm to perform integer multiplication. 31 27 19 15 cond 28 16 11 12 21 20 s rd rn [15:12][11:8][3:0] operand registers [19:16] destination register [20] set condition code 0 = do not alter condition codes 1 = set condition codes [21] accumulate 0 = multiply only 1 = multiply and accumulate [31:28] condition field 22 1 0 0 1 rs rm a 0 0 0 0 0 0 8 7 4 3 0 figure 3-12. multiply instructions the multiply form of the instruction gives rd: = rm * rs. rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. the multiply-accumulate form gives rd: = rm * rs + rn, which can save an explicit add instruction in some circumstances. both forms of the instruction work on operands which may be considered as signed (2? complement) or unsigned integers. the results of a signed multiply nd of an unsigned multiply of 32 bit operands differ only in the upper 32 bits-the low 32 bits of the signed and unsigned results are identical. as these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies. for example consider the multiplication of the operands: operand a operand b result 0xfffffff6 0x0000001 0xffffff38 if the operands are interpreted as signed operand a has the value -10, operand b has the value 20, and the result is -200 which is correctly represented as 0xffffff38. if the operands are interpreted as unsigned operand a has the value 4294967286, operand b has the value 20 and the result is 85899345720, which is represented as 0x13ffffff38, so the least significant 32 bits are 0xffffff38. operand restrictions the destination register rd must not be the same as the operand register rm. r15 must not be used as an operand or as the destination register. all other register combinations will give correct results, and rd, rn and rs may use the same register when required. instruction set s3c 2500b 3- 24 3.7.1 cpsr flags setting the cpsr flags is optional, and is controlled by the s bit in the instruction. the n (negative) and z (zero) flags are set correctly on the result (n is made equal to bit 31 of the result, and z is set if and only if the result is zero). the c (carry) flag is set to a meaningless value and the v (overflow) flag is unaffected. 3.7.2 instruction cycle times mul takes 1s + mi and mla 1s + (m+1)i cycles to execute, where s and i are defined as sequential (s-cycle) and internal (i-cycle), respectively. m the number of 8 bit multiplier array cycles is required to complete the multiply, which is controlled by the value of the multiplier operand specified by rs. its possible values are as follows 1 if bits [32:8] of the multiplier operand are all zero or all one. 2 if bits [32:16] of the multiplier operand are all zero or all one. 3 if bits [32:24] of the multiplier operand are all zero or all one. 4 in all other cases. 3.7.3 assembler syntax mul{cond}{s} rd,rm,rs mla{cond}{s} rd,rm,rs,rn { cond} two-character condition mnemonic. see table 3-2. { s} set condition codes if s present rd, rm, rs and rn expressions evaluating to a register number other than r15. examples mul r1,r2,r3 ; r1: = r2 * r3 mlaeqs r1,r2,r3,r4 ; conditionally r1: = r2 * r3 + r4, setting condition codes. S3C2500B instruction set 3- 25 3.8 multiply long and multiply-accumulate long (mull,mlal) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-13. the multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. signed and unsigned multiplication each with optional accumulate give rise to four variations. 31 27 19 15 cond 28 16 11 12 21 23 u 20 s rdhi rdlo [11:8][3:0] operand registers [19:16][15:12] source destination registers [20] set condition code 0 = do not alter condition codes 1 = set condition codes [21] accumulate 0 = multiply only 1 = multiply and accumulate [22] unsigned 0 = unsigned 1 = signed [31:28] condition field 22 0 0 0 0 1 1 0 0 1 rs rm a 8 7 4 3 0 figure 3-13. multiply long instructions the multiply forms (umull and smull) take two 32 bit numbers and multiply them to produce a 64 bit result of the form rdhi, rdlo: = rm * rs. the lower 32 bits of the 64 bit result are written to rdlo, the upper 32 bits of the result are written to rdhi. the multiply-accumulate forms (umlal and smlal) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form rdhi, rdlo: = rm * rs + rdhi, rdlo. the lower 32 bits of the 64 bit number to add is read from rdlo. the upper 32 bits of the 64 bit number to add is read from rdhi. the lower 32 bits of the 64 bit result are written to rdlo. the upper 32 bits of the 64 bit result are written to rdhi. the umull and umlal instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. the smull and smlal instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result. 3.8.1 operand restrictions ? r15 must not be used as an operand or as a destination register. ? rdhi, rdlo, and rm must all specify different registers. instruction set s3c 2500b 3- 26 3.8.2 cpsr flags setting the cpsr flags is optional, and is controlled by the s bit in the instruction. the n and z flags are set correctly on the result (n is equal to bit 63 of the result, z is set if and only if all 64 bits of the result are zero). both the c and v flags are set to meaningless values. 3.8.3 instruction cycle times mull takes 1s + (m+1)i and mlal 1s + (m+2)i cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by rs. its possible values are as follows: for signed instructions smull, smlal: ? if bits [31:8] of the multiplier operand are all zero or all one. ? if bits [31:16] of the multiplier operand are all zero or all one. ? if bits [31:24] of the multiplier operand are all zero or all one. ? in all other cases. for unsigned instructions umull, umlal: ? if bits [31:8] of the multiplier operand are all zero. ? if bits [31:16] of the multiplier operand are all zero. ? if bits [31:24] of the multiplier operand are all zero. ? in all other cases. s and i are defined as sequential (s-cycle) and internal (i-cycle), respectively. S3C2500B instruction set 3- 27 3.8.4 assembler syntax table 3-5. assembler syntax descriptions mnemonic description purpose umull{cond}{s} rdlo, rdhi, rm, rs unsigned multiply long 32 x 32 = 64 umlal{cond}{s} rdlo, rdhi, rm, rs unsigned multiply & accumulate long 32 x 32 + 64 = 64 smull{cond}{s} rdlo, rdhi, rm, rs signed multiply long 32 x 32 = 64 smlal{cond}{s} rdlo, rdhi, rm, rs signed multiply & accumulate long 32 x 32 + 64 = 64 where: { cond} two-character condition mnemonic. see table 3-2. { s} set condition codes if s present rdlo, rdhi, rm, rs expressions evaluating to a register number other than r15. examples umull r1, r4, r2, r3 ; r4, r1: = r2 * r3 umlals r1, r5, r2, r3 ; r5, r1: = r2 * r3 + r5, r1 also setting condition codes instruction set s3c 2500b 3- 28 3.9 single data transfer (ldr, str) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-14. the single data transfer instructions are used to load or store single bytes or words of data. the memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. the result of this calculation may be written back into the base register if auto-indexing is required. 31 27 19 15 0 cond 28 16 11 12 21 23 b 20 l rn rd 22 01 i p u offset w 26 24 25 [15:12] source/destination registers [19:16] base register [20] load/store bit 0 = store to memory 1 = load from memory [21] write-back bit 0 = no write-back 1 = write address into base [22] byte/word bit 0 = transfer word quantity 1 = transfer byte quantity [23] up/down bit 0 = down: subtract offset from base 1 = up: add offset to base [24] pre/post indexing bit 0 = post: add offset after transfer 1 = pre: add offset bofore transfer [25] immediate offset 0 = offset is an immediate value [11:0] offset shift immediate [11:0] unsigned 12-bit immediate offset 11 11 rm [3:0] offset register [11:4] shift applied to rm [31:28] condition field 0 4 3 0 figure 3-14. single data transfer instructions S3C2500B instruction set 3- 29 3.9.1 offsets and auto-indexing the offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). the offset may be added to (u = 1) or subtracted from (u = 0) the base register rn. the offset modification may be performed either before (pre-indexed, p = 1) or after (post-indexed, p = 0) the base is used as the transfer address. the w bit gives optional auto increment and decrement addressing modes. the modified base value may be written back into the base (w = 1), or the old base value may be kept (w = 0). in the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. therefore post-indexed data transfers always write back the modified base. the only use of the w bit in a post-indexed data transfer is in privileged mode code, where setting the w bit forces non- privileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware. 3.9.2 shifted register offset the 8 shift control bits are described in the data processing instructions section. however, the register specified shift amounts are not available in this instruction class. see figure 3-5. 3.9.3 bytes and words this instruction class may be used to transfer a byte (b = 1) or a word (b = 0) between an arm9tdmi register and memory. the action of ldr(b) and str(b) instructions is influenced by the bigend control signal of arm9tdmi core. the two possible configurations are described below. 3.9.3.1 little-endian configuration a byte load (ldrb) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. the selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. please see figure 2-2. a byte store (strb) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. the external memory system should activate the appropriate byte subsystem to store the data. a word load (ldr) will normally use a word aligned address. however, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. this means that half-words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. two shift operations are then required to clear or to sign extend the upper 16 bits. a word store (str) should generate a word aligned address. the word presented to the data bus is not affected if the address is not word aligned. that is, bit 31 of the register being stored always appears on data bus output 31. instruction set s3c 2500b 3- 30 ldr from word aligned address a+3 a a+2 a+1 memory 24 16 8 0 a b c d register 24 16 8 0 a b c d ldr from address offset by 2 a+3 a a+2 a+1 memory 24 16 8 0 a b c d register 24 16 8 0 a b c d figure 3-15. little-endian offset addressing 3.9.3.2 big-endian configuration a byte load (ldrb) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. the selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. please see figure 2-1. a byte store (strb) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. the external memory system should activate the appropriate byte subsystem to store the data. a word load (ldr) should generate a word aligned address. an address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. this means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. a shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. an address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8. a word store (str) should generate a word aligned address. the word presented to the data bus is not affected if the address is not word aligned. that is, bit 31 of the register being stored always appears on data bus output 31. S3C2500B instruction set 3- 31 3.9.4 use of r15 write-back must not be specified if r15 is specified as the base register (rn). when using r15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. r15 must not be specified as the register offset (rm). when r15 is the source register (rd) of a register store (str) instruction, the stored value will be address of the instruction plus 12. 3.9.5 restriction on the use of base register when configured for late aborts, the following example code is difficult to unwind as the base register, rn, gets updated before the abort handler starts. sometimes it may be impossible to calculate the initial value. after an abort, the following example code is difficult to unwind as the base register, rn, gets updated before the abort handler starts. sometimes it may be impossible to calculate the initial value. example: ldr r0,[r1],r1 therefore a post-indexed ldr or str where rm is the same register as rn should not be used. 3.9.6 data aborts a transfer to or from a legal address may cause problems for a memory management system. for instance, in a system which uses virtual memory the required data may be absent from main memory. the memory manager can signal a problem by taking the processor abort input high whereupon the data abort trap will be taken. it is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. 3.9.7 instruction cycle times normal ldr instructions take 1s + 1n + 1i and ldr pc take 2s + 2n +1i incremental cycles, where s,n and i are defined as sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle), respectively. str instructions take 2n incremental cycles to execute. instruction set s3c 2500b 3- 32 3.9.8 assembler syntax S3C2500B instruction set 3- 33 examples str r1,[r2,r4]! ; store r1 at r2 + r4 (both of which are registers) ; and write back address to r2. str r1,[r2],r4 ; store r1 at r2 and write back r2 + r4 to r2. ldr r1,[r2,#16] ; load r1 from contents of r2 + 16, but don't write back. ldr r1,[r2,r3,lsl#2] ; load r1 from contents of r2 + r3 * 4. ldreqb r1,[r6,#5] ; conditionally load byte at r6 + 5 into ; r1 bits 0 to 7, filling bits 8 to 31 with zeros. str r1,place ; generate pc relative offset to address place. place instruction set s3c 2500b 3- 34 3.10 halfwo rd and signed data transfer (ldrh/strh/ldrsb/ldrsh) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-16. these instructions are used to load or store half-words of data and also load sign -extended bytes or half-words of data. the memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. the result of this calculation may be written back into the base register if auto-indexing is required. 31 27 19 15 cond 28 16 11 12 21 23 0 20 l rn rd [3:0] offset register [6][5] s h 0 0 = swp instruction 0 1 = unsigned halfwords 1 1 = signed byte 1 1 = signed half words [15:12] source/destination register [19:16] base register [20] load/store 0 = store to memory 1 = load from memory [21] write-back 0 = no write-back 1 = write address into base [23] up/down 0 = down: subtract offset from base 1 = up: add offset to base [24] pre/post indexing 0 = post: add/subtract offset after transfer 1 = pre: add/subtract offset bofore transfer [31:28] condition field 22 000 p u 0000 w 24 25 1 rm s h 1 8 7 6 5 4 3 0 figure 3-16. half-word and signed data transfer with register offset S3C2500B instruction set 3- 35 31 27 19 15 cond 28 16 11 12 21 23 1 20 l rn rd [3:0] immediate offset (low nibble) [6][5] s h 0 0 = swp instruction 0 1 = unsigned halfwords 1 1 = signed byte 1 1 = signed half words [11:8] immediate offset (high nibble) [15:12] source/destination register [19:16] base register [20] load/store 0 = store to memory 1 = load from memory [21] write-back 0 = no write-back 1 = write address into base [23] up/down 0 = down: subtract offset from base 1 = up: add offset to base [24] pre/post indexing 0 = post: add/subtract offset after transfer 1 = pre: add/subtract offset bofore transfer [31:28] condition field 22 000 p u offset w 24 25 1 offset s h 1 8 7 6 5 4 3 0 figure 3-17. half-word and signed data transfer with immediate offset and auto-indexing 3.10.1 offsets and auto-indexing the offset from the base may be either a 8 -bit unsigned binary immediate value in the instruction, or a second register. the 8-bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word, such that bit 11 becomes the msb and bit 0 becomes the lsb. the offset may be added to (u = 1) or subtracted from (u = 0) the base register rn. the offset modification may be performed either before (pre-indexed, p = 1) or after (post-indexed, p = 0) the base register is used as the transfer address. the w bit gives optional auto-increment and decrement addressing modes. the modified base value may be written back into the base (w = 1), or the old base may be kept (w = 0). in the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained if necessary by setting the offset to zero. therefore post-indexed data transfers always write back the modified base. the write-back bit should not be set high (w = 1) when post-indexed addressing is selected. instruction set s3c 2500b 3- 36 3.10.2 half-word load and stores setting s = 0 and h = 1 may be used to transfer unsigned half-words between an arm9tdmi register and memory. the action of ldrh and strh instructions is influenced by the bigend control signal. the two possible configurations are described in the section below. 3.10.3 signed byte and half-word loads the s bit controls the loading of sign-extended data. when s = 1 the h bit selects between bytes (h = 0) and half-words (h = 1). the l bit should not be set low (store) when signed (s = 1) operations have been selected. the ldrsb instruction loads the selected byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7, the sign bit. the ldrsh instruction loads the selected half-word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15, the sign bit. the action of the ldrsb and ldrsh instructions is influenced by the bigend control signal. the two possible configurations are described in the following section. 3.10.4 endianness and byte/half-word selection 3.10.4.1 little-endian configuration a signed byte load (ldrsb) expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary, on data bus inputs 15 through to 8 if it is a word address plus one byte, and so on. the selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. please see figure 2-2. a half-word load (ldrsh or ldrh) expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a half-word boundary, (a[1]=1).the supplied address should always be on a half-word boundary. if bit 0 of the supplied address is high then the arm9tdmi will load an unpredictable value. the selected half-word is placed in the bottom 16 bits of the destination register. for unsigned half-words (ldrh), the top 16 bits of the register are filled with zeros and for signed half-words (ldrsh) the top 16 bits are filled with the sign bit, bit 15 of the half-word. a half-word store (strh) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. the external memory system should activate the appropriate half-word subsystem to store the data. note that the address must be half-word aligned, if bit 0 of the address is high this will cause unpredictable behaviour. S3C2500B instruction set 3- 37 3.10.4.2 big-endian configuration a signed byte load (ldrsb) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. the selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. please see figure 2-1. a half-word load (ldrsh or ldrh) expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a half-word boundary, (a[1] =1). the supplied address should always be on a half-word boundary. if bit 0 of the supplied address is high then the arm9tdmi will load an unpredictable value. the selected half-word is placed in the bottom 16 bits of the destination register. for unsigned half-words (ldrh), the top 16 bits of the register are filled with zeros and for signed half-words (ldrsh) the top 16 bits are filled with the sign bit, bit 15 of the half-word. a half-word store (strh) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. the external memory system should activate the appropriate half-word subsystem to store the data. note that the address must be half-word aligned, if bit 0 of the address is high this will cause unpredictable behaviour. 3.10.5 use of r15 write-back should not be specified if r15 is specified as the base register (rn). when using r15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. r15 should not be specified as the register offset (rm). when r15 is the source register (rd) of a half-word store (strh) instruction, the stored address will be address of the instruction plus 12. 3.10.6 data aborts a transfer to or from a legal address may cause problems for a memory management system. for instance, in a system which uses virtual memory the required data may be absent from the main memory. the memory manager can signal a problem by taking the processor abort input high whereupon the data abort trap will be taken. it is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. 3.10.7 instruction cycle times normal ldr(h, sh, sb) instructions take 1s + 1n + 1i. ldr(h, sh, sb) pc take 2s + 2n + 1i incremental cycles. s,n and i are defined as sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle), respectively. strh instructions take 2n incremental cycles to execute. instruction set s3c 2500b 3- 38 3.10.8 assembler syntax S3C2500B instruction set 3- 39 examples ldrh r1,[r2,-r3]! ; load r1 from the contents of the half-word address ; contained in r2-r3 (both of which are registers) ; and write back address to r2 strh r3,[r4,#14] ; store the half-word in r3 at r14+14 but don't write back. ldrsb r8,[r2],#-223 ; load r8 with the sign extended contents of the byte ; address contained in r2 and write back r2-223 to r2. ldrnesh r11,[r0] ; conditionally load r11 with the sign extended contents ; of the half-word address contained in r0. here ; generate pc relative offset to address fred. strh r5, [pc,#(fred-here-8)]; store the half-word in r5 at address fred fred instruction set s3c 2500b 3- 40 3.11 block data transfer (ldm, stm) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-18. block data transfer instructions are used to load (ldm) or store (stm) any subset of the currently visible registers. they support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory. 3.11.1 the register list the instruction can cause the transfer of any registers in the current bank (and non -user mode pro grams can also transfer to and from the user bank, see below). the register list is a 16 bit field in the instruction, with each bit corresponding to a register. a 1 in bit 0 of the register field will cause r0 to be transferred, a 0 will cause it not to be transferred; similarly bit 1 controls the transfer of r1, and so on. any subset of the registers, or all the registers, may be specified. the only restriction is that the register list should not be empty. whenever r15 is stored to memory the stored value is the address of the stm instruction plus 12. 31 27 19 15 cond 28 16 21 23 s 20 l rn [19:16] base register [20] load/store bit 0 = store to memory 1 = load from memory [21] write-back bit 0 = no write-back 1 = write address into base [22] psr & force user bit 0 = do not load psr or user mode 1 = load psr or force user mode [23] up/down bit 0 = down: subtract offset from base 1 = up: add offset to base [24] pre/post indexing bit 0 = post: add offset after transfer 1 = pre: add offset bofore transfer [31:28] condition field 22 100 p u w 24 25 register list 24 0 figure 3-18. block data transfer instructions S3C2500B instruction set 3- 41 3.11.2 addressing modes the transfer addresses are determined by the contents of the base register (rn), the pre/post bit (p) and the up/ down bit (u). the registers are transferred in the order lowest to highest, so r15 (if in the list) will always be transferred last. the lowest register also gets transferred to/from the lowest memory address. by way of illustration, consider the transfer of r1, r5 and r7 in the case where rn = 0x1000 and write back of the modified base is required (w = 1). figure 3.19-22 show the sequence of register transfers, the addresses used, and the value of rn after the instruction has completed. in all cases, had write back of the modified base not been required (w = 0), rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value. 3.11.3 address alignment the address should normally be a word aligned quantity and non-word aligned addresses do not affect the instruction. however, the bottom 2 bits of the address will appear on a[1:0] and might be interpreted by the memory system. 1 2 3 4 rn r1 r1 r5 r1 r5 r7 rn 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 figure 3-19. post-increment addressing instruction set s3c 2500b 3- 42 rn 1 r1 r1 2 r5 3 r1 r5 4 r7 rn 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 figure 3-20. pre-increment addressing rn 1 r1 r1 2 r5 3 r1 r5 4 r7 rn 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 figure 3-21. post-decrement addressing S3C2500B instruction set 3- 43 rn 1 r1 r1 2 r5 3 r1 r5 4 r7 rn 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 0x100c 0x1000 0x0ff4 figure 3-22. pre-decrement addressing 3.11.4 use of the s bit when the s bit is set in a ldm/stm instruction its meaning depends on whether or not r15 is in the transfer list and on the type of instruction. the s bit should only be set if the instruction is to execute in a privileged mode. 3.11.4.1 ldm with r15 in transfer list and s bit set (mode changes) if the instruction is a ldm then spsr_ instruction set s3c 2500b 3- 44 3.11.6 inclusion of the base in the register list when write-back is specified, the base is written back at the end of the second cycle of the instruction. during a stm, the first register is written out at the start of the second cycle. a stm which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value. a ldm will always overwrite the updated base if the base is in the list. 3.11.7 data aborts some legal addresses may be unacceptable to a memory management system, and the memory manager can indicate a problem with an address by taking the abort signal high. this can happen on any transfer during a multiple register load or store, and must be recoverable if arm9tdmi is to be used in a virtual memory system. 3.11.7.1 aborts during stm instructions if the abort occurs during a store multiple instruction, arm9tdmi takes little action until the instruction completes, whereupon it enters the data abort trap. the memory manager is responsible for preventing erroneous writes to the memory. the only change to the internal state of the processor will be the modification of the base register if write-back was specified, and this must be reversed by software (and the cause of the abort resolved) before the instruction may be retried. 3.11.7.2 aborts during ldm instructions when arm9tdmi detects a data abort during a load multiple instruction, it modifies the operation of the instruction to ensure that recovery is possible. ? overwriting of registers stops when the abort happens. the aborting load will not take place but earlier ones may have overwritten registers. the pc is always the last register to be written and so will always be preserved. ? the base register is restored, to its modified value if write-back was requested. this ensures recoverability in the case where the base register is also in the transfer list, and may have been overwritten before the abort occurred. the data abort trap is taken when the load multiple has completed, and the system software must undo any base modification (and resolve the cause of the abort) before restarting the instruction. 3.11.8 instruction cycle times normal ldm instructions take ns + 1n + 1i and ldm pc takes (n+1)s + 2n + 1i incremental cycles, where s,n and i are defined as sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle), respectively. stm instructions take (n-1)s + 2n incremental cycles to execute, where n is the number of words transferred. S3C2500B instruction set 3- 45 3.11.9 assembler syntax instruction set s3c 2500b 3- 46 examples ldmfd sp!,{r0,r1,r2} ; unstack 3 registers. stmia r0,{r0-r15} ; save all registers. ldmfd sp!,{r15} ; r15 <- (sp), cpsr unchanged. ldmfd sp!,{r15}^ ; r15 <- (sp), cpsr <- spsr_mode ; (allowed only in privileged modes). stmfd r13,{r0-r14}^ ; save user mode regs on stack ; (allowed only in privileged modes). these instructions may be used to save state on subroutine entry, and restore it efficiently on return to the calling routine: stmed sp!,{r0?r3,r14} ; save r0 to r3 to use as workspace ; and r14 for returning. bl somewhere ; this nested call will overwrite r14 ldmed sp!,{r0?r3,r15} ; restore workspace and return. S3C2500B instruction set 3- 47 3.12 single data swap (swp) 31 19 15 cond 28 16 11 12 21 23 b 20 00 rn rd [3:0] source register [15:12] destination register [19:16] base register [22] byte/word bit 0 = swap word quantity 1 = swap word quantity [31:28] condition field 22 00010 0000 rm 1001 27 8 7 4 3 0 figure 3-23. swap instruction the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-23. the data swap instruction is used to swap a byte or word quantity between a register and external memory. this instruction is implemented as a memory read followed by a memory write which are ?locked? together (the processor cannot be interrupted until both operations have completed, and the memory manager is warned to treat them as inseparable). this class of instruction is particularly useful for implementing software semaphores. the swap address is determined by the contents of the base register (rn). the processor first reads the contents of the swap address. then it writes the contents of the source register (rm) to the swap address, and stores the old memory contents in the destination register (rd). the same register may be specified as both the source and destination. the lock output goes high for the duration of the read and write operations to signal to the external memory manager that they are locked together, and should be allowed to complete without interruption. this is important in multi-processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores; control of the memory must not be removed from a processor while it is performing a locked operation. 3.12.1 bytes and words this instruction class may be used to swap a byte (b = 1) or a word (b = 0) between an arm9tdmi register and memory. the swp instruction is implemented as a ldr followed by a str and the action of these is as described in the section on single data transfers. in particular, the description of big and little endian configuration applies to the swp instruction. 3.12.2 use of r15 do not use r15 as an operand (rd, rn or rs) in a swp instruction. instruction set s3c 2500b 3- 48 3.12.3 data aborts if the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving abort high. this can happen on either the read or the write cycle (or both), and in either case, the data abort trap will be taken. it is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. 3.12.4 instruction cycle times swap instructions take 1s + 2n +1i incremental cycles to execute, where s, n and i are defined as squential (s- cycle), non-sequential, and internal (i-cycle), respectively. 3.12.5 assembler syntax S3C2500B instruction set 3- 49 3.13 software interrupt (swi) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-24, below 31 24 27 1111 cond comment field (ignored by processor) 28 23 [31:28] condition field 0 figure 3-24. software interrupt instruction the software interrupt instruction is used to enter supervisor mode in a controlled manner. the instruction causes the software interrupt trap to be taken, which effects the mode change. the pc is then forced to a fixed value (0x08) and the cpsr is saved in spsr_svc. if the swi vector address is suitably protected (by external memory management hardware) from modification by the user, a fully protected operating system may be constructed. 3.13.1 return from the supervisor the pc is saved in r14_svc upon entering the software interrupt trap, with the pc adjusted to point to the word after the swi instruction. movs pc,r14_svc will return to the calling program and restore the cpsr. note that the link mechanism is not re-entrant, so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and spsr. 3.13.2 comment field the bottom 24 bits of the instruction are ignored by the processor, and may be used to communicate information to the supervisor code. for instance, the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions. 3.13.3 instruction cycle times software interrupt instructions take 2s + 1n incremental cycles to execute, where s and n are defined as squential (s-cycle) and non-squential (n-cycle). instruction set s3c 2500b 3- 50 3.13.4 assembler syntax swi{cond} S3C2500B instruction set 3- 51 3.14 coprocessor data operations (cdp) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-25. this class of instruction is used to tell a coprocessor to perform some internal operation. no result is communicated back to arm9tdmi, and it will not wait for the operation to complete. the coprocessor could contain a queue of such instructions awaiting execution, and their execution can overlap other activity, allowing the coprocessor and arm9tdmi to perform independent tasks in parallel. 3.14.1 coprocessor instructions the S3C2500B, unlike some other arm-based processors, does not have an external coprocessor interface. it does not have a on-chip coprocessor also. so then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C2500B. these coprocessor instructions can be emulated by the undefined trap handler. even though external coprocessor can not be connected to the S3C2500B, the coprocessor instructions are still described here in full for completeness. (remember that any external coprocessor described in this section is a software emulation.) 31 24 27 19 15 cond crm 28 16 11 12 23 20 [3:0] coprocessor operand register [7:5] coprocessor information [11:8] coprocessor number [15:12] coprocessor destination register [19:16] coprocessor operand register [23:20] coprocessor operation code [31:28] condition field 0 cp cp# crd crn 1110 cp opc 8 7 5 4 3 0 figure 3-25. coprocessor data operation instruction 3.14.2 the coprocessor fields only bit 4 and bits 24 to 31 are significant to arm9tdmi. the remaining bits are used by coprocessors. the above field names are used by convention, and particular coprocessors may redefine the use of all fields except cp# as appropriate. the cp# field is used to contain an identifying number (in the range 0 to 15) for each coprocessor, and a coprocessor will ignore any instruction which does not contain its number in the cp# field. the conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the cp opc field (and possibly in the cp field) on the contents of crn and crm, and place the result in crd. instruction set s3c 2500b 3- 52 3.14.3 instruction cycle times coprocessor data operations take 1s + bi incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. s and i are defined as sequential (s-cycle) and internal (i-cycle). 3.14.4 assembler syntax cdp{cond} p#, S3C2500B instruction set 3- 53 3.15 coprocessor data transfers (ldc, stc) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-26. this class of instruction is used to load (ldc) or store (stc) a subset of a coprocessor's registers directly to memory. arm9tdmi is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred. [7:0] unsigned 8 bit immediate offset [11:8] coprocessor number [15:12] coprocessor source/destination register [19:16] base register [20] load/store bit 0 = store to memory 1 = load from memory [21] write-back bit 0 = no write-back 1 = write address into base [22] transfer length [23] up/down bit 0 = down: subtract offset from base 1 = up: add offset to base [24] pre/post indexing bit 0 = post: add offset after transfer 1 = pre: add offset bofore transfer [31:28] condition field 31 27 19 15 cond 28 16 11 12 21 23 n 20 l rn crd 22 110 p u cp# w 24 25 offset 8 7 0 figure 3-26. coprocessor data transfer instructions 3.15.1 the coprocessor fields the cp# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field. the crd field and the n bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors, but by convention crd is the register to be transferred (or the first register where more than one is to be transferred), and the n bit is used to choose one of two transfer length options. for instance n = 0 could select the transfer of a single register, and n = 1 could select the transfer of all the registers for context switching. instruction set s3c 2500b 3- 54 3.15.2 addressing modes arm9tdmi is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. note, however, that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and specify byte offsets for single data transfers. the 8 bit unsigned immediate offset is shifted left 2 bits and either added to (u = 1) or subtracted from (u = 0) the base register (rn); this calculation may be performed either before (p = 1) or after (p = 0) the base is used as the transfer address. the modified base value may be overwritten back into the base register (if w = 1), or the old value of the base may be preserved (w = 0). note that post-indexed addressing modes require explicit setting of the w bit, unlike ldr and str which always write-back when post-indexed. the value of the base register, modified by the offset in a pre-indexed instruction, is used as the address for the transfer of the first word. the second word (if more than one is transferred) will go to or come from an address one word (4 bytes) higher than the first transfer, and the address will be incremented by one word for each subsequent transfer. 3.15.3 address alignment the base address should normally be a word aligned quantity. the bottom 2 bits of the address will appear on a[1:0] and might be interpreted by the memory system. 3.15.4 use of r15 if rn is r15, the value used will be the address of the instruction plus 8 bytes. base write-back to r15 must not be specified. 3.15.5 data aborts if the address is legal but the memory manager generates an abort, the data trap will be taken. the write-back of the modified base will take place, but all other processor state will be preserved. the coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved, and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried. 3.15.6 instruction cycle times coprocessor data transfer instructions take (n-1)s + 2n + bi incremental cycles to execute, where: n the number of words transferred. b the number of cycles spent in the coprocessor busy-wait loop. s, n and i are defined as sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle), respectively. S3C2500B instruction set 3- 55 3.15.7 assembler syntax instruction set s3c 2500b 3- 56 3.16 coprocessor register transfers (mrc, mcr) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2.. the instruction encoding is shown in figure 3-27 . this class of instruction is used to communicate information directly between arm9tdmi and a coprocessor. an example of a coprocessor to arm9tdmi register transfer (mrc) instruction would be a fix of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to arm9tdmi register. a float of a 32 bit value in arm9tdmi register into a floating point value within the coprocessor illustrates the use of arm9tdmi register to coprocessor transfer (mcr). an important use of this instruction is to communicate control information directly from the coprocessor into the arm9tdmi cpsr flags. as an example, the result of a comparison of two floating point values within a coprocessor can be moved to the cpsr to control the subsequent flow of execution. 31 27 19 15 cond 28 16 11 12 21 23 20 l crn rd [3:0] coprocessor operand register [7:5] coprocessor information [11:8] coprocessor number [15:12] arm source/destination register [19:16] coprocessor source/destination register [20] load/store bit 0 = store to coprocessor 1 = load from coprocessor [21] coprocessor operation mode [31:28] condition field 1110 cp opc cp# 24 crm 1 cp 8 7 5 4 3 0 figure 3-27. coprocessor register transfer instructions 3.16.1 the coprocessor fields the cp# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon. the cp opc, crn, cp and crm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. other interpretations are allowed where the coprocessor functionality is incompatible with this one. the conventional interpretation is that the cp opc and cp fields specify the operation the coprocessor is required to perform, crn is the coprocessor register which is the source or destination of the transferred information, and crm is a second coprocessor register which may be involved in some way which depends on the particular operation specified. S3C2500B instruction set 3- 57 3.16.2 transfers to r15 when a coprocessor register transfer to arm9tdmi has r15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the n, z, c and v flags respectively. the other bits of the transferred word are ignored, and the pc and other cpsr bits are unaffected by the transfer. 3.16.3 transfers from r15 a coprocessor register transfer from arm9tdmi with r15 as the source register will store the pc+ 12. 3.16.4 instruction cycle times mrc instructions take 1s + (b+1)i +1c incremental cycles to execute, where s, i and c are defined as sequential (s-cycle), internal (i-cycle), and coprocessor register transfer (c-cycle), respectively. mcr instructions take 1s + bi +1c incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. 3.16.5 assembler syntax instruction set s3c 2500b 3- 58 3.17 undefined instruction the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction format is shown in figure 3-28. 31 27 cond 28 25 24 011 xxxxxxxxxxxxxxxxxxxx 1 xxxx 5 4 3 0 figure 3-28. undefined instruction if the condition is true, the undefined instruction trap will be taken. note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving cpa and cpb high. 3.17.1 instruction cycle times this instruction takes 2s + 1i + 1n cycles, where s, n and i are defined as sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle). 3.17.2 assembler syntax the assembler has no mnemonics for generating this instruction. if it is adopted in the future for some specified use, suitable mnemonics will be added to the assembler. until such time, this instruction must not be used. S3C2500B instruction set 3- 59 3.18 instruction set examples the following examples show ways in which the basic arm9tdmi instructions can combine to give efficient code. none of these methods saves a great deal of execution time (although they may save some), mostly they just save code. 3.18.1 using the conditional instructions using conditionals for logical or cmp rn,#p ; if rn=p or rm=q then goto label. beq label cmp rm,#q beq label this can be replaced by cmp rn,#p cmpne rm,#q ; if condition not satisfied try other test. beq label absolute value teq rn,#0 ; test sign rsbmi rn,rn,#0 ; and 2's complement if necessary. multiplication by 4, 5 or 6 (run time) mov rc,ra,lsl#2 ; multiply by 4, cmp rb,#5 ; test value, addcs rc,rc,ra ; complete multiply by 5, addhi rc,rc,ra ; complete multiply by 6. combining discrete and range tests teq rc,#127 ; discrete test, cmpne rc, # ? ? - 1 ; range test movls rc,# ? ? ; if rc<= ? ? or rc=ascii(127) ; then rc:= ? ? instruction set s3c 2500b 3- 60 division and remainder a number of divide routines for specific applications are provided in source form as part of the ansi c library provided with the arm cross development toolkit, available from your supplier. a short general purpose divide routine follows. ; enter with numbers in ra and rb. mov rcnt,#1 ; bit to control the division. div1 cmp rb,#0x80000000 ; move rb until greater than ra. cmpcc rb,ra movcc rb,rb,asl#1 movcc rcnt,rcnt,asl#1 bcc div1 mov rc,#0 div2 cmp ra,rb ; test for possible subtraction. subcs ra,ra,rb ; subtract if ok, addcs rc,rc,rcnt ; put relevant bit into result movs rcnt,rcnt,lsr#1 ; shift control bit movne rb,rb,lsr#1 ; halve unless finished. bne div2 ; divide result in rc, remainder in ra. overflow detection in the arm9tdmi 1. overflow in unsigned multiply with a 32-bit result umull rd,rt,rm,rn ; 3 to 6 cycles teq rt,#0 ; +1 cycle and a register bne overflow 2. overflow in signed multiply with a 32-bit result smull rd,rt,rm,rn ; 3 to 6 cycles teq rt,rd asr#31 ; +1 cycle and a register bne overflow 3. overflow in unsigned multiply accumulate with a 32 bit result umlal rd,rt,rm,rn ; 4 to 7 cycles teq rt,#0 ; +1 cycle and a register bne overflow 4. overflow in signed multiply accumulate with a 32 bit result smlal rd,rt,rm,rn ; 4 to 7 cycles teq rt,rd, asr#31 ; +1 cycle and a register bne overflow S3C2500B instruction set 3- 61 5. overflow in unsigned multiply accumulate with a 64 bit result umull rl,rh,rm,rn ; 3 to 6 cycles adds rl,rl,ra1 ; lower accumulate adc rh,rh,ra2 ; upper accumulate bcs overflow ; 1 cycle and 2 registers 6. overflow in signed multiply accumulate with a 64 bit result smull rl,rh,rm,rn ; 3 to 6 cycles adds rl,rl,ra1 ; lower accumulate adc rh,rh,ra2 ; upper accumulate bvs overflow ; 1 cycle and 2 registers note overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations. 3.18.2 pseudo-random binary sequence generator it is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-or feedback rather like a cyclic redundancy check generator. unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33 bit register with taps at bits 33 and 20. the basic algorithm is newbit: = bit 33 eor bit 20, shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). the entire operation can be done in 5 s cycles: ; enter with seed in ra (32 bits), ; rb (1 bit in rb lsb), uses rc. tst rb,rb,lsr#1 ; top bit into carry movs rc,ra,rrx ; 33 bit rotate right adc rb,rb,rb ; carry into lsb of rb eor rc,rc,ra,lsl#12 ; (involved!) eor ra,rc,rc,lsr#20 ; (similarly involved!) new seed in ra, rb as before 3.18.3 multiplication by constant using the barrel shifter multiplication by 2^n (1,2,4,8,16,32..) mov ra, rb, lsl #n multiplication by 2^n+1 (3,5,9,17..) add ra,ra,ra,lsl #n multiplication by 2^n-1 (3,7,15..) rsb ra,ra, ra,lsl #n instruction set s3c 2500b 3- 62 multiplication by 6 add ra,ra,ra,lsl #1 ; multiply by 3 mov ra,ra,lsl#1 ; and then by 2 multiply by 10 and add in extra number add ra,ra,ra,lsl#2 ; multiply by 5 add ra,rc,ra,lsl#1 ; multiply by 2 and add in next digit general recursive method for rb := ra*c, c a constant: 1. if c even, say c = 2^n*d, d odd: d=1: mov rb,ra,lsl #n d<>1: {rb := ra*d} mov rb,rb,lsl #n 2. if c mod 4 = 1, say c = 2^n*d+1, d odd, n>1: d=1: add rb,ra,ra,lsl #n d<>1: {rb := ra*d} add rb,ra,rb,lsl #n 3. if c mod 4 = 3, say c = 2^n*d-1, d odd, n>1: d=1: rsb rb,ra,ra,lsl #n d<>1: {rb := ra*d} rsb rb,ra,rb,lsl #n this is not quite optimal, but close. an example of its non-optimality is multiply by 45 which is done by: rsb rb,ra,ra,lsl#2 ; multiply by 3 rsb rb,ra,rb,lsl#2 ; multiply by 4*3-1 = 11 add rb,ra,rb,lsl# 2 ; multiply by 4*11+1 = 45 rather than by: add rb,ra,ra,lsl#3 ; multiply by 9 add rb,rb,rb,lsl#2 ; multiply by 5*9 = 45 S3C2500B instruction set 3- 63 3.18.4 loading a word from an unknown alignment ; enter with address in ra (32 bits) uses ; rb, rc result in rd. note d must be less than c e.g. 0,1 bic rb,ra,#3 ; get word aligned address ldmia rb,{rd,rc} ; get 64 bits containing answer and rb,ra,#3 ; correction factor in bytes movs rb,rb,lsl#3 ; ...now in bits and test if aligned movne rd,rd,lsr rb ; produce bottom of result word (if not aligned) rsbne rb,rb,#32 ; get other shift amount orrne rd,rd,rc,lsl rb ; combine two halves to get result instruction set s3c 2500b 3- 64 3.19 thumb instruction set format the thumb instruction sets are 16-bit versions of arm instruction sets (32-bit format). the arm instructions are reduced to 16-bit versions, thumb instructions, at the cost of versatile functions of the arm instruction sets. the thumb instructions are decompressed to the arm instructions by the thumb decompressor inside the arm9tdmi core. as the thumb instructions are compressed arm instructions, the thumb instructions have the 16-bit format instructions and have some restrictions. the restrictions by 16-bit format is fully notified for using the thumb instructions. 3.19.1 format summary the thumb instruction set formats are shown in the following figure. move shifted register 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 l 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 l 1 0 r 1 1 0 1 0 sp 1 l l s h 0 0 1 b l 0 1 h 0 1 b 0 0 1 1 1 i op op op op op l 0 s 1 offset5 rs rd rn/offset3 rd rs rd offset8 rs rd/hd rd h1 h2 rs/hs rd word8 rd rb ro ro rb rd offset5 rb rd rb rd offset5 rd rd word8 word8 sword7 rb cond rlist rlist softset8 value8 offset11 offset add/subtract move/compare/add/ subtract immediate alu operations hi regiter operations /branch exchange pc-relative load load/store with register offset load/store with immediate offset load/store sign-extended byte/halfword load/store halfword sp-relative load/store load address add offset to stack pointer push/pop register multiple load/store conditional branch software interrupt unconditional branch long branch with link 15 14 13 12 11 10 9 8 7 6 5 4 2 3 1 0 15 14 13 12 11 10 9 8 7 6 5 4 2 3 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 figure 3-29. thumb instruction set formats S3C2500B instruction set 3- 65 3.19.2 opcode summary the following table summarises the thumb instruction set. for further information about a particular instruction please refer to the sections listed in the right-most column. table 3-7. thumb instruction set opcodes mnemonic instruction lo-register operand hi-register operand condition codes set adc add with carry v ? v add add v v v (1) and and v ? v asr arithmetic shift right v ? v b unconditional branch v ? ? bxx conditional branch v ? ? bic bit clear v ? v bl branch and link v ? ? bx branch and exchange v v ? cmn compare negative v ? v cmp compare v v v eor eor v ? v ldmia load multiple v ? ? ldr load word v ? ? ldrb load byte v ? ? ldrh load half-word v ? ? lsl logical shift left v ? v ldsb load sign-extended byte v ? ? ldsh load sign-extended half-word v ? ? lsr logical shift right v ? v mov move register v v v (2) mul multiply v ? v mvn move negative register v ? v neg negate v ? v orr or v ? v pop pop registers v ? ? push push registers v ? ? por rotate right v ? v instruction set s3c 2500b 3- 66 table 3-7. thumb instruction set opcodes (continued) mnemonic instruction lo-register operand hi-register operand condition codes set sbc subtract with carry v ? v stmia store multiple v ? ? str store word v ? ? strb store byte v ? ? strh store half-word v ? ? swi software interrupt ? ? ? sub subtract v ? v tst test bits v ? v notes: 1. the condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. the condition codes are unaffected by the format 5 version of this instruction. S3C2500B instruction set 3- 67 3.20 format 1: move shifted register 15 0 0 14 10 [2:0] destination register [5:3] source register [10:6] immediate vale [12:11] opcode 0 = lsl 1 = lsr 2 = asr offset5 6 5 3 2 rd 0 0 13 12 11 op rs figure 3-30. format 1 3.20.1 operation these instructions move a shifted value between lo registers. the thumb assembler syntax is shown in table 3-8. note all instructions in this group set the cpsr condition codes. table 3-8. summary of format 1 instructions op thumb assembler arm equivalent action 00 lsl rd, rs, #offset5 movs rd, rs, lsl #offset5 shift rs left by a 5-bit immediate value and store the result in rd. 01 lsr rd, rs, #offset5 movs rd, rs, lsr #offset5 perform logical shift right on rs by a 5-bit immediate value and store the result in rd. 10 asr rd, rs, #offset5 movs rd, rs, asr #offset5 perform arithmetic shift right on rs by a 5-bit immediate value and store the result in rd. 3.20.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-8. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples lsr r2, r5, #27 ; logical shift right the contents ; of r5 by 27 and store the result in r2. ; set condition codes on the result. instruction set s3c 2500b 3- 68 3.21 format 2: add/subtract 15 0 14 10 [2:0] destination register [5:3] source register [8:6] register/immediate value [9] opcode 0 = add 1 = sub [10] immediate flag 0 = register operand 1 = immediate oerand rn/offset3 rd 0 0 13 12 11 op rs 9 8 1 1 1 6 5 3 2 0 figure 3-31. format 2 3.21.1 operation these instructions allow the contents of a lo register or a 3-bit immediate value to be added to or subtracted from a lo register. the thumb assembler syntax is shown in table 3-9. note all instructions in this group set the cpsr condition codes. table 3-9. summary of format 2 instructions op i thumb assembler arm equivalent action 0 0 add rd, rs, rn adds rd, rs, rn add contents of rn to contents of rs. place result in rd. 0 1 add rd, rs, #offset3 adds rd, rs, #offset3 add 3-bit immediate value to contents of rs. place result in rd. 1 0 sub rd, rs, rn subs rd, rs, rn subtract contents of rn from contents of rs. place result in rd. 1 1 sub rd, rs, #offset3 subs rd, rs, #offset3 subtract 3-bit immediate value from contents of rs. place result in rd. S3C2500B instruction set 3- 69 3.21.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-9. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add r0, r3, r4 ; r0 : = r3 + r4 and set condition codes on the result. sub r6, r2, #6 ; r6 : = r2 - 6 and set condition codes. instruction set s3c 2500b 3- 70 3.22 format 3: move/compare/add/subtract immediate 15 0 0 14 10 [7:0] immediate value [10:8] source/destination register [12:11] opcode 0 = mov 1 = cmp 2 = add 3 = sub offset8 rd 0 0 13 12 11 op 7 8 figure 3-32. format 3 3.22.1 operations the instructions in this group perform operations between a lo register and an 8-bit immediate value. the thumb assembler syntax is shown in table 3-10. note all instructions in this group set the cpsr condition codes. table 3-10. summary of format 3 instructions op thumb assembler arm equivalent action 00 mov rd, #offset8 movs rd, #offset8 move 8-bit immediate value into rd. 01 cmp rd, #offset8 cmp rd, #offset8 compare contents of rd with 8-bit immediate value. 10 add rd, #offset8 adds rd, rd, #offset8 add 8-bit immediate value to contents of rd and place the result in rd. 11 sub rd, #offset8 subs rd, rd, #offset8 subtract 8-bit immediate value from contents of rd and place the result in rd. 3.22.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-10. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples mov r0, #128 ; r0 : = 128 and set condition codes cmp r2, #62 ; set condition codes on r2 - 62 add r1, #255 ; r1 : = r1 + 255 and set condition codes sub r6, #145 ; r6 : = r6 - 145 and set condition codes S3C2500B instruction set 3- 71 3.23 format 4: alu operations 15 0 0 14 10 [2:0] source/destination register [5:3] source register 2 [9:6] opcode 5 6 3 rd 0 0 13 12 11 op rs 0 0 0 9 2 figure 3-33. format 4 3.23.1 operation the following instructions perform alu operations on a lo register pair. note all instructions in this group set the cpsr condition codes table 3-11. summary of format 4 instructions op thumb assembler arm equivalent action 0000 and rd, rs ands rd, rd, rs rd: = rd and rs 0001 eor rd, rs eors rd, rd, rs rd: = rd eor rs 0010 lsl rd, rs movs rd, rd, lsl rs rd : = rd << rs 0011 lsr rd, rs movs rd, rd, lsr rs rd : = rd >> rs 0100 asr rd, rs movs rd, rd, asr rs rd : = rd asr rs 0101 adc rd, rs adcs rd, rd, rs rd : = rd + rs + c-bit 0110 sbc rd, rs sbcs rd, rd, rs rd : = rd - rs - not c-bit 0111 ror rd, rs movs rd, rd, ror rs rd : = rd ror rs 1000 tst rd, rs tst rd, rs set condition codes on rd and rs 1001 neg rd, rs rsbs rd, rs, #0 rd = - rs 1010 cmp rd, rs cmp rd, rs set condition codes on rd - rs 1011 cmn rd, rs cmn rd, rs set condition codes on rd + rs 1100 orr rd, rs orrs rd, rd, rs rd: = rd or rs 1101 mul rd, rs muls rd, rs, rd rd: = rs * rd 1110 bic rd, rs bics rd, rd, rs rd: = rd and not rs 1111 mvn rd, rs mvns rd, rs rd: = not rs instruction set s3c 2500b 3- 72 3.23.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-11. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples eor r3, r4 ; r3 : = r3 eor r4 and set condition codes ror r1, r0 ; rotate right r1 by the value in r0, store ; the res ult in r1 and set condition codes neg r5, r3 ; subtract the contents of r3 from zero, ; store the result in r5. set condition codes ie r5 = - r3 cmp r2, r6 ; set the condition codes on the result of r2 - r6 mul r0, r7 ; r0 : = r7 * r0 and set condition codes S3C2500B instruction set 3- 73 3.24 format 5: hi-register operations/branch exchange 15 0 0 14 10 [2:0] destination register [5:3] source register [6] hi operand flag 2 [7] hi operand flag 1 [9:8] opcode 6 5 3 2 rd/hd 0 0 13 12 11 op rs/hs 0 0 0 9 8 7 h1 h2 figure 3-34. format 5 3.24.1 operation there are four sets of instructions in this group. the first three allow add, cmp and mov operations to be performed between lo and hi registers, or a pair of hi registers. the fourth, bx, allows a branch to be performed which may also be used to switch processor state. the thumb assembler syntax is shown in table 3-12. note in this group only cmp (op = 01) sets the cpsr condition codes. the action of h1 = 0, h2 = 0 for op = 00 (add), op = 01 (cmp) and op = 10 (mov) is undefined, and should not be used. instruction set s3c 2500b 3- 74 table 3-12. summary of format 5 instructions op h1 h2 thumb assembler arm equivalent action 00 0 1 add rd, hs add rd, rd, hs add a register in the range 8-15 to a register in the range 0-7. 00 1 0 add hd, rs add hd, hd, rs add a register in the range 0-7 to a register in the range 8-15. 00 1 1 add hd, hs add hd, hd, hs add two registers in the range 8-15. 01 0 1 cmp rd, hs cmp rd, hs compare a register in the range 0-7 with a register in the range 8-15. set the condition code flags on the result. 01 1 0 cmp hd, rs cmp hd, rs compare a register in the range 8-15 with a register in the range 0-7. set the condition code flags on the result. 01 1 1 cmp hd, hs cmp hd, hs compare two registers in the range 8-15. set the condition code flags on the result. 10 0 1 mov rd, hs mov rd, hs move a value from a register in the range 8-15 to a register in the range 0-7. 10 1 0 mov hd, rs mov hd, rs move a value from a register in the range 0-7 to a register in the range 8-15. 00 0 1 mov hd, hs mov hd, hs move a value between two registers in the range 8-15. 00 1 0 bx rs bx rs perform branch (plus optional state change) to address in a register in the range 0-7. 00 1 1 bx hs bx hs perform branch (plus optional state change) to address in a register in the range 8-15. 3.24.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-12. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. 3.24.3 the bx instruction bx performs a branch to a routine whose start address is specified in a lo or hi register. bit 0 of the address determines the processor state on entry to the routine: bit 0 = 0 causes the processor to enter arm state. bit 0 = 1 causes the processor to enter thumb state. note the action of h1 = 1 for this instruction is undefined, and should not be used. S3C2500B instruction set 3- 75 examples hi-register operations add pc, r5 ; pc := pc + r5 but don't set the condition codes.cmp r4, r12 ; set the condition codes on the result of r4 - r12. mov r15, r14 ; move r14 (lr) into r15 (pc) ; but don't set the condition codes, ; eg. return from subroutine. branch and exchange ; switch from thumb to arm state. adr r1,outofthumb ; load address of outofthumb into r1. mov r11,r1 bx r11 ; transfer the contents of r11 into the pc. ; bit 0 of r11 determines whether ; arm or thumb state i s entered, ie. arm state here. ... align code32 outofthumb ; now processing arm instructions... 3.24.4 using r15 as an operand if r15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. executing a bx pc in thumb state from a non-word aligned address will result in unpredictable execution. instruction set s3c 2500b 3- 76 3.25 format 6: pc-relative load 15 0 0 14 10 [7:0] immediate value [10:8] destination register word 8 0 0 13 12 11 rd 0 0 8 7 figure 3-35. format 6 3.25.1 operation this instruction loads a word from an address specified as a 10-bit immediate offset from the pc. the thumb assembler syntax is shown below. table 3-13. summary of pc-relative load instruction thumb assembler arm equivalent action ldr rd, [pc, #imm] ldr rd, [r15, #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the pc. load the word from the resulting address into rd. note: the value specified by #imm is a full 10-bit address, but must always be word-aligned (ie with bits 1:0 set to 0), since the assembler places #imm >> 2 in field word 8. the value of the pc will be 4 bytes greater than the address of this instruction, but bit 1 of the pc is forced to 0 to ensure it is word aligned. 3.25.2 instruction cycle times all instructions in this format have an equivalent arm instruction. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples ldr r3,[pc,#844] ; load into r3 the word found at the ; address formed by adding 844 to pc. ; bit[1] of pc is forced to zero. ; note that the thumb opcode will contain ; 211 as the word8 value. S3C2500B instruction set 3- 77 3.26 format 7: load/store with register offset [2:0] source/destination register [5:3] base register [8:6] offset register [10] byte/word flag 0 = transfer word quantity 1 = transfer byte quantity [11] load/store flag 0 = store to memory 1 = load from memory 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 1 l b 9 8 ro 0 figure 3-36. format 7 3.26.1 operation these instructions transfer byte or word values between registers and memory. memory addresses are pre- indexed using an offset register in the range 0-7. the thumb assembler syntax is shown in table 3-14. table 3-14. summary of format 7 instructions l b thumb assembler arm equivalent action 0 0 str rd, [rb, ro] str rd, [rb, ro] pre-indexed word store: calculate the target address by adding together the value in rb and the value in ro. store the contents of rd at the address. 0 1 strb rd, [rb, ro] strb rd, [rb, ro] pre-indexed byte store: calculate the target address by adding together the value in rb and the value in ro. store the byte value in rd at the resulting address. 1 0 ldr rd, [rb, ro] ldr rd, [rb, ro] pre-indexed word load: calculate the source address by adding together the value in rb and the value in ro. load the contents of the address into rd. 1 1 ldrb rd, [rb, ro] ldrb rd, [rb, ro] pre-indexed byte load: calculate the source address by adding together the value in rb and the value in ro. load the byte value at the resulting address. instruction set s3c 2500b 3- 78 3.26.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-14. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples str r3, [r2,r6] ; store word in r3 at the address ; formed by adding r6 to r2. ldrb r2, [r0,r7] ; load into r2 the byte found at ; the address formed by adding r7 to r0. S3C2500B instruction set 3- 79 3.27 format 8: load/store sign-extended byte/half-word [2:0] destination register [5:3] base register [8:6] offset register [10] sign-extended flag 0 = operand not sing-extended 1 = operand sing-extended [11] h flag 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 1 h s 9 8 ro 1 figure 3-37. format 8 3.27.1 operation these instructions load optionally sign-extended bytes or half-words, and store half-words. the thumb assembler syntax is shown below. table 3-15. summary of format 8 instructions l b thumb assembler arm equivalent action 0 0 strh rd, [rb, ro] strh rd, [rb, ro] store half-word: add ro to base address in rb. store bits 0?15 of rd at the resulting address. 0 1 ldrh rd, [rb, ro] ldrh rd, [rb, ro] load half-word: add ro to base address in rb. load bits 0?15 of rd from the resulting address, and set bits 16-31 of rd to 0. 1 0 ldsb rd, [rb, ro] ldrsb rd, [rb, ro] load sign-extended byte: add ro to base address in rb. load bits 0?7 of rd from the resulting address, and set bits 8-31 of rd to bit 7. 1 1 ldsh rd, [rb, ro] ldrsh rd, [rb, ro] load sign-extended half-word: add ro to base address in rb. load bits 0?15 of rd from the resulting address, and set bits 16-31 of rd to bit 15. instruction set s3c 2500b 3- 80 3.27.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-15. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples strh r4, [r3, r0] ; store the lower 16 bits of r4 at the ; address formed by adding r0 to r3. ldsb r2, [r7, r1] ; load into r2 the sign extended byte ; found at the address formed b y adding r1 to r7. ldsh r3, [r4, r2] ; load into r3 the sign extended half-word ; found at the address formed by adding r2 to r4. S3C2500B instruction set 3- 81 3.28 format 9: load/store with immediate offset [2:0] source/destination register [5:3] base register [10:6] offset register [11] load/store flag 0 = store to memory 1 = load from memory [12] byte/word flad 0 = transfer word quantity 1 = transfer byte quantity 15 0 0 14 10 6 5 3 2 rd 1 1 13 12 11 rb b l offset5 figure 3-38. format 9 3.28.1 operation these instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. the thumb assembler syntax is shown in table 3-16 table 3-16. summary of format 9 instructions l b thumb assembler arm equivalent action 0 0 str rd, [rb, #imm] str rd, [rb, #imm] calculate the target address by adding together the value in rb and imm. store the contents of rd at the address. 0 1 ldr rd, [rb, #imm] ldr rd, [rb, #imm] calculate the source address by adding together the value in rb and imm. load rd from the address. 1 0 strb rd, [rb, #imm] strb rd, [rb, #imm] calculate the target address by adding together the value in rb and imm. store the byte value in rd at the address. 1 1 ldrb rd, [rb, #imm] ldrb rd, [rb, #imm] calculate source address by adding together the value in rb and imm. load the byte value at the address into rd. note: for word accesses (b = 0), the value specified by #imm is a full 7-bit address, but must be word-aligned (ie with bits 1:0 set to 0), since the assembler places #imm >> 2 in the offset5 field. instruction set s3c 2500b 3- 82 3.28.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-16. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples ldr r2, [r5,#116] ; load into r2 the word found at the ; address formed by adding 116 to r5. ; note that the thumb opcode will ; contain 29 as the offset5 value. strb r1, [r0,#13] ; store the lower 8 bits of r1 at the ; address formed by adding 13 to r0. ; note that the thumb opcode will ; contain 13 as the offset5 value. S3C2500B instruction set 3- 83 3.29 format 10: load/store half-word [2:0] source/destination register [5:3] base register [10:6] immediate value [11] load/store flag 0 = store to memory 1 = load from memory 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 0 l offset5 figure 3-39. format 10 3.29.1 operation these instructions transfer half-word values between a lo register and memory. addresses are pre-indexed, using a 6-bit immediate value. the thumb assembler syntax is shown in table 3-17. table 3-17. half-word data transfer instructions l thumb assembler arm equivalent action 0 strh rd, [rb, #imm] strh rd, [rb, #imm] add #imm to base address in rb and store bits 0?15 of rd at the resulting address. 1 ldrh rd, [rb, #imm] ldrh rd, [rb, #imm] add #imm to base address in rb. load bits 0?15 from the resulting address into rd and set bits 16-31 to zero. note: #imm is a full 6-bit address but must be half-word-aligned (ie with bit 0 set to 0), since the assembler places #imm >> 1 in the offset5 field. 3.29.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-17. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples strh r6, [r1, #56] ; store the lower 16 bits of r4 at the address formed by ; adding 56 r1. note that the thumb opcode will contain ; 28 as the offset5 value. ldrh r4, [r7, #4] ; load into r4 the half-word found at the address formed by ; adding 4 to r7. note that the thumb opcode will ; contain 2 as the offset5 value. instruction set s3c 2500b 3- 84 3.30 format 11: sp-relative load/store [7:0] immediate value [10:8] destination register [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 0 0 13 12 11 word 8 1 l rd 7 8 figure 3-40. format 11 3.30.1 operation the instructions in this group perform an sp-relative load or store. the thumb assembler syntax is shown in the following table. table 3-18. sp-relative load/store instructions l thumb assembler arm equivalent action 0 str rd, [sp, #imm] str rd, [r13 #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the sp (r7). store the contents of rd at the resulting address. 1 ldr rd, [sp, #imm] ldr rd, [r13 #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the sp (r7). load the word from the resulting address into rd. note: the offset supplied in #imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0), since the assembler places #imm >> 2 in the word8 field. 3.30.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-18. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples str r4, [sp,#492] ; store the contents of r4 at the address ; formed by adding 492 to sp (r13). ; note that the thumb opcode will contain ; 123 as the word8 value. S3C2500B instruction set 3- 85 3.31 format 12: load addres [7:0] 8-bit unsigned constant [10:8] destination register [11] source 0 = pc 1 = sp 15 0 1 14 10 0 1 13 12 11 word 8 0 sp rd 7 8 figure 3-41. format 12 3.31.1 operation these instructions calculate an address by adding an 10-bit constant to either the pc or the sp, and load the resulting address into a register. the thumb assembler syntax is shown in the following table. table 3-19. load address sp thumb assembler arm equivalent action 0 add rd, pc, #imm add rd, r15, #imm add #imm to the current value of the program counter (pc) and load the result into rd. 1 add rd, sp, #imm add rd, r13, #imm add #imm to the current value of the stack pointer (sp) and load the result into rd. note: the value specified by #imm is a full 10-bit value, but this must be word-aligned (ie with bits 1:0 set to 0) since the assembler places #imm >> 2 in field word 8. where the pc is used as the source register (sp = 0), bit 1 of the pc is always read as 0. the value of the pc will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0. the cpsr condition codes are unaffected by these instructions. instruction set s3c 2500b 3- 86 3.31.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-19. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add r2, pc, #572 ; r2: = pc + 572, but don't set the ; condition codes. bit[1] of pc is forced to zero. ; note that the thumb opcode will ; contain 143 as the word8 value. add r6, sp, #212 ; r6: = sp (r13) + 212, but don't ; set the condition codes. ; note that the thumb opcode will ; contain 53 as the word 8 value. S3C2500B instruction set 3- 87 3.32 format 13: add offset to stack pointer [6:0] 7-bit immediate value [7] sign flag 0 = offset is positive 1 = offset is negative 15 0 1 14 10 0 1 13 12 11 sword 7 1 0 0 7 8 9 6 0 0 s figure 3-42. format 13 3.32.1 operation this instruction adds a 9-bit signed constant to the stack pointer. the following table shows the thumb assembler syntax. table 3-20. the add sp instruction s thumb assembler arm equivalent action 0 add sp, #imm add r13, r13, #imm add #imm to the stack pointer (sp). 1 add sp, #-imm sub r13, r13, #imm add #-imm to the stack pointer (sp). note: the offset specified by #imm can be up to -/+ 508, but must be word-aligned (ie with bits 1:0 set to 0) since the assembler converts #imm to an 8-bit si gn + magnitude number before placing it in field sword7. the condition codes are not set by this instruction. 3.32.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-20. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add sp, #268 ; sp (r13): = sp + 268, but don't set the condition codes. ; note that the thumb opcode will ; contain 67 as the word7 value and s = 0. add sp, #-104 ; sp (r13): = sp - 104, but don't set the condition codes. ; note that the thumb opcode will contain ; 26 as the word7 value and s = 1. instruction set s3c 2500b 3- 88 3.33 format 14: push/pop registers [7:0] register list [8] pc/lr bit 0 = do not store lr/load pc 1 = store lr/load pc [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 0 1 13 12 11 rlist 1 l 0 7 8 9 1 r figure 3-43. format 14 3.33.1 operation the instructions in this group allow registers 0-7 and optionally lr to be pushed onto the stack, and registers 0-7 and optionally pc to be popped off the stack. the thumb assembler syntax is shown in table 3-21. note the stack is always assumed to be full descending. table 3-21. push and pop instructions l b thumb assembler arm equivalent action 0 0 push { rlist } stmdb r13!, { rlist } push the registers specified by rlist onto the stack. update the stack pointer. 0 1 push { rlist, lr } stmdb r13!, { rlist, r14} push the link register and the registers specified by rlist (if any) onto the stack. update the stack pointer. 1 0 pop { rlist } ldmia r13!, { rlist } pop values off the stack into the registers specified by rlist. update the stack pointer. 1 1 pop { rlist, pc } ldmia r13!, {rlist, r15} pop values off the stack and load into the registers specified by rlist. pop the pc off the stack. update the stack pointer. S3C2500B instruction set 3- 89 3.33.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-21. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples push {r0 ?r4,lr} ; store r0, r1, r2, r3, r4 and r14 (lr) at ; the stack pointed to by r13 (sp) and update r13. ; useful at start of a sub-routine to ; save workspace and return address. pop {r2, r6, pc} ; load r2, r6 and r15 (pc) from the stack ; pointed to by r13 (sp) and update r13. ; useful to restore workspace and return from sub-routine. instruction set s3c 2500b 3- 90 3.34 format 15: multiple load/store [7:0] register list [10:8] base register [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 1 0 13 12 11 rlist 0 l 7 8 rb figure 3-44. format 15 3.34.1 operation these instructions allow multiple loading and storing of lo registers. the thumb assembler syntax is shown in the following table. table 3-22. the multiple load/store instructions l thumb assembler arm equivalent action 0 stmia rb!, { rlist } stmia rb!, { rlist } store the registers specified by rlist, starting at the base address in rb. write back the new base address. 1 ldmia rb!, { rlist } ldmia rb!, { rlist } load the registers specified by rlist, starting at the base address in rb. write back the new base address. 3.34.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-22. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples stmia r0!, {r3-r7} ; store the contents of registers r3-r7 ; starting at the address specified in ; r0, incrementing the addresses for each word. ; write back the updated value of r0. S3C2500B instruction set 3- 91 3.35 format 16: conditional branch [7:0] 8-bit signed immediate [11:8] condition 15 0 1 14 1 0 13 12 11 soffset 8 1 7 8 cond figure 3-45. format 16 3.35.1 operation the instructions in this group all perform a conditional branch depending on the state of the cpsr condition codes. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. the thumb assembler syntax is shown in the following table. table 3-23. the conditional branch instructions code thumb assembler arm equivalent action 0000 beq label beq label branch if z set (equal) 0001 bne label bne label branch if z clear (not equal) 0010 bcs label bcs label branch if c set (unsigned higher or same) 0011 bcc label bcc label branch if c clear (unsigned lower) 0100 bmi label bmi label branch if n set (negative) 0101 bpl label bpl label branch if n clear (positive or zero) 0110 bvs label bvs label branch if v set (overflow) 0111 bvc label bvc label branch if v clear (no overflow) 1000 bhi label bhi label branch if c set and z clear (unsigned higher) 1001 bls label bls label branch if c clear or z set (unsigned lower or same) 1010 bge label bge label branch if n set and v set, or n clear and v clear (greater or equal) instruction set s3c 2500b 3- 92 table 3-23. the conditional branch instructions (continued) code thumb assembler arm equivalent action 1011 blt label blt label branch if n set and v clear, or n clear and v set (less than) 1100 bgt label bgt label branch if z clear, and either n set and v set or n clear and v clear (greater than) 1101 ble label ble label branch if z set, or n set and v clear, or n clear and v set (less than or equal) notes: 1. while label specifies a full 9-bit two?s complement address, this must always be half-word-aligned (ie with bit 0 set to 0) since the assembler actually places label >> 1 in field soffset8. 2. cond = 1110 is undefined, and should not be used. cond = 1111 creates the swi instruction: see . 3.35.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-23. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples cmp r0, #45 ; branch to over-if r0 > 45. bgt over ; note that the thumb opcode will contain ... ; the number of half-words to offset. ... over ... ; must be half-word aligned. ... S3C2500B instruction set 3- 93 3.36 format 17: software interrupt [7:0] comment field 15 0 1 14 1 0 13 12 11 value 8 1 7 8 10 9 1 1 1 1 figure 3-46. format 17 3.36.1 operation the swi instruction performs a software interrupt. on taking the swi, the processor switches into arm state and enters supervisor (svc) mode. the thumb assembler syntax for this instruction is shown below. table 3-24. the swi instruction thumb assembler arm equivalent action swi value 8 swi value 8 perform software interrupt: move the address of the next instruction into lr, move cpsr to spsr, load the swi vector address (0x8) into the pc. switch to arm state and enter svc mode. note: value 8 is used solely by the swi handler; it is ignored by the processor. 3.36.2 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-24. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples swi 18 ; take the software interrupt exception. ; enter supervisor mode with 18 as the ; requested swi number. instruction set s3c 2500b 3- 94 3.37 format 18: unconditional branch [10:0] immediate value 15 0 1 14 1 1 13 12 11 offset11 0 10 0 figure 3-47. format 18 3.37.1 operation this instruction performs a pc-relative branch. the thumb assembler syntax is shown below. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. table 3-25. summary of branch instruction thumb assembler arm equivalent action b label bal label (half-word offset) branch pc relative +/- offset11 << 1, where label is pc +/- 2048 bytes. note: the address specified by label is a full 12-bit two s complement address, but must always be half-word aligned (ie bit 0 set to 0), since the assembler places label >> 1 in the offset11 field. examples here b here ; branch onto itself. assembles to 0xe7fe. ; (note effect of pc offset). b jimmy ; branch to 'jimmy'. ... ; note that the thumb opcode will contain the number of ; half-words to offs et. jimmy ... ; must be half-word aligned. S3C2500B instruction set 3- 95 3.38 format 19: long branch with link [10:0] long branch and link offset high/low [11] low/high offset bit 0 = offset high 1 = offset low 15 0 1 14 1 1 13 12 11 offset 1 10 h figure 3-48. format 19 3.38.1 operation this format specifies a long branch with link. the assembler splits the 23-bit two?s complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two thumb instructions. 3.38.1.1 instruction 1 (h = 0) in the first instruction the offset field contains the upper 11 bits of the target address. this is shifted left by 12 bits and added to the current pc address. the resulting address is placed in lr. 3.38.1.2 instruction 2 (h =1) in the second instruction the offset field contains an 11-bit representation lower half of the target address. this is shifted left by 1 bit and added to lr. lr, which now contains the full 23-bit address, is placed in pc, the address of the instruction following the bl is placed in lr and bit 0 of lr is set. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. instruction set s3c 2500b 3- 96 3.38.2 instruction cycle times this instruction format does not have an equivalent arm instruction. table 3-26. the bl instruction h thumb assembler arm equivalent action 0 bl label none lr := pc + offsethigh << 12 1 temp := next instruction address pc := lr + offsetlow << 1 lr := temp | 1 examples bl faraway ; unconditionally branch to 'faraway' next ... ; and place following instruction ; address, ie ?next? , in r14,the link ; register and set bit 0 of lr high. ; note that the thumb opcodes will ; contain the number of half-words to offset. faraway ... ; must be half-word aligned. S3C2500B instruction set 3- 97 3.39 instruction set examples the following examples show ways in which the thumb instructions may be used to generate small and efficient code. each example also shows the arm equivalent so these may be compared. 3.39.1 multiplication by a constant using shifts and adds the following shows code to multiply by various constants using 1, 2 or 3 thumb instructions alongside the arm equivalents. for other constants it is generally better to use the built-in mul instruction rather than using a sequence of 4 or more instructions. thumb arm 1. multiplication by 2^n (1,2,4,8,...) lsl ra, rb, lsl #n ; mov ra, rb, lsl #n 2. multiplication by 2^n+1 (3,5,9,17,...) lsl rt, rb, #n ; add ra, rb, rb, lsl #n add ra, rt, rb 3. multiplication by 2^n-1 (3,7,15,...) lsl rt, r b, #n ; rsb ra, rb, rb, lsl #n sub ra, rt, rb 4. multiplication by -2^n (-2, -4, -8, ...) lsl ra, rb, #n ; mov ra, rb, lsl #n mvn ra, ra ; rsb ra, ra, #0 5. multiplication by -2^n-1 (-3, -7, -15, ...) lsl rt, rb, #n ; sub ra, rb, rb, lsl #n sub ra, rb, rt multiplication by any c = {2^n+1, 2^n-1, -2^n or -2^n-1} * 2^n effectively this is any of the multiplications in 2 to 5 followed by a final shift. this allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) ; (2..5) lsl ra, ra, #n ; mov ra, ra, lsl #n instruction set s3c 2500b 3- 98 3.39.2 general purpose signed divide this example shows a general purpose signed divide and remainder routine in both thumb and arm code. 3.39.2.1 thumb code ;signed_divide ; signed divide of r1 by r0: returns quotient in r0, ; remainder in r1 ;get abs value of r0 into r3 asr r2, r0, #31 ; get 0 or -1 in r2 depending on sign of r0 eor r0, r2 ; eor with -1 (0xffffffff) if negative sub r3, r0, r2 ; and add 1 (sub -1 ) to get abs value ;sub always sets flag so go & report division by 0 if necessary beq divide_by_zero ;get abs value of r1 by xoring with 0xffffffff and adding 1 if negative asr r0, r1, #31 ; get 0 or -1 in r3 depending on sign of r1 eor r1, r0 ; eor with -1 (0xffffffff) if negative sub r1, r0 ; and add 1 (sub -1) to get abs value ;save signs (0 or -1 in r0 & r2) for later use in determining ; sign of quotient & remainder. push {r0, r2} ;justification, shift 1 bit at a time until divisor (r0 value) ; is just <= than dividend (r1 value). to do this shift dividend ; right by 1 and stop as soon as shifted value becomes >. lsr r0, r1, #1 mov r2, r3 b %ft0 just_l lsl r2, #1 0 cmp r2, r0 bls just_l mov r0, #0 ; set accumulator to 0 b %ft0 ; branch into division loop div_l lsr r2, #1 0 cmp r1, r2 ; test subtract bcc %ft0 sub r1, r2 ; if successful do a real subtract 0 adc r0, r0 ; shift result and add 1 if subtract succeeded cmp r2, r3 ; terminate when r2 == r3 (ie we have just bne div_l ; teste d subtracting the 'ones' value). ;now fix up the signs of the quotient (r0) and remainder (r1) pop {r2, r3} ; get dividend/divisor signs back eor r3, r2 ; result sign eor r0, r3 ; negate if result sign = -1 sub r0, r3 eor r1, r2 ; negate remainder if dividend sign = -1 sub r1, r2 mov pc, lr S3C2500B instruction set 3- 99 3.39.2.2 arm code signed_divide ; effectively zero a4 as top bit will be shifted out later ands a4, a1, #&80000000 rsbmi a1, a1, #0 eors ip, a4, a2, asr #32 ;ip bit 31 = sign of result ;ip bit 30 = sign of a2 rsbcs a2, a2, #0 ;central part is identical code to udiv (without mov a4, #0 which comes for free as part of signed entry sequence) movs a3, a1 beq divide_by_zero just_l ; justification stage shifts 1 bit at a time cmp a3, a2, lsr #1 movls a3, a3, lsl #1 ; nb: lsl #1 is always ok if ls succeeds blo s_loop div_l cmp a2, a3 adc a4, a4, a4 subcs a2, a2, a3 teq a3, a1 movne a3, a3, lsr #1 bne s_loop2 mov a1, a4 movs ip, ip, as l #1 rsbcs a1, a1, #0 rsbmi a2, a2, #0 mov pc, lr instruction set s3c 2500b 3- 100 3.39.3 division by a constant division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. here is an example of a divide by 10 routine based on the algorithm in the arm cookbook in both thumb and arm code. 3.39.3.1 thumb code udiv10 ; take argument in a1 returns quotient in a1, ; remainder in a2 mov a2, a1 lsr a3, a1, #2 sub a1, a3 lsr a3, a1, #4 add a1, a3 lsr a3, a1, #8 add a1, a3 lsr a3, a1, #16 add a1, a3 lsr a1, #3 asl a3, a1, #2 add a3, a1 asl a3, #1 sub a2, a3 cmp a2, #10 blt %ft0 add a1, #1 sub a2, #10 0 mov pc, lr 3.39.3.2 arm code udiv10 ; take argument in a1 returns quotient in a1, ; remainder in a2 sub a2, a1, #10 sub a1, a1, a1, lsr #2 add a1, a1, a1, lsr #4 add a1, a1, a1, lsr #8 add a1, a1, a1, lsr #16 mov a1, a1, lsr #3 add a3, a1, a1, asl #2 subs a2, a2, a3, asl #1 addpl a1, a1, #1 addmi a2, a2, #10 mov pc, lr S3C2500B system con figuration 4- 1 4 system configuratio n 4.1 overview the system configuration consists of several functions that control the clock configuration, system bus arbitration method and address remap function etc. 4.2 features key features of the system configuration include the following; various clock mode operation - the fastbus mode, sync mode and async mode product code and revision number system clock control / clock status peripheral clock enable / disable ahb bus master priority define (fixed / round-robin) core, system, usb, phy pll configuration register setting. system configuration S3C2500B 4- 2 4.3 address map reserved internal register sdram #1 sdram #0 reserved ext i/o bank #7 ext i/o bank #6 ext i/o bank #5 ext i/o bank #4 ext i/o bank #3 ext i/o bank #1 ext i/o bank #2 ext i/o bank #0 reserved 0xffffffff 0xf0000000 0x88000000 0x80000000 0x40000000 0x08000000 0x07000000 0x06000000 0x05000000 0x04000000 0x03000000 0x02000000 0x01000000 0x00000000 0x48000000 figure 4-1. S3C2500B address map after resest each memory block is mapped within the fixed location of memory space. as shown in the figure 4-1, the maximum size of rom/sram/flash/external io bank is restricted to 16m-bytes and the sdram bank can be mapped within 1g-byte memory space. it must be noticed that the base address of each bank is fixed and the bank size is variable. although the sdram bank size are up to 1g-bytes in the figure 4-1, the possible maximum size is 128m-bytes because the sdram controller can supports 256m-bit sdram component. S3C2500B system con figuration 4- 3 4.4 remap of memory space the S3C2500B supports the address remap function. when the remap function is enabled, the base address of each memory bank is changed as follows : table 4-1. the base address of remapped memory before remap after remap memory bank0 0x00000000 0x80000000 memory bank1 0x01000000 0x81000000 memory bank2 0x02000000 0x82000000 memory bank3 0x03000000 0x83000000 memory bank4 0x04000000 0x84000000 memory bank5 0x05000000 0x85000000 memory bank6 0x06000000 0x86000000 memory bank7 0x07000000 0x87000000 sdram bank0 0x40000000 0x00000000 sdram bank1 0x80000000 0x40000000 4.5 external address translation the S3C2500B address bus is , in some respects, different than the bus used in other standard cpus. based on the required data bus width of each memory bank, the internal system address bus is shifted out to an external address bus, addr[23:0]. data bus width external address pins, addr[23:0] accessible memory size 8-bit a23-a0 (internal) 16m-byte 16-bit a24-a1 (internal) 8m-half-word 32-bit a25-a2 (internal) 4m-word system configuration S3C2500B 4- 4 data bus width configuration (8/16/32-bit) external address pins addr[23:0] 8 bit 16 bit 32 bit external internal haddr[23:0] haddr[24:1] haddr[25:2] figure 4-2. external address bus diagram 4.6 arbitration scheme the S3C2500B can support the fixed priority and the round-robin method for ahb bus arbitration by register setting. especially, the S3C2500B can program the priority order in the fixed priority mode as well as the ratio of the bus occupancy in the round-robin priority mode. the internal function blocks or ahb bus masters are divided into three groups, group a, group b, and group c. group a has only test interface controller (tic) block. the group a has the highest bus priority. group b has 6 ahb bus masters, general dma, ethernet controller 0, ethernet controller 1, hdlc controller 0, hdlc controller 1, and hdlc controller 2. the S3C2500B can program the bus priority of each bus masters among group b. so the bus priority of bus masters in only group b can be programmed. group c has the arm940t cpu. the relative priority of group b and group c is determined more or less in an alternating manner. the local priority of six channels of general dma can be programmed by fixed priority or round-robin priority in similar manner to the ahb bus priority. please refer to the general dma chapter. table 4-2. ahb bus priorities for arbitration function block ahb bus priority (group) test interface controller (tic) group a (highest priority) general dma (gdma) group b ethernet controller 0 group b ethernet controller 1 group b hdlc controller 0 group b hdlc controller 1 group b hdlc controller 2 group b arm940t cpu group c S3C2500B system con figuration 4- 5 tic group a arm940t group b group c general dma ethernet controller 0 ethernet controller 1 hdlc controller 2 hdlc controller 1 hdlc controller 0 figure 4-3. priority groups of S3C2500B ahb bus programmable priority register are hprif(programmable priority register for fixed) and hprir (programmable priority register for round-robin). if system configuration register (0xf0000000) syscfg[0] = 0x1, the programmable fixed priority is run by hprif register. each master has its own fixed priority index. for example, gdma has the index 0. the reset value of hprif register is 0x00543210. the first field of hprif[3:0] indicates the highest priority. so, the gdma has the highest ahb master when syscfg[0] = 0x1 and the hprif has the reset value. for example, syscfg[0] = 0x1 and the hprif is 0x00432501, the fixed priority order from the highest to the lowest is ethernet controller 0, general dma, hdlc controller 2, ethernet controller 1, hdlc controller 0, and hdlc controller 1. if system configuration register (0xf0000000) syscfg[0] = 0x0, the programmable round-robin priority is run by hprir register. all ahb bus masters own their respective field position in hprir. the ratio of the bus occupancy can be programmed by writing an arbitrary value on each field. the arbitrary value can be 0x0 to 0xf. the ratio of the bus occupancy of the bus master in the first field is (hprir0+1)/((hprir5+1)+(hprir4+1)+(hprir3+1)+(hprir2+1)+(hprir1+1)+(hprir0+1)). the reset value of hprir register is 0x00000000. so each master has the same bus occupancy ratio when syscfg[0] = 0x0 and the hprir has the reset value. for example, syscfg[0] = 0x0 and the hprir is 0x0011f001, the expected ratios of the bus occupancy of the bus masters, general dma, ethernet controller 0, ethernet controller 1, hdlc controller 0, hdlc controller 1, and hdlc controller 2, are 2/24, 1/24, 1/24, 16/24, 2/24, and 2/24, respectively. system configuration S3C2500B 4- 6 hprir 16 15 12 11 8 7 4 3 0 19 20 23 hprir0 hprir1 hprir2 hprir3 hprir4 hprir5 24 31 reserved high priority low priority hprif 16 15 12 11 8 7 4 3 0 19 20 23 hprif0 hprif1 hprif2 hprif3 hprif4 hprif5 24 31 reserved ahb masters index for hprif field for hprir general dma (gdma) 0 hprir[3:0] ethernet contoller 0 1 hprir[7:4] ethernet contoller 1 2 hprir[11:8] hdlc controller 0 3 hprir[15:12] hdlc controller 1 4 hprir[19:16] hdlc controller 2 5 hprir[23:20] x 0 1 31 [0] system bus arbitration method (arb) 0 = round-robin 1 = fixed priority syscfg note: see page 4-16 and 4-17. figure 4-4. ahb programmable priority registers S3C2500B system con figuration 4- 7 4.6.1 problem solvings with programmable round-robin S3C2500B has a stuff to think about with arbiter operation. this only applies to arbiter with round-robin priority. assuming all '0's are set for hprir register for round-robin, hprir (all same bus occupancy in round-robin), and only three of six masters are used, the problem arises as follows. number hprir channel expected bus occupancy actual running block real system bus occupancy 1 0 gdma 1/3 gdma 1/6 2 0 ethernet controller 0 1/3 ethernet controller 0 1/6 3 0 ethernet controller 1 1/3 ethernet controller 1 1/6 4 0 not used 0 gdma 1/6 5 0 not used 0 gdma 1/6 6 0 not used 0 gdma 1/6 when hprir is 0x0 and only gdma , ethernet controller 0 and 1 are used, the expected bus occupancy for each channel is 1/3. however, S3C2500B does not work in that way, instead, gdma gets 4/6 of the bus occupancy, ethernet controller 0 1/6, and ethernet controller 1 1/6. in short, gdma is run four times more than ethernet controller 0 and 1. this is because S3C2500B is designed to turn the bus occupancy to the next master when there is non-used master. for instance, number 1: gdma number 2: ethernet controller 0 number 3: ethernet controller 1 number 4: no hdlc 0 -> go to number 5: no hdlc 1 -> go to number 6: no hdlc 2 -> go to number 1: gdma number 5: no hdlc 1 -> go to number 6: no hdlc 2 -> go to number 1: gdma number 6: no hdlc 2 -> go to number 1: gdma system configuration S3C2500B 4- 8 the following is the problem solving with software. hprir channel expected bus occupancy real system bus occupancy hprir channel occupancy 0 gdma 1/3 4/6 0 gdma 1/3 0 ethernet controller 0 1/3 1/6 3 ethernet controller 0 1/3 0 ethernet controller 1 1/3 1/6 t 3 ethernet controller 1 1/3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 problem problem solving writing "0x000330", instead of "0x0" will give each channel of three masters with the same amount of bus occupancy. this is because gdma is run to fill the blank of non-used masters, (in this case, hdlc0, hdlc1, hdlc2) S3C2500B system con figuration 4- 9 4.7 clock configuration the S3C2500B has four pll clocking scheme ? cpu pll, system bus pll, usb pll, phy pll. all of the pll can operate if the corresponding clock select pin is set to ?0? (clksel- shared with cpu pll and system bus pll, usb_clksel, phy_clksel). when the clock select pin is set to ?1?, the pll goes into power down state. the cpu pll can generate arm940t clock or system bus clock depending on clock mode selection (clkmod[1:0]). the system bus pll generates system bus clock only. the usb pll generates usb clock. the phy pll generates clock for external devices. each pll clock output frequency can be programmed by either the pin setting or software setting. in pin configurable mode, the cpu_freq[2:0] pins determine the frequency of the cpu pll clock output and the bus_freq[2:0] pins determine the frequency of the system bus pll clock output. the usb pll always generates 4.8 times the input clock, i.e. if the 10mhz input clock is provided, the usb clock output is always 48 mhz. the phy_freq pin determines the frequency of the phy pll output. the phy pll generates 2 times the input clock if the phy_freq is ?0? and 2.5 times the input clock if the phy_freq is "1". the clkmod[1:0] pins determine the relation of the arm940t clock and the system clock. if the clkmod[1:0] is "00", the fastbus clock mode is defined. in this mode, the arm940t clock and the system bus clock is the same clock and the clock is from the cpu pll output. the two clocks are of the same phase and of the same frequency. if the clkmod[1:0] is ?11?, the async clock mode is defined. in this mode, the arm940t clock is out of the cpu pll and the system bus clock is out of the system bus pll. the frequency of the two clocks could be set to any frequency so long as the the frequency of the arm940t clock is faster than that of the system bus clock. the table 4-3 shows the clock configuration of the external pin setting. table 4-3. clock frequencies for clkmod pins, cpu_freq pins, and bus_freq pins clkmod [1:0] cpu_freq [2:0] bus_freq [2:0] arm940t clock frequency amba bus clock frequency usb clock frequency 2'b00 (fastbus) 3'b000 3'bxxx 166mhz 166mhz 48mhz 3'b001 3'bxxx 150mhz 150mhz 48mhz 3'b010 3'bxxx 133mhz 133mhz 48mhz 3'b011 3'bxxx 125mhz 125mhz 48mhz 3'b100 3'bxxx 100mhz 100mhz 48mhz 3'b101 3'bxxx 66mhz 166mhz 48mhz 3'b110 3'bxxx 50mhz 50mhz 48mhz 3'b111 3'bxxx 33mhz 33mhz 48mhz 2'b11 (async) 3'b000 3'b000 166mhz 133mhz 48mhz 3'b000 3'b001 166mhz 133mhz 48mhz 3'b000 3'b010 166mhz 133mhz 48mhz 3'b000 3'b011 166mhz 125mhz 48mhz 3'b000 3'b100 166mhz 100mhz 48mhz 3'b000 3'b101 166mhz 66mhz 48mhz 3'b000 3'b110 166mhz 50mhz 48mhz 3'b000 3'b111 166mhz 33mhz 48mhz not supported system configuration S3C2500B 4- 10 table 4-3. clock frequencies for clkmod pins, cpu_freq pins, and bus_freq pins (continued) clkmod [1:0] cpu_freq [2:0] bus_freq [2:0] arm940t clock frequency amba bus clock frequency usb clock frequency 2'b11 (async) 3'b001 3'b000 150mhz 133mhz 48mhz 3'b001 3'b001 150mhz 133mhz 48mhz 3'b001 3'b010 150mhz 133mhz 48mhz 3'b001 3'b011 150mhz 125mhz 48mhz 3'b001 3'b100 150mhz 100mhz 48mhz 3'b001 3'b101 150mhz 66mhz 48mhz 3'b001 3'b110 150mhz 50mhz 48mhz 3'b001 3'b111 150mhz 33mhz 48mhz 2'b11(async) 3'b010 3'b000 133mhz 133mhz 48mhz 3'b010 3'b001 133mhz 133mhz 48mhz 3'b010 3'b010 133mhz 133mhz 48mhz 3'b010 3'b011 133mhz 125mhz 48mhz 3'b010 3'b100 133mhz 100mhz 48mhz 3'b010 3'b101 133mhz 66mhz 48mhz 3'b010 3'b110 133mhz 50mhz 48mhz 3'b010 3'b111 133mhz 33mhz 48mhz 2'b11 (async) 3'b011 3'b000 125mhz 133mhz 48mhz 3'b011 3'b001 125mhz 133mhz 48mhz 3'b011 3'b010 125mhz 133mhz 48mhz 3'b011 3'b011 125mhz 125mhz 48mhz 3'b011 3'b100 125mhz 100mhz 48mhz 3'b011 3'b101 125mhz 66mhz 48mhz 3'b011 3'b110 125mhz 50mhz 48mhz 3'b011 3'b111 125mhz 33mhz 48mhz 2'b11 (async) 3'b100 3'b000 100mhz 133mhz 48mhz 3'b100 3'b001 100mhz 133mhz 48mhz 3'b100 3'b010 100mhz 133mhz 48mhz 3'b100 3'b011 100mhz 125mhz 48mhz 3'b100 3'b100 100mhz 100mhz 48mhz 3'b100 3'b101 100mhz 66mhz 48mhz 3'b100 3'b110 100mhz 50mhz 48mhz 3'b100 3'b111 100mhz 33mhz 48mhz not supported S3C2500B system con figuration 4- 11 table 4-3. clock frequencies for clkmod pins, cpu_freq pins, and bus_freq pins (continued) clkmod [1:0] cpu_freq [2:0] bus_freq [2:0] arm940t clock frequency amba bus clock frequency usb clock frequency 2'b11 (async) 3'b101 3'b000 66mhz 133mhz 48mhz 3'b101 3'b001 66mhz 133mhz 48mhz 3'b101 3'b010 66mhz 133mhz 48mhz 3'b101 3'b011 66mhz 125mhz 48mhz 3'b101 3'b100 66mhz 100mhz 48mhz 3'b101 3'b101 66mhz 66mhz 48mhz 3'b101 3'b110 66mhz 50mhz 48mhz 3'b101 3'b111 66mhz 33mhz 48mhz 2?b11 (async) 3'b110 3'b000 50mhz 133mhz 48mhz 3'b110 3'b001 50mhz 133mhz 48mhz 3'b110 3'b010 50mhz 133mhz 48mhz 3'b110 3'b011 50mhz 125mhz 48mhz 3'b110 3'b100 50mhz 100mhz 48mhz 3'b110 3'b101 50mhz 66mhz 48mhz 3'b110 3'b110 50mhz 50mhz 48mhz 3'b110 3'b111 50mhz 33mhz 48mhz not supported system configuration S3C2500B 4- 12 each pll can also be programmed by s/w register setting. each pll is in pin configurable mode after the system reset is released. you can change the pll configuration mode to the register configurable mode by set cpllren, spllren, upllren, ppllren in the syscfg[31:28]. if the pll register enable bit is set to "1, the pll multiplication factor is not from the external pin but from the corresponding pllcon regiseter- cpllcon, spllcon, upllcon, ppllcon registers. the pll is controlled by the 3 control variables, p, m ,s. when the pll is under the control of the s/w and the pll control variables are dynamically changed by the s/w, the glitch may occur in the pll output clock. you can avoid the glitch generation by set the pll clock enable bit, cpllce, spllce, upllce, ppllce in the syscfg [27:24]. when the pll clock enable bit is set to "0" during the pll control variable change, the stable pll output clock is provided. the pll output frequency is determined as follows. fout = fin (m+8) / ((p+2) (2^s)) where the fin is the frequency of the pll input clock and the fout is the frequency of the pll output clock. the four plls in the S3C2500B are controlled by above formula and the table 4-4 shows the pll variables for the most widely used frequencies. table 4-4. p, m, s values of the S3C2500B pll p[5:0] m[7:0] s[1:0] pll input clock frequency pll output clock frequency 00_0001 0101_0010 00 10mhz 300mhz 00_0001 0100_1000 00 10mhz 266mhz 00_0001 1000_0100 01 10mhz 233mhz 00_0001 0111_0000 01 10mhz 200mhz 00_0001 0101_1100 01 10mhz 166mhz 00_0001 0101_0010 01 10mhz 150mhz 00_0001 0100_1000 01 10mhz 133mhz 00_0001 0100_0011 01 10mhz 125mhz 00_0001 0111_0000 10 10mhz 100mhz 00_0001 0100_1000 10 10mhz 66mhz 00_0001 0111_0000 11 10mhz 50mhz 00_0011 1011_1000 11 10mhz 48mhz 00_0001 0100_1000 11 10mhz 33mhz S3C2500B system con figuration 4- 13 notes: 1. cpu pll block can generate eight clock frequencies between 166mhz and 33mhz according to the cpu_freq[2:0] pins out of the 10mhz xclk input clock frequency. 2. usb pll block can generate only 48mhz clock frequency out of the 10mhz usb_xclk input clock frequency. 3. if clksel, or usb_clksel is 1, the cpu pll, bus pll, or usb pll go into the state of power down. 4. three pins of cpu_freq[2:0] can control the multiplication factor of the cpu pll block. 5. the phy_freq pin controls the frequency of the phy pll. 6. the system configuration register clkcon[15:0] can divide the arm9 clock and the system clock. if all bits are 0, non-divided clock is used.only one bit can be set in clkcon[15:0]. that is, the clock dividing value is defined as 1, 2, 4, 8, 16, .... the internal clock is (pll output clock between 166mhz and 33mhz) / (clkcon+1). 7. the clkcon[15:0] register, clkmod[1:0] pins and cpu_freq[2:0] pins can control the amba clock divider. the clkmod[1:0] pins and bus_freq[2:0] pins can generate the various amba bus clock frequecies referring to the table 3. the clkcon[15:0] register can divide the various amba clock frequecies of the table 4-3. 8. all pll can be controlled by either pin setting or register setting. {clkcon[15:0], clkmod[1:0], bus_freq[2:0]} cpu pll 166-33 mhz 0 1 arm940t block arm clock divider cpu_freq[2:0] or cpllcon pdown clksel xclk clkcon[15:0] bus pll system block amba clock divider bus_freq[2:0] or spllcon pdown clksel xclk 0 1 0 1 pll_test pll clock divider hclko pin pll_test & pp[1:0] clkmod[0] usb pll 0 1 usb block usb clock divider upllcon pdown usb_clksel usb_sclk phy pll 20/25 mhz 0 1 phy_freq or ppllcon pdown phy_clksel xclk 48mhz phy_clko 48mhz 48mhz 133-33 mhz figure 4-5. shows the clock generation logic of the S3C2500B system configuration S3C2500B 4- 14 4.8 external bus master the s3c2500 allows the external bus master to get the external memory bus and control the external memory system. when the external bus master asserts xbmreq to get the external memory bus, the s3c2500 asserts xmback high and drives the state of the external memory bus to high impedance after s3c2500 finishes current transfer with memory. when the external bus master takes the control of external memory bus, it should take care of sdram refresh operation. s3c2500 can get the control of the memory bus 1 cycle after xbmreq is deactivated. pxbmreq hclk pxbmack figure 4-6. external master request timing S3C2500B system con figuration 4- 15 4.9 system configuration special registers the system configuration reigisters are as follows table 4-5. s ystem c onfiguration r egisters name address description reset value syscfg 0xf0000000 system configuration register ? pdcode 0xf0000004 product code and revision number register 0x250000a0 clkcon 0xf0000008 system clock control register 0x00000000 pclkdis 0xf000000c peripheral clock disable register 0x00000000 clkst 0xf0000010 clock status register hprif 0xf0000014 ahb bus master fixed priority register 0x00543210 hprir 0xf0000018 ahb bus master round-robin priority register 0x00000000 cpllcon 0xf000001c core pll configuration register 0x0001039e spllcon 0xf0000020 system bus pll configuration register 0x00010370 upllcon 0xf0000024 usb pll configuration register 0x00010328 ppllcon 0xf0000028 phy pll configuration register 0x000103111 system configuration S3C2500B 4- 16 4.9.1 system configuration register (syscfg) you can control the system bus arbitration method, pll operation, system clock output enable/disable function, external memory address remap function and little/big information read function by syscfg. register address r/w description reset value syscfg 0xf0000000 r/w system configuration register ? syscfg bit description initial state cpllren [31] cpllcon register enable this bit controls which value is used for the cpu pll constant from the two constant values. when this bit is set to ?0?, the cpu pll constant is from cpu_freq[2:0] setting. when this bit is set to ?1?, the cpu pll constant is from the cpllcon register. 0 spllren [30] spllcon register enable this bit controls which value is used for the bus pll constant from the two constant values. when this bit is set to ?0?, the bus pll constant is from bus_freq[2:0] setting. when this bit is set to ?1?, the bus pll constant is from the spllcon register. 0 upllren [29] upllcon register enable this bit controls which value is used for the usb pll constant from the two constant values. when this bit is set to ?0?, the bus pll constant is always set to generates the clock frequency 4.8 times the input clock. when this bit is set to ?1?, the usb pll constant is from the upllcon register. 0 ppllren [28] ppllcon register enable this bit controls which value is used for the phy pll constant from the two constant values. when this bit is set to ?0?, the phy pll constant is from phy_freq setting. when this bit is set to ?1?, the phy pll constant is from the ppllcon register. 0 cpllfd [27] cpll filter disable this bit determines whether the cpu pll output is filtered or not during the configuration. when this bit is set to ?0?, the cpu pll output is filtered to be provided to the system during the configuration. in this case, the glitch output from pll can be masked. when this bit is set to ?1?, the cpu pll output is not filtered to be provided to the system. 0 spllfd [26] spll filter disable this bit determines whether the bus pll output is filtered or not during the configuration. when this bit is set to ?0?, the bus pll output is filtered to be provided to the system during the configuration. in this case, the glitch output from pll can be masked. when this bit is set to ?1?, the bus pll output is not filtered to be provided to the system. 0 S3C2500B system con figuration 4- 17 syscfg bit description initial state upllfd [25] upll filter disable this bit determines whether the usb pll output is filtered or not during the configuration. when this bit is set to ?0?, the usb pll output is filtered to be provided to the usb during the configuration. in this case, the glitch output from pll can be masked. when this bit is set to ?1?, the usb pll output is not filtered to be provided to the usb. 0 ppllfd [24] ppll filter disable this bit determines whether the phy pll output is filtered or not during the configuration. when this bit is set to ?0?, the phy pll output is filtered to be provided to the phy during the configuration. in this case, the glitch output from pll can be masked. when this bit is set to ?1?, the phy pll output is not filtered to be provided to the phy. 0 big [16] little / big endian information (read only) 0 = little endian 1 = big endian ? remap [8] external memory address remapping enable 0 = remap disable 1 = remap enable rom bank0 : 0x00000000 rom bank0 : 0x80000000 rom bank1 : 0x01000000 rom bank1 : 0x81000000 rom bank2 : 0x02000000 rom bank2 : 0x82000000 rom bank3 : 0x03000000 rom bank3 : 0x83000000 rom bank4 : 0x04000000 rom bank4 : 0x84000000 rom bank5 : 0x05000000 rom bank5 : 0x85000000 rom bank6 : 0x06000000 rom bank6 : 0x86000000 rom bank7 : 0x07000000 rom bank7 : 0x87000000 sdram bank0 : 0x40000000 sdram0 bank0 : 0x00000000 sdram bank1 : 0x80000000 sdram1 bank1 : 0x40000000 0 misalign [7] misalign exception enable S3C2500B asserts the data abort exception in case of cpu misaligned accesses. but there is a limitation to that you should set off instruction/data cache when you want misaligned access aborts. 0 hclko_dis [4] hclko output disable if this bit is set to ?1?, hclko output is activated only when sdram access - sdram read/write or refresh - is enabled. if this bit is set to ?0?, hclko is always activated. 0 = enabled always 1 = enabled during sdram access. 0 arb [0] system bus arbitration method 0 = round-robin 1 = fixed priority 0 system configuration S3C2500B 4- 18 4.9.2 product code and revision number register (pdcode) register address r/w description reset value pdcode 0xf0000004 r product code and revision number register 0x250000b0 pdcode bit description initial state pc [31-16] product code 0x2500 reserved [15:8] reserved 0x0 majrev [7:4] major revision number 0xb minrev [3:0] minor revision number 0x0 S3C2500B system con figuration 4- 19 4.9.3 clock control register (clkcon) there is a clock control register(clkcon) in system configuration. for the purpose of power save, clock control register(clkcon) can be programmed at low frequency and the slower clock than the system clock can be made by clock dividing value . when the internal system clock is divided by clkcon, its duty-cycle is changed. if clkcon is programmed to zero, the internal system clock remains the same as the internal clock. in other case, the duty cycle of internal system clock is no logner 50%. register address r/w description reset value clkcon 0xf0000008 r/w clock control register 0x00000000 clkcon bit description initial state reserved [31:16] reserved 0 dval [15:0] system clock dividing value. if all bits are 0, non-divided clock is used. only one bit can be set in clkcon[15:0]. that is, the clock dividing value is defined as 1, 2, 4, 8, 16, ? internal system clock is (pll output clock) / (clkcon+1). 0 hclk hclk clkcon = 0 hclk clkcon = 1 hclk clkcon = 2 figure 4-7. divided system clock timing diagram system configuration S3C2500B 4- 20 4.9.4 peripheral clock disable register (pclkdis) there is a peripheral clock disable register in system configuration. you can set this register with the specific value for the purpose of power save. if you set pclkdis[0] to ?1?, the clock for gdma channel 0 is disabled. similarly, you control the clock input of each peripheral. register address r/w description reset value pclkdis 0xf000000c r/w peripheral clock disable register 0x00000000 pclkdis bit description initial state srreq [31] sdram self-refresh request 0x0 srack [30] sdram self-refresh acknowledge ( read only) 0x0 reserved [29:28] reserved for future use 0x0 iom2 [27] iom2 clock disable 0x0 hdlc2 [26] hdlc2 clock disable 0x0 hdlc1 [25] hdlc1 clock disable 0x0 hdlc0 [24] hdlc0 clock disable 0x0 sdramc [23] sdramc clock disable 0x0 memcon [22] memcon clock disable 0x0 des [21] des clock disable 0x0 iic [20] iic clock disable 0x0 iopc [19] iopc clock disable 0x0 wdt [18] watch dog timer clock disable 0x0 timer5 [17] timer5 clock disable 0x0 timer4 [16] timer4 clock disable 0x0 timer3 [15] timer3 clock disable 0x0 timer2 [14] timer2 clock disable 0x0 timer1 [13] timer1 clock disable 0x0 timer0 [12] timer0 clock disable 0x0 huart1 [11] huart clock disable 0x0 huart0 [10] huart clock disable 0x0 cuart [9] cuart clock disable 0x0 usb [8] usb clock disable 0x0 etherc1 [7] etherc1 clock disable 0x0 etherc0 [6] etherc0 clock disable 0x0 gdma5 [5] gdma channel 5 clock disable 0x0 gdma4 [4] gdma channel 4 clock disable 0x0 gdma3 [3] gdma channel 3 clock disable 0x0 gdma2 [2] gdma channel 2 clock disable 0x0 gdma1 [1] gdma channel 1 clock disable 0x0 gdma0 [0] gdma channel 0 clock disable 0x0 S3C2500B system con figuration 4- 21 4.9.5 clock status register (clkst) the operating frequency of the S3C2500B can be obtained by reading the clkst register. the cpu freq field in clkst[11:0] decodes the cpu_freq[2:0] settings and the bus freq in clkst[23:12] decodes the bus_freq[2:0] settings. there are 3 clock modes in the S3C2500B - fast mode, sync mode and async mode. in async mode, there is no misinformation about the frequency. but care must be taken for the fastbus mode and sync mode. in the fastbus mode, the bus frequency in the clkst[23:12] should be ignored and the cpu frequency in the clkst[11:0] should be taken for the bus frequency because the cpu clock and system bus clock is the same. in the sync mode, the bus frequency in the clkst[23:12] should also be ignored , and the half of the cpu frequency should be taken for the bus frequency. register address r/w description reset value clkst 0xf0000010 r clock status register (read only) ? clkst bit description initial state clock mode [31:30] 00 = fastbus mode 01 = reserved 10 = reserved 11 = asynchronous reserved [29:24] bus freq [23:12] system bus clock frequency cpu freq [11:0] cpu clock frequency 4.9.6 ahb bus master priority register register address r/w description reset value hprif 0xf0000014 r/w ahb bus master fixed priority register 0x00543210 hprir 0xf0000018 r/w ahb bus master round-robin priority register 0x00000000 system configuration S3C2500B 4- 22 4.9.7 core pll control register (cpllcon) if you want to use this register, you should set cpllren in syscfg[31] to ?1?. this register doesn?t work with cpllren set to ?0?. register address r/w description reset value cpllcon 0xf000001c r/w core pll control register 0x0001039e cpllcon bit description initial state reserved [31:12] 0x0 s [17:16] scaler 0x1 reserved [15:14] 0x0 p [13:8] pre divider 0x3 m [7:0] main divider 0x9e output clock frequency is determined by following formula. fout = fin (m+8) / ((p+2) (2^s)) if fin = 10mhz, p = 3, m = 158 (0x9e), and s = 1, fout is 166 mhz. fclk signal of arm940t core is connected to fout, 166mhz clock. but, bclk signal of arm940t and system bus clock is connect to fout / 2, 66 mhz clock. S3C2500B system con figuration 4- 23 4.9.8 system bus pll control register (spllcon) if you want to use this register, you should set spllren in syscfg[30] to ?1?. this register doesn?t work with spllren set to ?0?. register address r/w description reset value spllcon 0xf0000020 r/w system bus pll control register 0x0001037d spllcon bit description initial state reserved [31:12] 0x0 s [17:16] scaler 0x1 reserved [15:14] 0x0 p [13:8] pre divider 0x3 m [7:0] main divider 0x7d output clock frequency is determined by following formula. fout = fi n (m+8) / ((p+2) (2^s)) if fin = 10mhz, p = 3, m = 125 (0x7d), and s = 1, fout is 133 mhz. fclk signal of arm940t core is connected to fout, 133mhz clock. but, bclk signal of arm940t and system bus clock is connect to fout / 2, 66 mhz clock. system configuration S3C2500B 4- 24 4.9.9 usb pll control register (upllcon) if you want to use this register, you should set upllren in syscfg[29] to ?1?. this register doesn?t work with upllren set to ?0?. register address r/w description reset value upllcon 0xf0000024 r/w usb pll control register 0x00010328 upllcon bit description initial state reserved [31:12] 0x0 s [17:16] scaler 0x1 reserved [15:14] 0x0 p [13:8] pre divider 0x3 m [7:0] main divider 0x28 output clock frequency is determined by following formula. fout = fin (m+8) / ((p+2) (2^s)) if fin = 10mhz, p = 3, m = 40 (0x28), and s = 1, fout is 48mhz. 4.9.10 phy pll control register (ppllcon) if you want to use this register, you should set ppllren in syscfg[28] to ?1?. this register doesn?t work with ppllren set to ?0?. register address r/w description reset value ppllcon 0xf0000028 r/w phy pll control register 0x00010311 ppllcon bit description initial state reserved [31:12] 0x0 s [17:16] scaler 0x1 reserved [15:14] 0x0 p [13:8] pre divider 0x3 m [7:0] main divider 0x11 note : some switches may cause a link failure when s3c2500?s phy source clock, phy_clko, is used. output clock frequency is determined by following formula. fout = fin (m+8) / ((p+2) * (2^s)) if fin = 10mhz, p = 3, m = 17 (0x11), and s = 1, fout is 25mhz. S3C2500B memory controller 5- 1 5 memory controller 5.1 overview this memory controller consists of ext i/o bank controller and sdram controller. ext i/o bank controller supports rom, sram and flash memory. sdram controller support sdram. the S3C2500B memory controller has the following functions. to provide the required memory control signals for external memory accesses. for example, if a master block such as dma controller or cpu generates an address that corresponds to a sdram bank, the sdram controller generates the required sdram access signals. to provide the required signals for bus traffic between the S3C2500B and rom/sram and the external i/o banks. to compensate for differences in bus width for data flowing between the external memory bus and the internal data bus. S3C2500B supports both little and big endians for external memory or i/o devices. memory controller s 3c2500b 5- 2 5.2 features the following is a list of the memory controller?s features: 10 banks (8 banks for rom / sram / flash memory / external i/o interface, 2 banks for sdram interface ) 16m-byte maximum address range per bank (24 bit external address pins) 32 bit internal and external data bus various timing control options note by generating an external bus request, an external device can access the S3C2500B's external memory interface pins. in addition, the S3C2500B can access slow external devices by using a wait signal. the wait signal, which is generated by the external device, extends the duration of the cpu?s memory access cycle beyond its programmable value. S3C2500B memory controller 5- 3 5.3 memory map after a power-on or system reset, all bank address pointer registers are initialized to their default values. and the base address of all banks are fixed. the initial system memory map following system start-up is shown in figure 5-1. table 5-1. base address of each bank bank base address ext i/o bank 0 0x00000000 ext i/o bank 1 0x01000000 ext i/o bank 2 0x02000000 ext i/o bank 3 0x03000000 ext i/o bank 4 0x04000000 ext i/o bank 5 0x05000000 ext i/o bank 6 0x06000000 ext i/o bank 7 0x07000000 sdram bank 0 0x40000000 sdram bank 1 0x80000000 memory controller s 3c2500b 5- 4 0xffffffff 0xf0000000 0x88000000 0x80000000 0x40000000 0x08000000 0x07000000 0x06000000 0x05000000 0x04000000 0x03000000 0x02000000 0x01000000 0x00000000 reserved internal register bank 1 reserved reserved ext i/o bank 7 ext i/o bank 6 ext i/o bank 5 ext i/o bank 4 ext i/o bank 3 ext i/o bank 1 ext i/o bank 2 ext i/o bank 0 notes: 1. rom, sram, flash and external i/o bank have the same operation in internal logic. therefore you may connect a sram or a flash memory with a external i/o bank. 2. each ext i/o bank address is fixed with maximum address range. s3c2500 has 24 address pins, which restrict to 16m-byte address. 3. each sdram bank supports up to 128m-byte in size. bank 0 0x48000000 figure 5-1. memory bank address map S3C2500B memory controller 5- 5 5.4 bus interface signals the bus interface signals transfer information between the S3C2500B and external memory device. these divide into address and data which used commonly, sdram interface signals for sdram and memory device interface for rom/sram, etc. for detail description for the bus interface signals, refer to the table below. table 5-2. bus interface signals signal name pins active i/o description addr 24 high o specifies the physical address of the external device data 32 high b specifies data of the external device b0size 2 high i specifies data bus access size for the bank 0 noe 1 low o specifies read/write state from S3C2500B. when S3C2500B read from ext i/o device, noe?s value is 1?b0. nrcs 8 low o specifies which ext i/o device is selected. newait/nready 1 low i signal be controlled from ext i/o slow device to delay cycles in data read and write. hclko 1 high o S3C2500B system clock out cke 1 high o clock enable for sdram nsdcs 2 low o chip select strobe for sdram nsdras 1 low o row address strobe for sdram nsdcas 1 low o column address strobe for sdram nwbe/nbe/dqm 4 low o write byte enable nsdwe/nwe16 1 low o write enable for rom, sram, flash that have 16bit- data width and sdram. xbmreq 1 high i external master bus request xbmack 1 high o external bus acknowledge notes: 1. o = output from the S3C2500B. 2. i = input to the S3C2500B. 3. b = bi-direction. memory controller s 3c2500b 5- 6 address & data rom & sram interface signals sdram interface signals rom, sram, flash and sdram common signals external device interface signals adjust with pin selection noe nrcs[7:0] addr[23:0] hclko cke nsdcs[1:0] nsdras nsdcas nwbe/nbe/dqm[3:0] newait/nready nsdwe/nwe16 b0size[1:0] xbmreq data[31:0] xbmack S3C2500B figure 5-2. memory controller bus signals S3C2500B memory controller 5- 7 5.5 endian modes S3C2500B supports both little-endian and big-endian for external memory or i/o devices by setting the pin big. below tables(5-3 through 5-14) are show the program/data path between the cpu register and the external memory using little-/big-endian and word/half-word/byte access. table 5-3 and 5-4. using big-endian and word access, program/data path between register and external memory. wa=address whose lsb is 0, 4, 8, c, ha=address whose lsb is 0, 2, 4, 6, 8, a, c, e ba=address whose lsb is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f ea=external address x=don't care table 5-3. external 32-bit datawidth store operation with big-endian transfer width store (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxab 31 0 xxcd 31 0 xxxa 31 0 xxxb 31 0 xxxc 31 0 xxxd cpu address wa ha ha+1 ba ba+1 ba+2 ba+3 bit num. cpu data bus 31 0 abcd 31 0 abab 31 0 cdcd 31 0 aaaa 31 0 bbbb 31 0 cccc 31 0 dddd external address (addr) ea bit num. external data 31 0 dcba 31 0 xxba 31 0 dcxx 31 0 xxxa 31 0 xxbx 31 0 xcxx 31 0 dxxx timing sequence table 5-4. external 32-bit datawidth load operation with big-endian transfer width load (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxab 31 0 xxcd 31 0 xxxa 31 0 xxxb 31 0 xxxc 31 0 xxxd cpu address wa ha ha+1 ba ba+1 ba+2 ba+3 bit num. cpu data bus 31 0 abcd 31 0 abab 31 0 cdcd 31 0 aaaa 31 0 bbbb 31 0 cccc 31 0 dddd external address (addr) ea bit num. external data 31 0 dcba 31 0 dcba 31 0 dcba timing sequence memory controller s 3c2500b 5- 8 table 5-5 and 5-6. using big-endian and half-word access, program/data path between register and external memory. wa=address whose lsb is 0, 4, 8, c, ea=external address ha=address whose lsb is 0, 2, 4, 6, 8, a, c, e ba=address whose lsb is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f x=don't care. table 5-5. external 16-bit datawidth store operation with big-endian transfer width store (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxab 31 0 xxxa 31 0 xxxb cpu address wa ha ba ba+1 bit num. cpu data bus 31 0 abcd 31 0 abab 31 0 aaaa 31 0 bbbb external address (addr) ea ea+1 ea ea bit num. external data 15 0 ba 15 0 dc 15 0 ba 15 0 xa 15 0 bx timing sequence 1st 2nd table 5-6. external 16-bit datawidth load operation with big-endian transfer width load (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxab 31 0 xxxa 31 0 xxxb cpu address wa ha ba ba+1 bit num. cpu data bus 31 0 abxx 31 0 abcd 31 0 abab 31 0 aaaa 31 0 bbbb external address (addr) ea ea + 1 ea ea bit num. external data 15 0 ba 15 0 dc 15 0 ba 15 0 ba timing sequence 1st 2nd S3C2500B memory controller 5- 9 table 5-7 and 5-8. using big-endian and byte access, program/data path between register and external memory. wa=address whose lsb is 0, 4, 8, c, ea=external address ha=address whose lsb is 0, 2, 4, 6, 8, a, c, e ba=address whose lsb is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f x=don't care. table 5-7. external 8-bit datawidth store operation with big-endian transfer width store (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 15 0 xxab 7 0 xxxa cpu address wa ha ba bit num. cpu data bus 31 0 abcd 31 0 abab 31 0 aaaa external address ea ea+1 ea+2 ea+3 ea ea+1 ea bit num. external data 7 0 a 7 0 b 7 0 c 7 0 d 7 0 a 7 0 b 7 0 a timing sequence 1st 2nd 3rd 4th 1st 2nd table 5-8. external 8-bit datawidth load operation with big-endian transfer width load (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 15 0 xxab 7 0 xxxa cpu address wa ha ba bit num. cpu data bus 31 0 axxxx 31 0 abxx 31 0 abcx 31 0 abcd 31 0 axax 31 0 abab 31 0 aaaa external address ea ea+1 ea+2 ea+3 ea ea+1 ea bit num. external data 7 0 a 7 0 b 7 0 c 7 0 d 7 0 a 7 0 b 7 0 a timing sequence 1st 2nd 3rd 4th 1st 2nd memory controller s 3c2500b 5- 10 table 5-9 and 5-10. using little-endian and word access, program/data path between register and external memory. wa=address whose lsb is 0, 4, 8, c, ea=external address ha=address whose lsb is 0, 2, 4, 6, 8, a, c, e ba=address whose lsb is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f x=don't care table 5-9. external 32-bit datawidth store operation with little-endian transfer width store (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxcd 31 0 xxab 31 0 xxxd 31 0 xxxc 31 0 xxxb 31 0 xxxa cpu address wa ha ha+1 ba ba+1 ba+2 ba+3 bit num. cpu data bus 31 0 abcd 31 0 cdcd 31 0 abab 31 0 dddd 31 0 cccc 31 0 bbbb 31 0 aaaa external address (addr) ea bit num. external data 31 0 abcd 31 0 xxcd 31 0 abxx 31 0 xxxd 31 0 xxcx 31 0 xbxx 31 0 axxx timing sequence table 5-10. external 32-bit datawidth load operation with little-endian transfer width load (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxcd 31 0 xxab 31 0 xxxd 31 0 xxxc 31 0 xxxb 31 0 xxxa cpu address wa ha ha+1 ba ba+1 ba+2 ba+3 bit num. cpu data bus 31 0 abcd 31 0 cdcd 31 0 abab 31 0 dddd 31 0 cccc 31 0 bbbb 31 0 aaaa external address (addr) ea bit num. external data 31 0 abcd 31 0 abcd 31 0 abcd timing sequence S3C2500B memory controller 5- 11 table 5-11 and 5-12. using little-endian and half-word access, program/data path between register and external memory. wa=address whose lsb is 0, 4, 8, c, ea=external address ha=address whose lsb is 0, 2, 4, 6, 8, a, c, e ba=address whose lsb is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f x=don't care. table 5-11. external 16-bit datawidth store operation with little-endian transfer width store (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxab 31 0 xxxb 31 0 xxxa cpu address wa ha ba ba+1 bit num. cpu data bus 31 0 abcd 31 0 abab 31 0 bbbb 31 0 aaaa external address (addr) ea+1 ea ea ea bit num. external data 15 0 ab 15 0 cd 15 0 ab 15 0 xb 15 0 ax timing sequence 1st 2nd table 5-12. external 16-bit datawidth load operation with little-endian transfer width load (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxab 31 0 xxxb 31 0 xxxa cpu address wa ha ba ba+1 bit num. cpu data bus 31 0 abxx 31 0 abcd 31 0 abab 31 0 bbbb 31 0 aaaa external address (addr) ea + 1 ea ea ea bit num. external data 15 0 ab 15 0 cd 15 0 ab 15 0 ab timing sequence 1st 2nd memory controller s 3c2500b 5- 12 table 5-13 and 5-14. using little-endian and byte access, program/data path between register and external memory. wa=address whose lsb is 0, 4, 8, c, ea=external address ha=address whose lsb is 0, 2, 4, 6, 8, a, c, e ba=address whose lsb is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f x=don't care. table 5-13. external 8-bit datawidth store operation with little-endian transfer width store (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxab 31 0 xxxa cpu address wa ha ba bit num. cpu data bus 31 0 abcd 31 0 abab 31 0 aaaa external address (addr) ea+3 ea+2 ea+1 ea ea+1 ea ea bit num. external data 7 0 a 7 0 b 7 0 c 7 0 d 7 0 a 7 0 b 7 0 a timing sequence 1st 2nd 3rd 4th 1st 2nd table 5-14. external 8-bit datawidth load operation with little-endian transfer width load (cpu reg ? ? external memory) 32-bit 16-bit 8-bit bit num. cpu register data 31 0 abcd 31 0 xxab 31 0 xxxa cpu address wa ha ba bit num. cpu data bus 31 0 axxxx 31 0 abxx 31 0 abcx 31 0 abcd 31 0 axax 31 0 abab 31 0 aaaa external address (addr) ea+3 ea+2 ea+1 ea ea+1 ea ea bit num. external data 7 0 a 7 0 b 7 0 c 7 0 d 7 0 a 7 0 b 7 0 a timing sequence 1st 2nd 3rd 4th 1st 2nd S3C2500B memory controller 5- 13 5.6 ext i/o bank controller ext i/o bank controller can be interfaceing rom, sram, flash memory, etc, except sdram. it also supports muxed bus memory device which shares address bus and data bus. ext i/o bank controller has three kind of the register for eight banks and then it can be controlled by various timing control options. 5.6.1 features the following is a list of the ext i/o bank controller?s features: 8 banks rom / sram / flash memory / external i/o interface 16m-byte maximum address range per bank (24-bit external address pins) 32-bit internal and external data bus various timing control options memory controller s 3c2500b 5- 14 5.6.2 external device connection figure 5-3. illustrates a simple connection between 8-bit rom/flash and S3C2500B. addr data noe ncs nwe 8-bit rom/ flash noe nrcs[0] addr[23:0] data[7:0] nwbe[0] S3C2500B figure 5-3. 8-bit rom, sram and flash basic connection S3C2500B memory controller 5- 15 figure 5-4. illustrates a example connection between two of 8-bit rom/flash and S3C2500B for the consisting of 16-bit rom/sram/flash. noe nrcs[0] nwbe[0] nwbe[1] addr[23:0] data[7:0] data[15:8] addr[23:0] data[7:0] noe ncs nwe 8-bit rom/flash addr[23:0] data[7:0] noe ncs nwe 8-bit rom/flash S3C2500B figure 5-4. 8-bit rom, sram and flash basic connection (8-bit memory x 2) memory controller s 3c2500b 5- 16 figure 5-5. illustrates a connection between 16-bit rom/sram and S3C2500B. addr data noe ncs upper byte lower byte 16-bit sram nwe noe nrcs nbe[0] addr[23:0] data[15:0] nbe[1] nsdwe/nwe16 S3C2500B figure 5-5. 16-bit sram basic connection S3C2500B memory controller 5- 17 figure 5-6. illustrates a connection between 16-bit rom/flash and S3C2500B. addr data noe nwe 16-bit rom/flash ncs noe nsdwe/nwe16 addr[23:0] data[15:0] nrcs S3C2500B figure 5-6. 16-bit rom and flash basic connection memory controller s 3c2500b 5- 18 figure 5-7. illustrates a connection between 16-bit rom and S3C2500B. noe nrcs addr[23:0] data[31:0] data[15:0] data[31:16] S3C2500B addr data noe ncs nwe 16-bit rom addr data noe ncs nwe 16-bit rom nsdwe/nwe16 figure 5-7. 16-bit rom basic connection 2 S3C2500B memory controller 5- 19 figure 5-8. illustrates a connection between 16-bit sram and S3C2500B. noe nrcs addr[23:0] data[31:0] nwbe[1] data[15:0] data[31:16] nwbe[0] addr data noe ncs upper byte 16-bit rom lower byte addr data noe ncs upper byte 16-bit rom lower byte nwbe[3] nwbe[2] S3C2500B figure 5-8. 16-bit sram basic connection 2 memory controller s 3c2500b 5- 20 figure 5-9. illustrates a connection between S3C2500B and muxed bus rom & sram. ale data[7:0] noe ncs nwbe nready S3C2500B noe nrcs addr[23]/ale data[7:0] nwbe nready figure 5-9. rom & sram with muxed address & data bus connection note if the external i/o use nready signal insteady of nwait, you must select nready in waitcon register of memory controller. addr[23] bit is used the address latch enable(ale) signal to latch an address for the rom and sram which have the muxed bus structure. S3C2500B memory controller 5- 21 5.6.3 ext. i/o bank controller special register to control the external memory operations, the memory controller uses a dedicated set of special registers (see table 5-15). by programming the values in the memory controller special registers, you can specify such things as memory type external bus width selection control signal timing ext i/o access cycles control the sizes of memory banks to be used for arbitrary address spacing the memory controller uses some special registers to control the generation and processing of the control signals, addresses, and data that are required by the external devices in a standard system configuration. the special registers are also used to control access to all banks. table 5-15. ext. i/o bank controller special registers name address description reset value b0con 0xf0010000 bank 0 control register 0xc514e488 (b0size=3) 0x8514e488 (b0size=2) 0x4514e488 (b0size=1) b1con 0xf0010004 bank 1 control register 0xc514e488 b2con 0xf0010008 bank 2 control register 0xc514e488 b3con 0xf001000c bank 3 control register 0xc514e488 b4con 0xf0010010 bank 4 control register 0xc514e488 b5con 0xf0010014 bank 5 control register 0xc514e488 b6con 0xf0010018 bank 6 control register 0xc514e488 b7con 0xf001001c bank 7 control register 0xc514e488 muxbcon 0xf0010020 muxed bus control register 0x006db6db waitcon 0xf0010024 wait control register 0x00000000 note: b0size means the size of physical data bus width in bank 0. refer to the next page. memory controller s 3c2500b 5- 22 5.6.3.1 ext i/o bank access control registers (bncon) the ext i/o bank controller has eight external i/o access control registers. these registers correspond to up to eight external i/o banks that are supported by S3C2500B. table 5-16 describes eight registers that are used to control the timing of external i/o bank accesses. the external i/o access cycles can be controlled by using either a specified value or an external wait signal, newait. especially, to obtain access cycles that are longer than tacc of 31 cycles, you can delay the active time of noe or nwbe by newait assertion. in case of rom bank, noe/nwbe signals are activated simultaneously; that is, there is no control parameter as like tcos. address setup time(tacs) can be used when the external memory access is handled by the noe assertion to be delayed. thus the external memory may use more stable address. access cycles(tacc) extend ncs cycles to access external memory. after noe is deasserted, chip selection hold time(tcoh) can be used when ncs is keep up. b0con is used to set the external access timings for external i/o bank 0. b1con is used to set the external access timing for i/o bank 1, and so on. bncon bank number figure 5-10. bncon the ext i/o bank controller has eight kind control registers for rom, sram, and flash memory (see table 5-16). these registers correspond to up to eight rom/sram/flash banks that are supported by S3C2500B. for rom/sram/flash bank 0, the external data bus width is determined by the signal at the b0size pins: when b0size[1:0] = "01", the external bus width for rom/sram/flash bank 0 is 8 bits. when b0size[1:0] = "10", the external bus width for rom/sram/flash bank 0 is 16 bits. when b0size[1:0] = "11", the external bus width for rom/sram/flash bank 0 is 32 bits. bncon register configuration is described in figure 5-11. S3C2500B memory controller 5- 23 table 5-16. bank n control (bncon) register register address r/w description reset value b0con 0xf0010000 r/w bank 0 control register 0xc514e488 (b0size=3) 0x8514e488 (b0size=2) 0x4514e488 (b0size=1) b1con 0xf0010004 r/w bank 1 control register 0xc514e488 b2con 0xf0010008 r/w bank 2 control register 0xc514e488 b3con 0xf001000c r/w bank 3 control register 0xc514e488 b4con 0xf0010010 r/w bank 4 control register 0xc514e488 b5con 0xf0010014 r/w bank 5 control register 0xc514e488 b6con 0xf0010018 r/w bank 6 control register 0xc514e488 b7con 0xf001001c r/w bank 7 control register 0xc514e488 memory controller s 3c2500b 5- 24 [3:0] chip selection hold time on noe: tcoh 0000 = 0 cycle 0001 = 1 cycle 0010 = 2 cycles 0011 = 3 cycles 0100 = 4 cycles 0101 = 5 cycles 0110 = 6 cycles 0111 = 7 cycles 1000 = 8 cycles 1001 = 9 cycles 1010 = 10 cycles 1011 = 11 cycles 1100 = 12 cycles 1101 = 13 cycles 1110 = 14 cycles 1111 = 15 cycles [7:4] chip selection setup time on noe: tcos 0000 = 0 cycle 0001 = 1 cycle 0010 = 2 cycles 0011 = 3 cycles 0100 = 4 cycles 0101 = 5 cycles 0110 = 6 cycles 0111 = 7 cycles 1000 = 8 cycles 1001 = 9 cycles 1010 = 10 cycles 1011 = 11 cycles 1100 = 12 cycles 1101 = 13 cycles 1110 = 14 cycles 1111 = 15 cycles [11:8] address setup time: tacs 0000 = 0 cycle 0001 = 1 cycle 0010 = 2 cycles 0011 = 3 cycles 0100 = 4 cycles 0101 = 5 cycles 0110 = 6 cycles 0111 = 7 cycles 1000 = 8 cycles 1001 = 9 cycles 1010 = 10 cycles 1011 = 11 cycles 1100 = 12 cycles 1101 = 13 cycles 1110 = 14 cycles 1111 = 15 cycles [15:12] page address access cycle: tpa 0000 = 0 cycle 0001 = 1 cycle 0010 = 2 cycles 0011 = 3 cycles 0100 = 4 cycles 0101 = 5 cycles 0110 = 6 cycles 0111 = 7 cycles 1000 = 8 cycles 1001 = 9 cycles 1010 = 10 cycles 1011 = 11 cycles 1100 = 12 cycles 1101 = 13 cycles 1110 = 14 cycles 1111 = 15 cycles [20:16] access cycles(noe low time): tacc 00000 = reserved 00001 = reserved 00010 = reserved 00011 = 3 cycles 00100 = 4 cycles 00101 = 5 cycles 00110 = 6 cycles 00111 = 7 cycles 01000 = 8 cycles 01001 = 9 cycles 01010 = 10 cycles 01011 = 11 cycles 01100 = 12 cycles 01101 = 13 cycles 01110 = 14 cycles 01111 = 15 cycles 10000 = 16 cycles 10001 = 17 cycles 10010 = 18 cycles 10011 = 19 cycles 10100 = 20 cycles 10101 = 21 cycles 10110 = 22 cycles 10111 = 23 cycles 11000 = 24 cycles 11001 = 25 cycles 11010 = 26 cycles 11011 = 27 cycles 11100 = 28 cycles 11101 = 29 cycles 11110 = 30 cycles 11111 = 31 cycles [22:21] reserved [23] nwbe or nbe/dqm selection: is 0 = nwbe function 1 = nbe function note: the nwbe signal is operated at only coriting operation. the nbe/dqm signal is operated at writing and reading operation. [27:24] bank size: bs 0000 = disable 0001 = 1m 0010 = 2m 0011 = 4m 0100 = 8m 0101 = 16m 0110-1111 = reserved [29:28] page mode configuration: pmc 00 = normal rom or external i/o 01 = 4 word page 10 = 8 word page 11 = 16 word page [31:30] physical memory data bus width: dw 00 = reserved 01 = 8-bit 10 = 16-bit 11 = 32-bit 31 27 15 dw 28 16 11 12 21 20 tacc tpa 22 tacs bs is 8 7 4 3 0 30 29 23 24 pmc tcos tcoh figure 5-11. bank n control (bncon) register configuration S3C2500B memory controller 5- 25 notes 1. if waiten of waitcon register is enable, memory controller can't finish access cycle until newait signal is high. if you use slow device, you can set waiten to '1' and control ne wait signal. the memory controller checks newait signal at the last cycle of tacc. if you set waiten to '0', the f newait signal is ignored. 2. you can use memory control signals such as ncs, nwbe, noe, newait for 8 bit memory, and ncs, nwe16, noe, newait for 16 bit memory. 3. the dw of bank 0 is the same with b0size[1:0] pin. that is read only value. the initial value of other banks is "11". 5.6.3.2 muxed bus control register ext i/o bank controller supports memory devices which have the muxed bus interface. to use muxed bus memory device, muxed bus enable(mbe) and muxed bus address cycle(tma) for each bank in muxbcon register must be set. table 5-17. muxed bus control register register address r/w description reset value muxbcon 0xf0010020 r/w muxed bus control register 0x006db6db memory controller s 3c2500b 5- 26 [2-0] muxed bus address cycle for bank 0: tma0 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 000 = 8 cycles [5-3] muxed bus address cycle for bank 1: tma1 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 000 = 8 cycles [8-6] muxed bus address cycle for bank 2: tma2 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 000 = 8 cycles [11-9] muxed bus address cycle for bank 3: tma3 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 000 = 8 cycles [14-12] muxed bus address cycle for bank 4: tma4 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 000 = 8 cycles [17-15] muxed bus address cycle for bank 5: tma5 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 000 = 8 cycles [20-18] muxed bus address cycle for bank 6: tma6 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 000 = 8 cycles [23-21] muxed bus address cycle for bank 7: tma7 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles 000 = 8 cycles [24] address / data muxed bus enable for bank 0: mbe0 0 = disable 1 = enable [25] address / data muxed bus enable for bank 1: mbe1 0 = disable 1 = enable [26] address / data muxed bus enable for bank 2: mbe2 0 = disable 1 = enable [27] address / data muxed bus enable for bank 3: mbe3 0 = disable 1 = enable [28] address / data muxed bus enable for bank 4: mbe4 0 = disable 1 = enable [29] address / data muxed bus enable for bank 5: mbe5 0 = disable 1 = enable [30] address / data muxed bus enable for bank 6: mbe6 0 = disable 1 = enable [31] address / data muxed bus enable for bank 7: mbe7 0 = disable 1 = enable 31 27 15 28 11 12 21 20 8 3 0 30 29 23 24 26 25 17 18 14 9 6 5 2 m b e 7 m b e 6 m b e 5 m b e 4 m b e 3 m b e 2 m b e 1 m b e 0 t m a 7 t m a 6 t m a 5 t m a 4 t m a 3 t m a 2 t m a 1 t m a 0 figure 5-12. muxed bus control (muxbcon) register configuration S3C2500B memory controller 5- 27 5.6.3.3 wait control register slow external i/o devices requiring a long delay cycles on data read and write, should set ewaitenn in the waitcon register. (in this case newait pin should connected to the external i/o device, if multiple slow external i/o devices are connected to newait, each wait signals of external i/o devices should be or.) newait is low active signal. when newait is a low, S3C2500B is waiting until newait is high again. nready in the waitcon register is used when the external i/o device is ready for transferring data. when nready is low, S3C2500B transfers data. in addition, ext i/o controller provides cohdis in the waitcon register. when this cohdis is enabled as '1', ext i/o contoller disables chip selection hold time(tcoh) while access the same bank except first access cycle. so, tcohdis helps you to access slow external i/o devices more quickly. performance by using cohdis in the waitcon register when slow external i/o is used, could be improved. if you use slow external i/o, you must set tcoh to a proper value because you have to prevent the data collision. but, when you set tcoh to a non- zero value, all types of data access in the selected bank have tcoh cycle time. so although write to write, read to read, and write to read access don't have to use tcoh cycle, memory controller extends chip select signal during tcoh cycle. it decreases the system performance. in S3C2500B, to improve this operation, we add tcohdis field. if you set cohdis to '1', although tcoh isn't zero, tcoh is ignored in write to write, read to read, and write to read access. in those case memory controller operates as if tcoh is zero. table 5-18. wait control register register address r/w description reset value waitcon 0xf0010024 r/w wait control register 0x00000000 memory controller s 3c2500b 5- 28 [31:24] reserved [23] tcoh disable for bank 7: cohdis7 this forces tcoh to '0' for read to read, write to write, and write to read access in the bank 7 0 = disable 1 = enable [22] tcoh disable for bank 6: cohdis6 [21] tcoh disable for bank 5: cohdis5 [20] tcoh disable for bank 4: cohdis4 [19] tcoh disable for bank 3: cohdis3 [18] tcoh disable for bank 2: cohdis2 [17] tcoh disable for bank 1: cohdis1 [16] tcoh disable for bank 0: cohdis0 [15] external wait enable for bank 7: ewaiten7 0 = disable 1 = enable [14] external wait enable for bank 6: ewaiten6 [13] external wait enable for bank 5: ewaiten5 [12] external wait enable for bank 4: ewaiten4 [11] external wait enable for bank 3: ewaiten3 [10] external wait enable for bank 2: ewaiten2 [9] external wait enable for bank 1: ewaiten1 [8] external wait enable for bank 0: ewaiten0 [7] nwait / nready select for bank 7: nready7 0 = nwait 1 = nready [6] nwait / nready select for bank 6: nready6 [5] nwait / nready select for bank 5: nready5 [4] nwait / nready select for bank 4: nready4 [3] nwait / nready select for bank 3: nready3 [2] nwait / nready select for bank 2: nready2 [1] nwait / nready select for bank 1: nready1 [0] nwait / nready select for bank 0: nready0 reserved 31 15 11 12 21 20 8 3 0 23 24 17 18 14 9 6 5 2 22 19 16 13 10 7 4 1 c o h d i s 7 c o h d i s 6 c o h d i s 5 c o h d i s 4 c o h d i s 3 c o h d i s 2 c o h d i s 1 c o h d i s 0 e w a i t e n 7 e w a i t e n 6 e w a i t e n 5 e w a i t e n 4 e w a i t e n 3 e w a i t e n 2 e w a i t e n 1 e w a i t e n 0 n r e a d y 7 n r e a d y 6 n r e a d y 5 n r e a d y 4 n r e a d y 3 n r e a d y 2 n r e a d y 1 n r e a d y 0 figure 5-13. wait control (waitcon) register configuration S3C2500B memory controller 5- 29 5.6.4 timing diagram nrcs noe addr data addr hclko data fetch tacc data trcsd tnoed taddrd tdatad tacc = 0x8 (8 cycles) tcos = 0x0 (0 cycle) tcoh = 0x0 (0 cycle) tacs = 0x0 (0 cycle) trcsh tnoeh taddrh tdatah figure 5-14. read timing diagram 1 memory controller s 3c2500b 5- 30 nrcs nsdwe addr data addr hclko tacc data tacc = 0x8 (8 cycles) tcos = 0x0 (0 cycle) tcoh = 0x0 (0 cycle) tacs = 0x0 (0 cycle) taddrd trcsh tnsdweh taddrh tdatah trcsd tnsdwed tdatad figure 5-15. write timing diagram 1 S3C2500B memory controller 5- 31 nrcs noe addr data addr hclko data fetch tacc data tcoh tacs tcos tacc = 0x5 (5 cycles) tcos = 0x1 (1 cycle) tcoh = 0x1 (1 cycle) tacs = 0x1 (1 cycle) trcsd tnoed taddrd tdatad trcsh tnoeh taddrh tdatah figure 5-16. read timing diagram 2 memory controller s 3c2500b 5- 32 nrcs nsdwe addr data hclko tacc data tcoh tacs tcos tacc = 0x5 (5 cycles) tcos = 0x1 (1 cycle) tcoh = 0x1 (1 cycle) tacs = 0x1 (1 cycle) taddrd trcsh tnsdweh taddrh tdatah trcsd tnsdwed tdatad addr figure 5-17. write timing diagram 2 S3C2500B memory controller 5- 33 nrcs noe addr data hclko tacc = 5 (5 cycles) tcos = 1 (1 cycle) tcoh = 2 (2 cycle) tacs = 1 (1 cycle) cohdis = 1(enable) addr1 at bank n tacc data 1 tcoh tacs tcos addr2 at bank n tacc data 2 tacs tcos nsdwe tcoh < 1st access cycle at bank n > < 2nd access cycle at bank n > ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 5-18. read after write at the same bank (cohdis = 1) memory controller s 3c2500b 5- 34 nrcs noe ale data hclko data fetch tacc data tcoh tma tcos tacc = 0x4 (4 cycles) tcos = 0x1 (1 cycle) tcoh = 0x1 (1 cycle) tma = 0x2 (2 cycles) mbe = 1 (enable) addr tdatad trcsd trcsh tnoeh tnoed tdatah taddrh taleh taled taddrd figure 5-19. read timing diagram (muxed bus) S3C2500B memory controller 5- 35 nrcs nsdwe ale data hclko data fetch tacc data tcoh tma tcos tacc = 0x4 (4 cycles) tcos = 0x1 (1 cycle) tcoh = 0x1 (1 cycle) tma = 0x2 (2 cycles) mbe = 1 (enable) addr tdatad tgcsd tgcsh tnsdweh tnsdwed tdatah taddrh taleh taled taddrd figure 5-20. write timing diagram (muxed bus) memory controller s 3c2500b 5- 36 nrcs nsdwe addr data addr hclko tacc tacs tcos tacc = 0x5 (5 cycles) tcos = 0x1 (1 cycle) tcoh = 0x0 (0 cycle) tacs = 0x1 (1 cycle) ewaiten = 1 (enable) newait /nready tnsdwed taddrd taddrh tnsdweh tdatah trcsh trcsd tdatad data tnwaitd tnwaith figure 5-21. write timing diagram (newait) S3C2500B memory controller 5- 37 nrcs nsdwe addr data hclko tacc tacs tcos tacc = 0x5 (5 cycles) tcos = 0x1 (1 cycle) tcoh = 0x0 (0 cycle) tacs = 0x1 (1 cycle) ewaiten = 1 (enable) nready = 1 (nready) newait /nready tdatad trcsd tnsdwed taddrd tdatah taddrh tnsdweh trcsh data tnwaitd tnwaith addr figure 5-22. write timing diagram (nready) memory controller s 3c2500b 5- 38 5.7 sdram controller 5.7.1 features the sdram controller provides the following features: provides merging write buffer to improve system performance. supports for 16m-bit, 64m-bit, 128m-bit and 256m-bit sdram devices with two or four leaves. allows a direct interface to up to two banks of sdram. each bank supports 16 or 32-bits wide and up to 128m-byte in size. support byte, half-word and word transaction. cas latency can be 1, 2 or 3 provides auto refresh and self refresh mode to sustain the contents of sdram memory. S3C2500B memory controller 5- 39 5.7.2 sdram size and configuration the sdram controller supports a sdram memory ranging from 2 to 256m-byte. table 5-19. illustrates the supported sdram configurations when external bus width is 32-bits. table 5-20. illustrates the supported sdram configurations when external bus width is 16 bits. if 16m-bit device, which has two leaves, is used, only addr[13] is used to select a leaf. if sdram device, which has four leaves, is used, both addr[14] and addr[13] are used to select a leaf. only the chip select signals (nsdcs[1:0]) are to select a bank. the other sdram control signals are common to both banks. memory controller s 3c2500b 5- 40 table 5-19. supported sdram configuration of 32-bit external bus sdram technology sdram arrangement # banks address size leaf select total memory size row col addr[14] addr[13] (byte) 16m-bit 2m 8 1 11 9 ? haddr[21] 8 m 2 16 m 1m 16 1 11 8 ? haddr[21] 4 m 2 8 m 64m-bit 8m 8 1 12 9 haddr[22] haddr[21] 32 m 2 64 m 4m 16 1 12 8 haddr[22] haddr[21] 16 m 2 32 m 2m 32 1 11 8 haddr[22] haddr[21] 8 m 2 16 m 128m-bit 16m 8 1 12 10 haddr[22] haddr[21] 64 m 2 128 m 8m 16 1 12 9 haddr[22] haddr[21] 32 m 2 64 m 4m 32 1 12 8 haddr[22] haddr[21] 16 m 2 32 m 256m-bit 32m 8 1 13 10 haddr[22] haddr[21] 128 m 2 256 m 16m 16 1 13 9 haddr[22] haddr[21] 64 m 2 128 m 8m 32 1 13 8 haddr[22] haddr[21] 32 m 2 64 m note: banks: number of external sdram memory bank used. the controller supports up to two banks. leaf: internal bank of sdram devices. S3C2500B memory controller 5- 41 table 5-20. supported sdram configuration of 16-bit external bus sdram technology sdram arrangement # banks address size leaf select total memory size row col addr[14] addr[13] (byte) 16m-bit 2m 8 1 11 9 ? haddr[20] 4 m 2 8 m 1m 16 1 11 8 ? haddr[20] 2 m 2 4 m 64m-bit 8m 8 1 12 9 haddr[21] haddr[20] 16 m 2 32 m 4m 16 1 12 8 haddr[21] haddr[20] 8 m 2 16 m 128m-bit 16m 8 1 12 10 haddr[21] haddr[20] 32 m 2 64 m 8m 16 1 12 9 haddr[21] haddr[20] 16 m 2 32 m 256m-bit 32m 8 1 13 10 haddr[21] haddr[20] 64 m 2 128 m 16m 16 1 13 9 haddr[21] haddr[20] 32 m 2 64 m note: banks: number of external sdram memory bank used. the controller supports up to two banks leaf : internal bank of sdram devices. memory controller s 3c2500b 5- 42 5.7.3 address mapping table 5-21. illustrates the ahb address bus to the sdram address addr[14:0] mapping for various memory devices when external bus width is 32-bits. table 5-22. illustrates the ahb address bus to the sdram address addr[14:0] mapping for various memory devices when external bus width is 16-bits. table 5-21. sdram address mapping of 32-bit external bus sdram column address (addrout[14:0]) technology 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16m-bit 2m 8 * 21 * * ap * 22 9 8 7 6 5 4 3 2 1m 16 * 21 * * * * 9 8 7 6 5 4 3 2 64m-bit 8m 8 22 21 * * * 24 9 8 7 6 5 4 3 2 4m 16 22 21 * * * * 9 8 7 6 5 4 3 2 2m 32 22 21 * * * * 9 8 7 6 5 4 3 2 128m-bit 16m 8 22 21 * * 25 24 9 8 7 6 5 4 3 2 8m 16 22 21 * * * 24 9 8 7 6 5 4 3 2 4m 32 22 21 * * * * 9 8 7 6 5 4 3 2 256m-bit 32m 8 22 21 * * 26 25 9 8 7 6 5 4 3 2 16m 16 22 21 * * * 25 9 8 7 6 5 4 3 2 8m 32 22 21 * * * * 9 8 7 6 5 4 3 2 sdram row address (addrout[14:0]) technology 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16m-bit 2m 8 * 21 * * 20 19 18 17 16 15 14 13 12 11 10 1m 16 * 21 * * 20 19 18 17 16 15 14 13 12 11 10 64m-bit 8m 8 22 21 * 23 20 19 18 17 16 15 14 13 12 11 10 4m 16 22 21 * 23 20 19 18 17 16 15 14 13 12 11 10 2m 32 22 21 * * 20 19 18 17 16 15 14 13 12 11 10 128m-bit 16m 8 22 21 * 23 20 19 18 17 16 15 14 13 12 11 10 8m 16 22 21 * 23 20 19 18 17 16 15 14 13 12 11 10 4m 32 22 21 * 23 20 19 18 17 16 15 14 13 12 11 10 256m-bit 32m 8 22 21 24 23 20 19 18 17 16 15 14 13 12 11 10 16m 16 22 21 24 23 20 19 18 17 16 15 14 13 12 11 10 8m 32 22 21 24 23 20 19 18 17 16 15 14 13 12 11 10 S3C2500B memory controller 5- 43 table 5-22. sdram address mapping of 16-bit external bus sdram column address (addrout[14:0]) technology 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16m-bit 2m 8 * 20 * * ap * 21 8 7 6 5 4 3 2 1 1m 16 * 20 * * * * 8 7 6 5 4 3 2 1 64m-bit 8m 8 21 20 * * * 23 8 7 6 5 4 3 2 1 4m 16 21 20 * * * * 8 7 6 5 4 3 2 1 128m-bit 16m 8 21 20 * * 24 23 8 7 6 5 4 3 2 1 8m 16 21 20 * * * 23 8 7 6 5 4 3 2 1 256m-bit 32m 8 21 20 * * 25 24 8 7 6 5 4 3 2 1 16m 16 21 20 * * * 24 8 7 6 5 4 3 2 1 sdram row address (addrout[14:0]) technology 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16m-bit 2m 8 * 20 * * 19 18 17 16 15 14 13 12 11 10 9 1m 16 * 20 * * 19 18 17 16 15 14 13 12 11 10 9 64m-bit 8m 8 21 20 * 22 19 18 17 16 15 14 13 12 11 10 9 4m 16 21 20 * 22 19 18 17 16 15 14 13 12 11 10 9 128m-bit 16m 8 21 20 * 22 19 18 17 16 15 14 13 12 11 10 9 8m 16 21 20 * 22 19 18 17 16 15 14 13 12 11 10 9 256m-bit 32m 8 21 20 23 22 19 18 17 16 15 14 13 12 11 10 9 16m 16 21 20 23 22 19 18 17 16 15 14 13 12 11 10 9 note: ap: auto precharge (enable and disable auto precharge function are controlled by this bit). at precharge command this bit controls the all bank or specified b ank to be precharged. shaded numbers: leaf selection bits. *: unused bits memory controller s 3c2500b 5- 44 5.7.4 sdram commands the sdram controller issues specific commands to the sdram devices by encoding the nsdcs, nsdras, nsdcas and nsdwe outputs. table 5-23. lists all of the sdram commands understood by sdram devices. the controller supports a subset of these commands. table 5-23. sdram commands command cke nsdcs nsdras nsdcas nsdwe ba a10/ap mnemonic mode register set (mrs) h l l l l op code mrs refresh auto refresh h l l l h x ref self refresh l l l l h sref row activate h l l h h v x act read with auto precharge h l h l h v h rda without auto precharge l rd write with auto precharge h l h l l v h wra without auto precharge l wr burst stop h l h h l x bst precharge bank selection h l l h l v l pre all banks x h pall active power down l h x x x x apwdn precharge power down l h x x x ppwdn no operation h h h h h nop note: shaded boxes indicate commands not supported by sdram controller. they are included for completeness. x = don't care v = valid value (h or l) a10/ap = addr[10] /auto pre-charge S3C2500B memory controller 5- 45 5.7.5 external data bus width the sdram controller supports not only 32-bit data bus, but also 16-bit data bus. external data bus width can be selected by the xw field of cfgreg. 5.7.6 merging write buffer a merging write buffer compacts the writes of all widths into quad-word, which can be efficiently transferred to the sdram. the merging write buffer improves the data bandwidth of write operation. the merging write buffer is comprised of write buffer 0 and write buffer 1. each write buffer holds a quad word, which is the size of the default sdram data burst length. two write buffer configuration allows a new quad word to be buffered while the contents of the other quad-word buffer are transferred to memory. these write buffers can also merge non- contiguous writes to the same quad word address. the conditions of the write buffer flush are as follows: write miss: there is a write to a sdram address outside the current merging quad word address read hit: there is a read from the same address as the merging quad word. write buffer time out: the write buffer timer reaches zero. the write buffer is disabled. when a read hit, the write-back operation is completed before the requested data is read from memory to maintain data consistency between the write buffer and sdram memory. 5.7.7 self refresh the sdram controller provides the auto refresh (ref) and self refresh (sref) command to sustain the contents of the sdram. the auto refresh is issued to sdram periodically when refresh timer is expired. the self refresh is entered and exited by request of on-chip power manager. the self refresh is the preferred refresh mode for data retention and low power operation of sdram. in self refresh mode the sdram ignores all the input signals except cke. the refresh addressing and timing are internally generated to reduced power consumption. before disabling clock of the sdram controller the sdram must be in self refresh mode to sustain the sdram memory data. self refresh mode might be entered or exited by asserting or deasserting the self refresh request bit (srreg) of the peripheral clock disable register (pclkdis). it is possible to know if the sdram is in self refresh mode or not by reading out the srreg bit srack bit of the pclkdis register. if the self refresh mode change is on processing, the srack bit of the pclkdis is deasserted, and if the self refresh mode, change is completed, the srack bit is asserted. to recover from the self refresh mode to normal operation mode, the srack bit should be checked asserted before access the sdram. memory controller s 3c2500b 5- 46 5.7.8 basic operation sdram initialization sequence on power-on reset, software must initialize the sdram controller and each of the sdram connected to the controller. refer to the sdram data sheet for more detailed information on the start up procedure for the sdram used. typical example sequence is given below : 1. wait 200us to allow sdram power and clocks to stabil ize. 2. program the init[1:0] of the cmdreg to 01 . this automatically issues a pall command to the sdram. 3. write 0xf into the refresh timer register. this provides a refresh cycle every 15 clock cycles. 4. wait for a time period equivalent to 120 clock cycles (8 refresh cycles). 5. program the normal operational value into the refresh timer. 6. program the cfgreg to their normal operation values. 7. program the init[1:0] to 10 . this automatically issues a mrs command to the sdram. 8. program the init[1 :0] to 00 . the controller enters the normal mode. 9. program the cmdreg and wbtoreg to their normal operation values. 10. the sdram is now ready for normal operation. S3C2500B memory controller 5- 47 5.7.9 sdram special registers the address and reset value of the special registers in the sdram controller summarized in table 5-24. table 5-24. sdram special registers name address description reset value cfgreg 0xf0020000 configuration register 0x00099f0c cmdreg 0xf0020004 command register 0x00000000 refreg 0xf0020008 refresh timer register 0x00000020 wbtoreg 0xf002000c write buffer time-out register 0x00000000 5.3.9.1 configuration register the configuration register is 32-bit read/write (some bits are read only) register. this register contains sdram control parameters such as external bus width, memory type, and various timing parameters. table 5-25. sdram configuration register registers address r/w description reset value cfgreg 0xf0020000 r/w sdram configuration register 0x00099f0c memory controller s 3c2500b 5- 48 table 5-25. sdram configuration register (continue) reg0 bit description r/w default value xw [0] external data bus width 0 = external bus width is 32-bit. 1 = external bus width is 16-bit. r/w 0 ap [1] auto pre-charge control for sdram accesses 0 = auto pre-charge 1 = no auto pre-charge r/w 0 cl [3:2] cas latency 00 = reserved 01 = cl: 1 cycle 10 = cl: 2 cycles 11 = cl: 3 cycles r/w 11 d1[1:0] [5:4] sdram device density of bank 1 00 = 16m-bit sdram memory devices. 01 = 64m-bit sdram memory devices. 10 = 128m-bit sdram memory devices. 11 = 256m-bit sdram memory devices. r/w 00 d0[1:0] [7:6] sdram device density of bank 0 00 = 16m-bit sdram memory devices. 01 = 64m-bit sdram memory devices. 10 = 128m-bit sdram memory devices. 11 = 256m-bit sdram memory devices. r/w 00 rp [9:8] row pre-charge time 00 = rp: 1 cycle 01 = rp: 2 cycles 10 = rp: 3 cycles 11 = rp: 4 cycles r/w 11 rcd [11:10] ras to cas delay 00 = rcd: 1 cycle 01 = rcd: 2 cycles 10 = rcd: 3 cycles 11 = rcd: 4 cycles r/w 11 rc [15:12] row cycle 0000 = rc: 1 cycles 0001 = rc: 2 cycles ? 1110 = rc: 15 cycles 1111 = rc: 16 cycles r/w 1001 ras [19:16] row active time 0000 = ras: 1 cycles 0001 = ras: 2 cycles ? 1110 = ras: 15 cycles 1111 = ras: 16 cycles r/w 1001 [31:20] reserved ? notes 1. software should not write to configuration register when the sdram engine is busy. the sdr am engine status bit, busy in command register, can be used to check if the control engine is idle. 2. we recommend that the auto pre-charge should be disabled by asserting "1" on the ap of reg0 when the page hit ratio is more than 50%. S3C2500B memory controller 5- 49 [0] external data bus width : xw 0 = external bus width is 32 bit , 1 = external bus width is 16 bit [1] auto pre-charge control for sdram accesses: ap 0 = auto pre-charge , 1 = no auto pre-charge [3:2] cas latency: cl 00 = reserved 01 = 1 cycles 10 = 2 cycles 11 = 3 cycles [5:4] sdram device density of bank 1: d1 00 = 16 mbit sdram memory devices. 01 = 64 mbit sdram memory devices. 10 = 128 mbit sdram memory devices. 11 = 256 mbit sdram memory devices. [7:6] sdram device density of bank 0: d0 00 = 16 mbit sdram memory devices. 01 = 64 mbit sdram memory devices. 10 = 128 mbit sdram memory devices. 11 = 256 mbit sdram memory devices. [9:8] row pre-charge time: rp 00 = 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles [11:10] ras to cas delay: rcd 00 = 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles [15:12] row cycle: rc 0000 = 1 cycle 0001 = 2 cycles 0010 = 3 cycles 0011 = 4 cycles 0100 = 5 cycles 0101 = 6 cycles 0110 = 7 cycles 0111 = 8 cycles 1000 = 9 cycles 1001 = 10 cycles 1010 = 11 cycle 1011 = 12 cycles 1100 = 13cycles 1101 = 14 cycles 1110 = 15 cycles 1111 = 16 cycles [19:16] row active time: ras 0000 = 1 cycle 0001 = 2 cycles 0010 = 3 cycles 0011 = 4 cycles 0100 = 5 cycles 0101 = 6 cycles 0110 = 7 cycles 0111 = 8 cycles 1000 = 9 cycles 1001 = 10 cycles 1010 = 11 cycle 1011 = 12 cycles 1100 = 13cycles 1101 = 14 cycles 1110 = 15 cycles 1111 = 16 cycles [31:20] reserved 31 0 3 4 5 1 2 20 19 15 10 9 16 12 11 8 7 6 reserved rc d1 x w a p cl d0 rp rcd ras figure 5 -23. sdram configuration register memory controller s 3c2500b 5- 50 5.7.9.2 command register the configuration register 1 is 32-bit read/write (some bits are read only) register. the sdram initialization command, write buffer operation can be controlled by this register. table 5-26. sdram command register registers address r/w description reset value cmdreg 0xf0020004 r/w sdram command register 0x00000000 cmdreg bit description r/w default value init [1:0] control bits for sdram device initialization 00 = normal operation 01 = automatically issue a pall to the sdram 10 = automatically issue a mrs to the sdram 11 = reserved r/w 00 wbuf [2] write buffer enable 0 = disable merging write buffer 1 = enable merging write buffer note: disabling the write buffer will flush any stored value(s) to the external sdram memory r/w 0 busy [3] sdram controller status bit 0 = sdram controller is idle 1 = sdram controller is busy r 0 [31:4] reserved note: wbuf field of configuration register is a read-only bit if write buffers are not included in an ahb interface sub-block S3C2500B memory controller 5- 51 [1:0] control bits for sdram device initialization : 00 = normal operation 01 = automatically issue a pall to the sdram 10 = automatically issue a mrs to the sdram 11 = reserved [2] write buffer enable: 0 = disable merging write buffer 1 = enable merging write buffer [3] sdram controller status bit: 0 = sdram controller is idle 1 = sdram controller is busy [31:4] reserved 31 0 3 4 1 2 reserved w b u f i n i t b u s y figure 5 -24. sdram command register memory controller s 3c2500b 5- 52 5.7.9.3 refresh timer register the refresh timer register is 32-bit read/write (some bits are read only) register. this register sets the sdram refresh cycle. the refresh timer register is programmed with the number of system bus clock that should be counted between sdram refresh cycles. table 5-27. sdram refresh timer register registers address r/w description reset value refreg 0xf0020008 r/w refresh timer register 0x00000020 refreg bit description r/w default value refcyc [15:0] sdram refresh cycle r/w 0x00000020 [31:16] reserved for refresh period of 15.6us in 16, 64 and 128mbit, and a system bus clock frequency of 133mhz: 15.6 x 10 -6 x 133 x 10 6 = 2075 for refresh period of 7.8us in 256mbit, and a system bus clock frequency of 133mhz: 7.8 x 10 -6 x 133 x 10 6 = 1037 the refresh timer is set to 32 on reset. to ensure a refresh interval of less than 15.6us in 16, 64 and 128mbit after reset, the minimum frequency of system bus clock allowed is: 32 / (15.6 x 10 -6 )= 2.1mhz the refresh timer is set to 32 on reset. to ensure a refresh interval of less than 7.8us in 256mbit after reset, the minimum frequency of system bus clock allowed is: 32 / (7.8 x 10 -6 )= 4.2mhz the refresh register should be written to as early as possible in the system start-up procedure, especially when clock frequency is very low. [15:0] sdram refresh cycle [31:16] reserved 31 0 15 16 reserved refcyc figure 5 -25. sdram refresh timer register S3C2500B memory controller 5- 53 5.7.9.4 write buffer time-out register the write buffer time-out register works with the merging write buffer (if write buffer is enabled). this 16-bit read/write field of register sets the cycles for a forced flush of the write buffer. table 5-28. sdram write buffer time-out register registers address r/w description reset value wbtoreg 0xf002000c r/w write buffer time-out register 0x00000000 wbtoreg bit description r/w default value wbto [15:0] write buffer time-out delay time r/w 0x00000000 [31:16] reserved ? a write to a merging write buffer loads the value in the timeout register into the time-out down counter of the buffer. when the time-out counter reaches 0 the merging write buffer contents is written(flushed) to the external memory. the down counter is clocked by system bus clock. storing a value of 0 in the timeout register disables the write buffer timeout function. [15:0] write buffer time-out delay time: [31:16] reserved 31 0 15 16 reserved wbto figure 5 -26. sdram write buffer time-out register memory controller s 3c2500b 5- 54 5.7.10 sdram controller timing read addr data hclko nsdcas nsdwe cke nsdras nsdcs dqm/ nwbe row active row addr. tcc tcl tch tcsd tcsh trasd trash taddrd tcasd tcash taddrh trdd trdh tdqmd tdqmh trcd col. addr. data dqm latency cas latency figure 5 -27. single read operation (cas latency=2) S3C2500B memory controller 5- 55 read addr data hclko nsdcas nsdwe cke nsdras nsdcs dqm/ nwbe row active row addr. tcc tcl tch tcsd tcsh trasd trash taddrd tcasd tcash taddrh trdd trdh tdqmd tdqmh trcd col. addr. data dqm latency cas latency figure 5 -28. single read operation (cas latency=3) memory controller s 3c2500b 5- 56 write addr data hclko nsdcas nsdwe nsdras nsdcs data row active row addr. tcc tcl tcsd tcsh trasd trash taddrd tcasd tcash taddrh twdd twdh tdqmd tdqmh trcd twed tweh dqm / nwbe col. addr. cke tch figure 5 -29. single write operation S3C2500B memory controller 5- 57 col. addr. data data data data write addr data hclko nsdcas nsdwe cke nsdras nsdcs row active row addr. trcd tcc tcl tch tcsd tcsh trasd trash taddrd tcasd tcash taddrh trdh tdqmd tdqmh cas latency dqm latency trdd dqm/ nwbe figure 5-30. burst read operation (cas latency = 2) memory controller s 3c2500b 5- 58 col. addr. data data data data write addr data hclko nsdcas nsdwe cke nsdras nsdcs row active row addr. trcd tcc tcl tch tcsd tcsh trasd trash taddrd tcasd tcash taddrh trdh tdqmd tdqmh cas latency dqm latency trdd dqm/ nwbe figure 5-31. burst read operation (cas latency = 3) S3C2500B memory controller 5- 59 col. addr. data data write addr data hclko nsdcas nsdwe cke nsdras nsdcs dqm/ nwbe row active row addr. trcd tcc tcl tch tcsd tcsh trasd trash taddrd tcasd tcash taddrh twdh tdqmd tdqmh twdd data data twed tweh figure 5-32. burst write operation memory controller s 3c2500b 5- 60 notes S3C2500B i 2 c controller 6- 1 6 i 2 c controller 6.1 overview the S3C2500B has internal i 2 c (or iic) controller. it requires only two bus lines, a serial data line (sda) and a serial clock lines (scl). when the i 2 c is free, both lines are high level. it is connected to the same i 2 c. and the number of ic is limited only by the maximum bus capacitance of 400 pf. 6.2 features supports only single master mode. supports 8-bit, bi-directional, serial data transfers. supports 7-bit addressing. figure 6-1 shows a block diagram of the S3C2500B i 2 c controller data control serial clock line control serial clock prescaler control status register (iiccon) reset busy cond1 cond0 ack lrb ien prescaler register (iicps) system clock (f sysclk ) 16 scl sda bf shift buffer register (iicbuf) figure 6-1. i 2 c block diagram i 2 c controller s3c250 0b 6- 2 6.3 functional description the S3C2500B i 2 c controller is the master of the serial i 2 c. using a prescaler register, the user can program the serial clock frequency that is supplied to the i 2 c controller. the serial clock frequency is calculated as follows: serial clock frequency = f sysclk / (16 (prescaler register value + 1) + 3), where f sysclk is the system clock frequency. S3C2500B i 2 c controller 6- 3 6.4 i 2 c concepts 6.4.1 basic operation the i 2 c has two wires, a serial data line (sdl) and a serial clock line (scl), to carry information between the ics connected to the bus. each ic is recognized by a unique address and can operate as either a transmitter or receiver, depending on the function of the specific ics. the i 2 c is a multi-master bus. this means that more than ics which are capable of controlling the bus can be connected to it. data transfers proceed as follows: case 1: a master ic wants to send data to another ic (slave): 1. master addresses slave 2. master sends data to the slave (master is transmitter, slave is receiver) 3. master terminates the data transfer start condition address p 9 stop condition sda by receiver scl from master 8 9 8 r/w ack ack s sda by transmitter msb acknowledge from receiver acknowledge from receiver 2 1 msb data 2 1 figure 6-2. master transmitter and slave receiver case 2: a master ic wants to receive information from another ic (slave): 1. master addresses slave 2. master receives data from the slave (master is receiver, slave is transmitter) 3. master terminates the data transfer i 2 c controller s3c250 0b 6- 4 start condition address p 9 stop condition sda by receiver scl from master 8 9 8 r/w ack ack s sda by transmitter msb acknowledge from receiver acknowledge from transmitter 2 1 msb data 2 1 figure 6-3. master receiver and slave transmitter even in this case, the master ic generates the timing and terminates the transfer. the master ic is always responsible for generating the clock signals on the i 2 c. bus clock signals from a master can only be altered by 1) a slow slave ic which "stretches" the signal by temporarily holding the clock line low, or 2) by another master ic during arbitration. 6.4.2 general characteristics both sda and scl are bi-directional lines which are connected to a positive supply voltage through a pull-up resistor. when the i 2 c is free, the sda and scl lines are both high level. the output stages of i 2 c interfaces connected to the bus have an open-drain or open-collector to perform the wired-and function. data on the i 2 c can be transferred at a rate up to 100k-bits/s. the number of interfaces that can be connected to the bus is solely dependent on the limiting bus capacitance of 400 pf. 6.4.3 bit transfers due to the variety of different ics (cmos, nmos, and i2l, for example) which can be connected to the i 2 c, the levels of logic zero (low) and logic one (high) are not fixed and depend on the associated level of v dd . one clock pulse is generated for each data bit that is transferred. S3C2500B i 2 c controller 6- 5 6.4.4 data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when clock signal on the scl line is low. 6.4.5 start and stop conditions start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition is generated. the bus is considered to be free again when a brief time interval has elapsed following the stop condition. ? start condition: a high-to-low transition of the sda line while scl is high. ? stop condition: a low-to-high transition of the sda line while s cl is high. start condition address p 9 stop condition sda scl 1-7 8 9 1-7 8 9 1-7 8 r/w ack data ack data ack s figure 6-4. start and stop conditions i 2 c controller s3c250 0b 6- 6 6.4.6 data trsansfer operations 6.4.6.1 data byte format every data byte that is put on the sda line must be 8 bits long. the number of bytes that can be transmitted per transfer is unlimited. each byte must be followed by an acknowledge bit. data is transferred msb-first. if the receiver cannot receive another complete byte of data until it has performed some other functions (such as servicing an internal interrupt), it can hold the clock line scl low to force the transmitter into a wait state. the data transfer then continues when the receiver is ready for another byte of data and releases the scl line. 6.4.6.2 acknowledge procedure data transfer with acknowledge is obligatory. the acknowledge-related clock pulses must be generated by the bus master. the transmitter releases the sda line (high) during the acknowledge clock pulse. the receiver must pull down the sda line during the acknowledge pulse so that it remains stable low during the high period of this clock pulse. usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte is received. when a slave receiver does not acknowledge from the slave address, the slave must leave the data line high. the master can then generate a stop condition to abort the transfer. if a slave receiver acknowledges the slave address, but later in the transfer cannot receive any more data bytes, the master must again abort the transfer. this is indicated by the slave not generating the acknowledge on the first byte to follow. the slave leaves the data line high and the master generates the stop condition. if a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. the slave transmitter must then release the data line to let the master generate the stop condition. S3C2500B i 2 c controller 6- 7 6.4.6.3 data transfer format data transfers uses the format shown in figure 6-5. after the start condition has been generated, a 7-bit slave address is sent. the eighth bit is a data direction bit (r/w). a "0" direction bit indicates a transmission (write) and a "1" indicates a request for data (read). a data transfer is always terminated by a stop condition which is generated by the master. however, if a master still wishes to communicate on the bus, it can generate another start condition and address another slaves without first generating a stop condition. this feature supports the use of various combinations of read/write formats for data transfers. s slave address a data 1 (8 bits) a data 2 data m a p s slave address a data 1 (8 bits) a data 2 data m a a p multiple byte master receiver format: multiple byte master transmitter format: note: s (start) w (write; bit value is 0) r (read; bit value is 1) p (stop), a (acknowledge; the ack is first sent from the slave. afterwards, the direction depends on the data transfer direction. in other words, if the mater reads the data, it sends the ack.) nak (not acknowledge) w r n a k figure 6-5. data transfer format i 2 c controller s3c250 0b 6- 8 6.4.6.4 i 2 c addressing the addressing procedure for the i 2 c is such that the first byte after the start condition determines which slave the master will select. usually, this first byte immediately follows the start procedure. an exception is the "general call" address which can address all ics simultaneously. when this address is used, all ics should, in theory, respond with an acknowledge. however, ics can also be made to ignore this address. the second byte of the general call address then defines the action to be taken. 6.4.6.5 definition of bits in the first data byte the first seven bits of the first data byte make up the slave address. the eighth bit is the lsb, or direction bit, which determines the direction (r/w) of the message. when an address is sent, each ic on the bus compares the first 7 bits received following start condition with its own address. if the addresses match, the ic considers itself addressed by the master as a slave receiver or a slave transmitter. S3C2500B i 2 c controller 6- 9 6.5 i 2 c special registers the i 2 c controller has three special registers: a control status register (iiccon), a prescaler register (iicps), and a shift buffer register (iicbuf). 6.5.1 control status register (iiccon) the control status register for the i 2 c, iiccon, is described in table 6-2. table 6-1. control status register (iiccon) register address r/w description rest value iiccon 0xf00f0000 r/w control status register 0x00000000 table 6-2. iiccon register description bit number bit name description [0] buffer flag (bf) the bf bit is set when the buffer is empty in transmit mode or when the buffer is full in receive mode. to clear the buffer, you write a "0" to this bit. the bf bit is cleared automatically whenever the iicbuf register is written or read. [1] interrupt enable (ien) setting the interrupt enable bit to "1" enables the i 2 c interrupt. an interrupt is generated if bf bit is set to 1. [2] last received bit (lrb) the lrb bit is read only. it holds the value of the last received bit over the i 2 c. normally, this bit will be the value of the slave acknowledgement. to check for slave acknowledgement, you test the lrb. [3] acknowledge enable (ack) the ack bit is normally set to "1". this causes the i 2 c controller to send an acknowledge automatically after each byte. this bit must be "0" when the i 2 c controller is operating in receiver mode and requires no further data to be received from the slave transmitter. this causes a negative acknowledge on the i 2 c, which halts further reception from the slave device. [5:4] cond1, cond0 these bits control the generation of the start, stop, and repeat start conditions: "00" = no effect, "01" = start, "10" = stop, and "11" = repeat start. when start condition, bf bit should be set simultaneously. when repeat start condition, ack bit should be set simultaneously. [6] bus busy (busy) this bit is a read-only flag that indicates when the i 2 c is in use. a "1" indicates that the bus is busy. this bit is set or cleared by a start or stop condition, respectively. [7] reset if "1" is written to the reset bit, the i 2 c controller is reset to its initial state. [31:8] reserved not applicable. i 2 c controller s3c250 0b 6- 10 [0] buffer flag (bf) 0 = automatically cleared when the iicbuf register is written or read. to manually clear the bf, write 0. 1 = automatically set when the buffer is empty in transmit mode or when the buffer is full in receive mode. [1] interrupt enable (ien) 0 = disable 1 = enable; an interrupt is generated if the bf bit is 1. [2] last received bit (lrb) use this read-only status bit to check for ack signals from the receiver (slave), or to monitor sda operation of sda when writing 11 to iiccon [5:4] for repeated starts. 0 = the most recent sda is low. (ack is received) 1 = the most recent sda is high. (ack not received) [3] acknow enable (ack) controls generation of an ack signal in receive mode. 0 = do not generate an ack at 9th scl (no more received data is required from the slave) 1 = generate an ack signal at 9th scl. [5:4] cond 1 and cond 0 generate a control such as start or stop. 00 = no effect. 01 = generate start condition. (bf bit should be set simultaneously.) 10 = generate stop condition. 11 = scl will be released to high level to generate repeated start condition. (ack bit should be set simultaneously.) [6] bus busy (busy) data transmission is in progress on the iic-bus. 0 = bus is currently not in use. (not busy) 1 = bus is in use. (busy) [7] reset 0 = normal 1 = reset the iic controller. [31:8] reserved i e n l r b a c k c o n d 0 c o n d 1 b u s y r e s e t reserved 31 8 7 0 6 5 4 3 2 1 b f figure 6-6. i 2 c control status register S3C2500B i 2 c controller 6- 11 6.5.2 shift buffer register (iicbuf) the shift buffer register for the i 2 c described in table 6-4. table 6-3. iicbuf register register address r/w description rest value iicbuf 0xf00f0004 r/w shift buffer register undefined table 6-4. iicbuf register description bit number bit name description [7:0] data this data field acts as serial shift register and read buffer for interfacing to the i 2 c. all read and write operations to/from the i 2 c are done via this register. the iicbuf register is a combination of a shift register and a data buffer. 8-bit parallel data is always written to the shift register, and read form the data buffer. i 2 c data is always shifted in or out of the shift register. [31:8] reserved not applicable. 6.5.3 prescaler register (iicps) the prescaler register for the i 2 c is described in table 6-6. table 6-5. iicps register register address r/w description rest value iicps 0xf00f0008 r/w prescaler register 0x00000000 table 6-6. iicps register description bit number bit name description [15:0] prescaler value this prescaler value is used to generate the serial i 2 c clock. the system clock is divided by (16 x (prescaler value + 1) + 3) to make the serial i 2 c clock. if the prescaler value is zero, the system clock is when divided by 19 to make the serial i 2 c clock. therefore, when i 2 c is used to 100kbit/s in the standard mode, the prescaler value must be changed. [31:16] reserved not applicable. i 2 c controller s3c250 0b 6- 12 6.5.4 prescaler counter register (iiccnt) the prescaler counter register for the i 2 c is described in table 6-8. table 6-7. iiccnt register register address r/w description rest value iiccnt 0xf00f000c r/w prescaler counter register 0x00000000 table 6-8. iiccnt register description bit number bit name description [15:0] counter value this 16-bit value is the value of the prescaler counter. it is read (in test mode only) to check the counter?s current value. [31:16] reserved not applicable. 6.5.5 interrupt pending register (iicpnd) the i 2 c interrupt pending register for the i 2 c is described in table 6-10. table 6-9. iicpnd register register address r/w description rest value iicpnd 0xf00f0010 r/w interrupt pending register 0x00000000 table 6-10. iicpnd register description bit number bit name description [0] interrupt pending value this bit is set when the interrupt is generated and cleared when the same value of interrupt pending bit is rewritten. [31:1] reserved not applicable. S3C2500B i 2 c controller 6- 13 iicbuf = iic slave address | 0 x 0 no yes iic setup (reset, iicps setup) iiccon = start | bf iicbuf = iic upper address iicbuf = iic lower address iiccon = stop all data sent? iicbuf = one byte data figure 6-7. write operation flow chart i 2 c controller s3c250 0b 6- 14 iicbuf = iic slave address | 0 x 0 no yes iic setup (reset, iicps setup) iiccon = start | bf iicbuf = iic upper address iicbuf = iic lower address iiccon = repeated start | ack iiccon = start | ack empty the bf bit iiccon = stop send no ack all data received? iicbuf = one byte data iicbuf = iic slave address | 0 x 1 figure 6-8. read operation flow chart S3C2500B ethernet c ontroller 7- 1 7 ethernet controller 7.1 overview the S3C2500B has two ethernet controllers that operate at either 100m-bit or 10m-bit per second in half-duplex or full-duplex mode. in half-duplex mode, the ieee 802.3 carrier sense multiple access with collision detection (csma/cd) protocol is supported. in full-duplex mode, the ieee 802.3 mac control layer is also supported, including the pause operation for flow control. the two ethernet controllers support both the media independent interface (mii) and the buffered dma interface (bdi). the mac layer consists of a receiver and a transmitter blocks, a flow control block, a content addressable memory(cam) for storing network addresses, a number of commands, status, and error counter registers. the mii supplies the transmission and reception clocks of 25mhz for 100m-bps operation, 2.5 mhz for the 10m- bps speed or 1mhz for (the 1m-bps for) home pna. the mii conforms to the iso/iec 802-3 standards. b d i m i i / 10 m b p s 7 - w i r e mac txfifo (80x9) mac preamble/ sfd/crc/ pad/jam generator mac rxfifo (16x10) cam checker (32x32) crc checker mac control and status station manager m d i bdma physical layer preamble/ sfd detector backoff and intergap timer flow control bdma tx buffer controller bdma tx buffer (64 words) bus arbiter/ controller bdma rx buffer (64 words) bdma rx buffer controller cam contents memory (32-words) bdma control and satus register 32 32 32 32 32 32 s y s t e m b u s figure 7-1. ethernet diagram ethernet controller S3C2500B 7- 2 7.2 features the most important features and benefits of each ethernet controller are as follows: cost-effective connection to an external ric(repeater interface controller)/ethernet backbone buffered dma (bdma) engine with burst mode bdma tx/rx buffers (btxbuff and brxbuff: 256 bytes/256 bytes) mac tx/rx fifos(mtxfifo and mrxfifo: 80 bytes/16 bytes) to support re-transmission after collision without dma request and dma latency data alignment logic old and new physical media support (compatible with existing 10m-bps networks) 100m-bps or 10m-bps operation to allow price/performance options and to support phased conversions full ieee 802.3 compatibility for existing applications media independent interface (mii) or 7-wire interface station management (sta) signaling for external physical layer configuration and link negotiation on-chip cam (21 mac addresses) full-duplex mode for doubled bandwidth hardware support of pause operation for full-duplex flow control long frame mode for specialized environment short frame mode for fast testing pad generation for easy processing and reduced processing time S3C2500B ethernet c ontroller 7- 3 7.3 mac function blocks the major function blocks of each ethernet of mac layer are described in table 7-1 and figure 7-1. table 7-1. mac function block descriptions function block description media independent interface (mii) the interface between the physical layer and the transmit/receiver blocks. transmitter block moves the outgoing data from the transmit buffer to the mii. this includes circuits for generating the crc, checking parity, and generating preamble or jam. also has timers for back-off after collision and the inter-frame gap follows a transmission. receiver block accepts incoming data from the mii and stores it in the mrxfifo. the receiver block has logic for computing and checking the crc value, generating parity for data from the mii, and checking minimum and maximum frame lengths. also has a cam that provides for address lookup, and for acceptance or rejection for frame based on their destination address. flow control block recognizes mac-control frame and supports the pause operation for full-duplex links. the flow control block also supports generation of pause frame, and provides timers and counters for pause control. mac control (command) and status registers controls programmable options, including the enabling or disabling of signals that notify the system when conditions occur. the status registers hold information for error handling software, and the error counters accumulate statistical information for network management software. loop-back circuit provides for mac-layer testing in isolation from the mii and physical layer. 7.3.1 media independent interface (mii) both transmitter and receiver blocks operate using the mii, which was developed by the ieee802.3 task force on 100-mbps ethernet. this interface has the following characteristics: media independence multi-vendor points of interoperability supports connection of mac layer and physical layer entity (phy) devices capable of supporting both 100m-bps and 10m-bps and 1m-bps data rates data and delimiters are synchronous to clock references provides independent 4-bit wide transmit and receive data paths uses ttl signal levels that are compatible with common digital cmos asic processes supports connection of phy layer and station management (sta) devices provides a simple management interface capable of driving a limited length of shielded cable ethernet controller S3C2500B 7- 4 7.3.2 physical layer entity (phy) the physical layer entity, or phy, performs all of the decoding/encoding on incoming and outgoing data. the manner of decoding and encoding (manchester for 10base-t, 4b/5b for 100base-x, or 8b/6t for 100base-t4) does not affect the mii. the mii provides the raw data it receives, starting with the preamble and ending with the crc. the mii expects raw data for transmission, also starting with the preamble and ending with the crc. the mac layer also generates jam data and transmits it to the phy. 7.3.3 buffered dma interface (bdi) the buffered dma interface (bdi) supports read and write operations across the system bus. two eight-bit buses transfer data with optional parity checking. the system interface initiates data transfers. the mac-layer controller responds with a ready signal to accept data for transmission, or to deliver data which has been received. an end- of-frame signal indicates the boundary between packets. 7.3.4 the mac transmitter block the mac transmitter block is responsible for transmitting data. it complies with the ieee802.3 standard for the carrier sense multiple access with collision detection (csma/cd) protocol. 7.3.4.1 mac txfifo(mtxfifo) the mtxfifo has an 80-byte depth. an extra bit is associated with each data byte for parity checking. this 80 -byte by 9-bit size allows the first 64 bytes of a data frame to b e stored and retransmitted, without further system involvement, in case of a collision. if no collision occurs and transmission is underway, the additional 16 bytes handle system latency and avoid fifo under-run. when the system interface has set the mactxcon.0 bit, the transmission state machine requests data from the bdi. the system controller then fetches data from the system memory. the data is stored in the mtxfifo until the threshold for transmit data is satisfied. when the mtxfifo is not full, a request is issued to the bdi for more data. it then appends the calculated crc to the end of the data (unless the crc truncate bit in the transmit control register is set). 7.3.4.2 preamble and jam generator as soon as the mactxcon.0 bit is set and there are eight bytes of data in the mtxfifo, the transmission state machine starts the transmission by asserting the tx_en signal and transmitting the preamble and the start frame delimiter (sfd). in case there is a collision, it transmits a 32-bit string of `1?s after the preamble as a jam pattern. 7.3.4.3 pad generator if a short data frame is transmitted, the mac will normally generate pad bytes to extend the frame to a minimum of 64 bytes. the pad bytes consist entirely of ?0? bits. a control bit is also used to suppress the generation of pad bytes. 7.3.4.4 parallel crc generator the crc generation of the outgoing data starts from the destination address and continues through the data field. you can suppress crc generation by setting the appropriate bit in the transmit control register. this is useful in testing, for example, to force the transmission of a bad crc in order to test error detection in the receiver. it can also be useful in certain bridge or switch applications, where end-to-end crc checking is desired. S3C2500B ethernet c ontroller 7- 5 7.3.4.5 threshold logic and counters the transmission state machine uses a counter and logic to control the threshold of when the transmission can begin. before transmitting the mac waits until eight bytes or a complete frame has been placed in the mtxfifo. this gives the dma engine some latency without causing an underflow during transmission. 7.3.4.6 back-off and retransmit timers when a collision is detected on the network, the transmitter block stops the transmission and starts a jamming pattern to ensure that all the nodes detect the collision. after this, the transmitter waits for a minimum of 96 bit times and then retransmits the data. after 16 attempts, the transmission state machine sets an error bit and generates an interrupt, if enabled, to signify the failure to transmit a frame due to excessive collisions. it flushes the mtxfifo, and the mac is ready for the next frame. 7.3.4.7 transmit data parity checker data in the fifo is even-parity. when data is read for transmission, the transmission state machine checks the parity. if a parity error is detected, the transmit data parity checker does the following: it stops transmission. it sets the parity error bit in the transmit status register. it generates an interrupt, if enabled. 7.3.4.8 transmission state machine the transmission state machine is the central control logic for the transmitter block. it controls the passing of signals, the timers, and the posting of errors in the status registers. ethernet controller S3C2500B 7- 6 7.3.5 the mac receiver block it complies with the ieee802.3 standard for carrier sense multiple access with collision detection (csma/cd) protocol. after it receives a frame, the receiver block checks for a number of error conditions: crc errors, alignment errors, and length errors. by setting bits in appropriate control registers some error condition is disabled. depending on the cam status, the destination address and the receiver block may reject an otherwise acceptable frame. 7.3.5.1 mac rxfifo (mrxfifo) the mrxfifo accepts data one byte at a time. the parity starts with the destination address. the receiver updates the counter with the number of bytes received. as the fifo stores the data, the cam block checks the destination address against its stored address. if the cam recognizes the address, the mrxfifo continues receiving the frame. if the cam block does not recognize the address and rejects the frame, the receiver block discards the frame and flushes the mrxfifo. 7.3.5.2 cam and address recognition the cam compares the destination address of the received frame to stored addresses. if it finds a match, the receive state machine continues to receive the frame. the cam is organized to hold six-byte address entries. the cam can store 21 address entries. the cam address entries 0, 1, and 18 are used to send the pause control frame. to send a pause control frame, you must write the destination address to cam0, the source address to cam1, and length/type, op-code, and operand to the cam18 entry. you must write the mac transmit control register to set the send pause control bit. in addition, cam19 and cam20 can be used to construct a user-define control frame. 7.3.5.3 parallel crc checker the receiver block computes a crc across the data and the transmitted crc, and then checks that the resulting syndrome is valid. a parallel crc checking scheme handles data arriving in 4-bit nibbles at 100m-bps. to support full-duplex operation, the receiver and transmitter blocks have independent crc circuits. 7.3.5.4 receive state machine in mii mode, the receiver block receives data from the mii on the rxd[3:0] lines. this data is synchronized to rx_clk at 25 mhz or 2.5mhz. in 7-wire mode, and at 10mhz, data is received on the rxd_10m line only. after it detects the preamble and sfd, the receive state machine arranges data in byte configurations, generates parity, and stores the result in the mrxfifo one byte at a time. if the cam block accepts the destination address, the mrxfifo stores the rest of the frame. any error in reception will reset the mrxfifo and the state machine will wait for the end of the current frame. it will then be idle while it is waiting for the next preamble and sfd. 7.3.5.5 bdma interface receive state machine the bdma i/f receive state machine issues the rx_rdy signal whenever data is present in the receive fifo. the last byte of the packet is signaled by asserting the rx_eof. in case there are any errors during the reception, or if there is a crc error at the end, the bdma i/f receive state machine asserts the rx_toss signal to indicate that the received packet should be discarded. S3C2500B ethernet c ontroller 7- 7 7.3.6 flow control block flow control is done using the mac control frame. the receiver sends control frames to the transmitter and the transmitter pauses its operation during the time interval specified in the control frames. the flow control block provides the following functions: recognition of mac control frames received by the receiver block transmission of mac control frames, even if transmitter is paused timers and counters for pause operation command and status register (csr) interface options for passing mac control frames through to software drivers for details, refer to the full-duplex pause operation section in this chapter. 7.3.7 buffered dma (bdma) overview the bdma engine controls the data feeding and reception between the mac and the system bus (amba) using two buffers, bdma txbuff (btxbuff) and bdma rxbuff (brxbuff). the btxbuff and brxbuff hold data and status information for frames being transmitted and received, respectively. each buffer is controlled by the block, which consists of a bus arbiter, a control and status block, buffer descriptors. 7.3.7.1 bus arbiter the bus arbiter decides which of the bdma buffer controllers, transmit (tx) or receive (rx), has the highest priority for accessing the system bus. the prioritization is dynamic. the bdma arbiter outputs a bus request signal (nreq) to the amba when rx buffer (brxbuff) contains 4-words data, or eof (end of frame) was saved to the buffer, or tx buffer (btxbuff) contains 4-word free space. after it receives a bus acknowledgement signal (nack) from the amba, the bdma bus arbiter determines the correct bus access priority. ethernet controller S3C2500B 7- 8 7.3.7.2 control and status this block controls the read/write operations of the bus master across the amba. the control logic supports the following operations: ? fixed 4-word burst size control between tx and rx. ? transmit threshold control (based on 1/8 of transmit buffer size) to match transmission latency to system bus latency. ? little-endian byte swapping, to support the data transfer of little-endian memory usage for frame data. ? big-endian byte swapping, to support the data transfer of big-endian memory usage for frame data. when memory operate on big-endian format and byte unit access, ethernet transmit(rece ive) reliable data by setting bdmatx(rx)con.7 to ?1? . ? a transmit/receive alignment widget to circumvent word alignment restrictions. the beginning of a frame should be placed on word boundary. misalignment of the bdma transfer would complicate the design of the dma and degrade the performance. to avoid this, you can use an alignment widget between the bdma buffer (word) and the mac fifo (byte) by controlling the widget field in tx buffer descriptor. the widget discards the first 'n' bytes (up to three), where 'n' is the value read from the tx buffer descriptor that configures the alignment widget. in the receiver, the bdma bus arbiter inserts a programmable number of bytes (up to three) into the received data stream while the preamble is being received. this adds some padding to the beginning of the frame. this padding can then be used to solve the alignment problem without having to use a copy of the buffer. because the data is inserted prior to the concatenation of bytes into words, it does not misalign the subsequent dma transfer. the number of the alignment bytes is read from the bdmarxcon.5-4 (brxwa). S3C2500B ethernet c ontroller 7- 9 7.3.7.3 buffer descriptor the ownership bit in the buffer descriptor controls the owner of the descriptor. when the ownership bit is '1', the bdma controller owns the descriptor. when the bit is '0', the cpu owns the descriptor. the owner of the descriptor always owns the associated data frame. (the descriptor's frame start address field always points to this frame.) software sets the bdmarxlen register to the length, and also sets the bdmarxdptr register to point to a chain of buffer descriptors, all of which have their ownership bits set. the bdma engine can then be started to set the bdmarxcon.10 (brxen). when a frame is received, it is copied into the external memory at the address specified by the bdmarxdptr register. please note that no configurable offset or page boundary calculation is required. the received frame is written into the buffer in the external memory until the end of frame is reached, or until the length exceeds the configured maximum frame size. if the entire frame is received successfully, the status bits in the buffer descriptor are set to indicate this. otherwise, the status bits are set to indicate that an error occurred. the ownership bit in the status and length field is cleared and an interrupt may now be generated. the length field in the rx buffer descriptor is updated in summation with previous length filed of rx buffer descriptor. the bdma points the next buffer descriptor automatically, but bdmatxdptr and bdmarxdptr is not updated to the next pointer. it always has the first buffer descriptor address. because bdma pointers are fixed as initial addresses, bdma count register values indicate the number of frames to be handled by bdma. in addition, users can determine how many buffer descriptors to use by controlling the bdmatxcon.3~0 (btxnbd) and bdmarxcon.3-0 (brxnbd). if the last buffer descriptor was used by the bdma, the next buffer is the first buffer and bdma count register value goes to zero. finally, the status and length fields in the first and the last rx buffer descriptors are updated. the length field value is same in the first and last rx buffer descriptor. the status field of the middle rx buffer descriptors does not have any mean. when the received frame size exceeds the maximum frame size (brxmfs bits of bdmarxlen), the data frame will be overwritten by the last word of maximum frame. if overflow occurred, this status is written to status field bit.20 in the rx buffer descriptor. when the bdma reads a descriptor, if the ownership bit is not set, it has two options: ? skip to the next buffer descriptor, or ? generate an interrupt and halt the bdma operation. if cpu set to skip bit in rx buffer descriptor?s status field, bdma goes next buffer without interrupt or bdma stop. during transmission, the two-byte frame length at the tx buffer descriptor is moved into the bdma internal tx counter. after transmission, tx status is saved in the tx buffer descriptor. the bdma points to the next buffer descriptor address register for the linked list structure. however, bdmatxdptr register cannot be updated. you should check btxbdcnt register to detect how many frames were handled. ethernet controller S3C2500B 7- 10 [31:0] buffer pointer a dd ress of the data be transmitted. [31] ownership bit (o) 0 = cpu 1 = bdma [30:18] txstatus writing in this field don't have any mean. [30] reserved [29] paused t ran smission of frame was paused due to the reception of a pause control frame. [28] halted the transmission of the next frame is halted when maccon.1 (mhaltimm) is set, or when mactxcon.0 (mtxen) is clear. [27] sqeerr signal quality error [26] defer the transmission of frame was deferred. [25] coll the collision is occured in half-duplex. the current frame is retried to send. [24] comp the transmition is finished. [23] parerr mtxfifo parity error [22] latecoll the co llisio n occured after 64 byte times. [21] nocarr no carrier sense is detected when mac tx transmits a frame. [20] defererr m ac doesn't run the transmission process until 6071-nibble or 24284-bit times. the current frame is aborted. [19] underflow mtxfifo underflow [18] excoll the excessive collision is occured 16 times consecutively . the current frame is aborted. [17:16] txwidget the transmission widget alignment of the current frame. [15:0] txlength th e size of the transmission data by using the bdma. the unit of the length field is the byte and the hexdecimal number. 31 15 0 buffer pointer 16 30 o txstatus 18 17 txwidget txlength figure 7-2. data structure of tx buffer descriptor S3C2500B ethernet c ontroller 7- 11 [31:0] buffer pointer address of the frame data be saved. [31] ownership bit (o) 0 = cpu 1 = bdma [30] skip bd (b) set this bit to skip the current buffer descriptor when the ownership bit is cleared. [29] sof (s) set by the bdma to indicate the first bd for a frame. [28] eof (e) set by the bdma to indicate the last bd for a frame. [27] done (d) set by the bdma on the first bd when the reception of a frame finished and it used multiple bd's. [26:16] rx status the rx status field of the received frame. [26] mso rx frame size is larger than the maximum rx frame size(brxmfs). [25] halted the reception of next frame is halted when maccon.1 (mhaltimm) is set, or when macrxcon.0 (mrxen) is clear. [24] mrx10stat the frame was received over 10mbps(wire-7) interface. [23] brxdone the reception process by the bdma is done without error. [22] rxparerr mrxfifo parity error [21] mufs set when the size of the rx frame is larger than the maximum untagged frame size(1518bytes) if the long packet is not enabled in the mac rx control register. [20] overflow mrxfifo overflow [19] crcerr crc at the end of a frame did not match the computed crc32, or else that phy asserted rx_er during the frame reception. [18] alignerr set if the frame length in bit is not the multiple of eight and the crc is invalid. [17] reserved [16] reserved [15:0] rxlength the byte count of the received data is written in hexa-decimal by the bdma. 31 15 0 buffer pointer 16 30 o status rxlength b s e d 29 28 27 26 figure 7-3. data structure of rx buffer descriptor ethernet controller S3C2500B 7- 12 buffer descriptor start address register buffer #1 buffer #2 buffer #n memory for frame brxbdcnt+0 + note: the brxbs and brxmfs of the bdmarxlen register have to keep multiples of 16 in byte unit. for long packet reception larger than 1518-byte, the brxbs should be at least 4 bytes larger than the brxmfs or less than 1518-byte for the reception with a single or multiple buffer descriptors, respectively. brxbs of bdmarxlen not used brxbs of bdmarxlen brxbs of bdmarxlen memory for rx bufer descriptor not used not used brxbdcnt+(n-1) brxbdcnt+1 buffer pointer #1 status length buffer pointer #2 status length buffer pointer #n status length . . . . . . . . . . . . . . . . . . figure 7-4. data structure of the receive frame S3C2500B ethernet c ontroller 7- 13 7.4 ethernet controller special registers there are two ethernet controllers in S3C2500B. they are same each other except the base addresses for internal registers. table 7-2. ethernet 0 special registers registers address r/w description reset value bdmatxcona 0xf00a0000 r/w buffered dma transmit control register 0x00000000 bdmarxcona 0xf00a0004 r/w buffered dma receive control register 0x00000000 bdmatxdptra 0xf00a0008 r/w transmit buffer descriptor start address 0x00000000 bdmarxdptra 0xf00a000c r/w receive buffer descriptor start address 0x00000000 btxbdcnta 0xf00a0010 r/w bdma tx buffer descriptor counter 0x00000000 brxbdcnta 0xf00a0014 r/w bdma rx buffer descriptor counter 0x00000000 bmtxintena 0xf00a0018 r/w bdma/mac tx interrupt enable register 0x00000000 bmrxintena 0xf00a001c r/w bdma/mac rx interrupt enable register 0x00000000 bmtxstata 0xf00a0020 r/w bdma/mac tx status register 0x00000000 bmrxstata 0xf00a0024 r/w bdma/mac rx status register 0x00000000 bdmarxlena 0xf00a0028 r/w receive frame size 0x00000000 cftxstata 0xf00a0030 r transmit control frame status 0x00000000 maccona 0xf00b0000 r/w mac control 0x00000000 camcona 0xf00b0004 r/w cam control 0x00000000 mactxcona 0xf00b0008 r/w transmit control 0x00000000 mactxstata 0xf00b000c r/w transmit status 0x00000000 macrxcona 0xf00b0010 r/w receive control 0x00000000 macrxstata 0xf00b0014 r/w receive status 0x00000000 stadataa 0xf00b0018 r/w station management data 0x00000000 stacona 0xf00b001c r/w station management control and address 0x00006000 camena 0xf00b0028 r/w cam enable 0x00000000 misscnta 0xf00b003c r(clr)/w missed error count 0x00000000 pzcnta 0xf00b0040 r pause count 0x00000000 rmpzcnta 0xf00b0044 r remote pause count 0x00000000 cama 0xf00b0080- 0xf00b00fc w cam content (32 words) undefined ethernet controller S3C2500B 7- 14 table 7-3. ethernet 1 special registers registers address r/w description reset value bdmatxconb 0xf00c0000 r/w buffered dma transmit control register 0x00000000 bdmarxconb 0xf00c0004 r/w buffered dma receive control register 0x00000000 bdmatxdptrb 0xf00c0008 r/w transmit buffer descriptor start address 0x00000000 bdmarxdptrb 0xf00c000c r/w receive buffer descriptor start address 0x00000000 btxbdcntb 0xf00c0010 r/w bdma tx buffer descriptor counter 0x00000000 brxbdcntb 0xf00c0014 r/w bdma rx buffer descriptor counter 0x00000000 bmtxintenb 0xf00c0018 r/w bdma/mac tx interrupt enable register 0x00000000 bmrxintenb 0xf00c001c r/w bdma/mac rx interrupt enable register 0x00000000 bmtxstatb 0xf00c0020 r/w bdma/mac tx status register 0x00000000 bmrxstatb 0xf00c0024 r/w bdma/mac rx status register 0x00000000 bdmarxlenb 0xf00c0028 r/w receive frame size 0x00000000 cftxstatb 0xf00c0030 r transmit control frame status 0x00000000 macconb 0xf00d0000 r/w mac control 0x00000000 camconb 0xf00d0004 r/w cam control 0x00000000 mactxconb 0xf00d0008 r/w transmit control 0x00000000 mactxstatb 0xf00d000c r/w transmit status 0x00000000 macrxconb 0xf00d0010 r/w receive control 0x00000000 macrxstatb 0xf00d0014 r/w receive status 0x00000000 stadatab 0xf00d0018 r/w station management data 0x00000000 staconb 0xf00d001c r/w station management control and address 0x00006000 camenb 0xf00d0028 r/w cam enable 0x00000000 misscntb 0xf00d003c r(clr)/w missed error count 0x00000000 pzcntb 0xf00d0040 r pause count 0x00000000 rmpzcntb 0xf00d0044 r remote pause count 0x00000000 camb 0xf00d0080- 0xf00d00fc w cam content (32 words) undefined S3C2500B ethernet c ontroller 7- 15 7.4.1 bdma relative special register 7.4.1.1 buffered dma transmit control register table 7-4. bdmatxcon register registers address r/w description reset value bdmatxcona 0xf00a0000 r/w buffered dma transmit control register 0x00000000 bdmatxconb 0xf00c0000 r/w buffered dma transmit control register 0x00000000 table 7-5. bdma transmit control register description bit number bit name description [3:0] bdma tx number of buffer descriptor (btxnbd) you can select number of buffer descriptor. 0000 = 2 0 , 0001 = 2 1 , 0010 = 2 2 ,?.., 11xx = 2 12 [6:4] bdma transmit to mac tx start level (btxmsl) these bits determine when to move the data of the new frame in the bdma tx buffer (btxbuff) to the mac txfifo (mtxfifo) at a new frame arrival. 000 means no wait, 001 means wait to fill 1/8 of the bdma tx buffer, 010 means wait to fill 2/8 of the buffer, and so on through 100, which means wait to fill 4/8 of the bdma tx buffer. note: if the last data of the frame arrives in bdma tx buffer, the data transfer from the bdma tx buffer to the mac txfifo starts immediately, regardless of the level of these bits. [7] tx byte swapping (btxbswap) use to prevent disorder of byte sequence when memory operate on big-endian format and byte unit access. if this bit is set, the transferring byte is swapped. (b3,b2,b1,b0) (b0,b1,b2,b3) [8] reserved not applicable. [9] ? factorial test bit [10] bdma tx enable (btxen) when the tx enable bit is set to ?1?, the bdma tx block is enabled. even if this bit is disabled, buffer data will be moved to the mac txfifo until the bdma txbuff underflows. this bit is automatically cleared when the bdma is not the owner. note: the bdmatxdptr register must be assigned before this bit is set. [11] bdma tx reset (btxrs) set this bit to ?1? to reset the bdma tx block. [31:12] reserved ethernet controller S3C2500B 7- 16 7.4.1.2 buffered dma receive control register table 7-6. bdma rxcon register register address r/w description rest value bdmarxcona 0xf00a0004 r/w buffered dma receive control register 0x00000000 bdmarxconb 0xf00c0004 r/w buffered dma receive control register 0x00000000 table 7-7. bdma receive control register description bit number bit name description [3:0] bdma rx number of buffer descriptor (brxnbd) you can select number of buffer descriptor. 0000 = 2 0 , 0001 = 2 1 , 0010 = 2 2 ,?.., 11xx = 2 12 [5:4] bdma rx word alignment (brxwa) the rx word alignment bits determine how many bytes are invalid in the first word of each data frame. these invalid bytes are inserted when the word is assembled by the bdma. ?00? = no invalid bytes, ?01? = 1 invalid byte, ?10? = 2 invalid bytes, and ?11? = 3 invalid bytes. [6] reserved not applicable. [7] rx byte swapping (brxbswap) use to prevent disorder of byte sequence when memory operate on big-endian format and byte unit access. if this bit is set, the reception byte is swapped. (b3,b2,b1,b0) -> (b0,b1,b2,b3) [8] reserved not applicable. [9] ? factorial test bits [10] bdma rx enable (brxen) when the rx enable bit is set to ?1?, the bdma rx block is enabled. even if this bit is disabled, buffer data will be moved to the bdma rxbuff until the mac rxfifo underflows. this bit is automatically disabled when the bdma is not the owner. note: the buffer descriptor start address pointer must be assigned before this bit is set. [11] bdma rx reset (brxrs) set this bit to ?1? to reset the bdma rx block. [31:12] reserved S3C2500B ethernet c ontroller 7- 17 7.4.1.3 bdma transmit buffer descriptor start address register table 7-8. bdmatxdptr register registers address r/w description reset value bdmatxdptra 0xf00a0008 r/w bdma tx buffer descriptor base register 0x00000000 bdmatxdptrb 0xf00c0008 r/w bdma tx buffer descriptor base register 0x00000000 table 7-9. bdma transmit buffer descriptor start address register description bit number bit name description [31:0] bdma transmit buffer descriptor start address the bdma transmit buffer descriptor start address register contains the address of the first buffer descriptor on the frame to be sent. 7.4.1.4 bdma receive buffer descriptor start address register table 7-10. bdmarxdptr register registers address r/w description reset value bdmarxdptra 0xf00a000c r/w bdma rx buffer descriptor base register 0x00000000 bdmarxdptrb 0xf00c000c r/w bdma rx buffer descriptor base register 0x00000000 table 7-11. bdma receive buffer descriptor start address register description bit number bit name description [31:0] bdma receive buffer descriptor start address the bdma receive buffer descriptor start address register contains the address of the first buffer descriptor on the frame to be saved. ethernet controller S3C2500B 7- 18 7.4.1.5 bdma transmit buffer descriptor counter table 7-12. btxbdcnt register registers address r/w description reset value btxbdcnta 0xf00a0010 r/w bdma tx buffer descriptor counter of current pointer 0x00000000 btxbdcntb 0xf00c0010 r/w bdma tx buffer descriptor counter of current pointer 0x00000000 table 7-13. bdma transmit buffer descriptor counter bit number bit name description [11:0] bdma tx buffer descriptor counter the maximum counter value is dependent on the btxnbd of the bdmatxcon register. buffer descriptor current address = bdmatxdptr + (btxbdcnt<<3) 7.4.1.6 bdma receive buffer descriptor counter table 7-14. brxbdcnt register registers address r/w description reset value brxbdcnta 0xf00a0014 r/w bdma rx buffer descriptor counter of current pointer 0x00000000 brxbdcntb 0xf00c0014 r/w bdma rx buffer descriptor counter of current pointer 0x00000000 table 7-15. bdma receive buffer descriptor counter bit number bit name description [11:0] bdma rx buffer descriptor counter the maximum counter value is dependent on the btxnbd of the bdmatxcon register. buffer descriptor current address = bdmarxdptr + (brxbdcnt<<3) S3C2500B ethernet c ontroller 7- 19 7.4.1.7 bdma/mac transmit interrupt enable register table 7-16. bmtxinten register registers address r/w description reset value bmtxintena 0xf00a0018 r/w bdma/mac tx interrupt enable 0x00000000 bmtxintenb 0xf00c0018 r/w bdma/mac tx interrupt enable 0x00000000 table 7-17. bdma/mac transmit interrupt enable register description bit number bit name description [0] enable mac tx excessive collision (excollie) this bit enables excoll interrupt. [1] enable mac tx underflow (underflowie) this bit enables underflow interrupt. [2] enable mac tx deferral (defererrie) this bit enables defererr interrupt. [3] enable mac tx no carrier (nocarrie) this bit enables nocarr interrupt. [4] enable mac tx late collision (latecollie) this bit enables latecoll interrupt. [5] enable mac tx transmit parity (txparerrie) this bit enables txparerr interrupt. [6] enable mac tx completion (txcompie) this bit enables txcomp interrupt. [15:7] reserved not applicable. [16] tx complete to send control frame interrupt enable (txcfcompie) this bit enable txcfcomp interrupt. [17] bdma tx not owner interrupt enable (btxnoie) this bit enables btxno interrupt. [18] bdma tx buffer empty interrupt enable (btxemptyie) this bit enables btxempty interrupt [31:19] reserved not applicable. ethernet controller S3C2500B 7- 20 7.4.1.8 bdma/mac transmit interrupt status register table 7-18. bmtxstat register registers address r/w description reset value bmtxstata 0xf00a0020 r/w bdma/mac tx interrupt status register 0x00000000 bmtxstatb 0xf00c0020 r/w bdma/mac tx interrupt status register 0x00000000 table 7-19. bdma/mac transmit interrupt status register description bit number bit name description [0] excessive collision (excoll) this bit is set when collision occurred 16 times consecutively. in this case, the frame transmission is aborted. if this bit is the cause of the interrupt, mtxen/btxen/mreset bit should be cleared for the re-transmission of the current frame. [1] underflow this bit is set if the mac txfifo becomes empty during the frame transmission. [2] deferral error (defererr) this bit is set when mac doesn't run the transmission process from tx_en falling to 6,071 nibble times or 24,284 bit times. [3] no carrier (nocarr) this bit is set if no carrier sense is detected during the transmission frame. [4] late collision (latecoll) this bit is set if a collision occurs after 512 bit times (or 64 byte times). [5] transmit parity error (txparerr) this bit is set if a parity error is detected in the mac txfifo. [6] tx completion (txcomp) this bit is set when the transmission always is completed with normal or abnormal status. [15:7] reserved not applicable. [16] tx complete to send control frame (txcfcomp) this bit is set each time the mac sends a complete control frame. [17] bdma tx not owner (btxno) this bit is set when bdma is not owner and the transmission process is stop. [18] bdma txbuff empty (btxempty) this bit is set when the bdma txbuff is empty. [31:19] reserved not applicable. S3C2500B ethernet c ontroller 7- 21 7.4.1.9 bdma/mac receive interrupt enable register table 7-20. bmrxinten register registers address r/w description reset value bmrxintena 0xf00a001c r/w bdma/mac rx interrupt enable register 0x00000000 bmrxintenb 0xf00c001c r/w bdma/mac rx interrupt enable register 0x00000000 table 7-21. bdma/mac receive interrupt enable register description bit number bit name description [0] enable mac rx missed roll (missrollie) this bit enables missroll interrupt. [1] enable mac rx alignment (alignerrie) this bit enables alignerr interrupt [2] enable mac rx crc error (crcerrie) this bit enables crcerr interrupt. [3] enable mac rx overflow (overflowie) this bit enables overflow interrupt. [4] enable mac rx long error (longerrie) this bit enables longerr interrupt. [5] enable mac rx receive parity (rxparerrie) this bit enables rxparerr interrupt. [6] ? factorial test bit [15:7] reserved not applicable. [16] enable bdma rx done for every received frames (brxdoneie) this bit enables brxdone interrupt. [17] enable bdma rx not owner interrupt (brxnoie) this bit enables brxno interrupt. [18] enable bdma rx maximum size over interrupt (brxmsoie) this bit enables brxmso interrupt. [19] enable bdma rx buffer(brxbuff) overflow interrupt(brxfullie) this bit enables brxfull interrupt. [20] enable bdma rx early notification interrupt (brxearlyie) this bit enables brxearly interrupt. [31:21] reserved not applicable. ethernet controller S3C2500B 7- 22 7.4.1.10 bdma/mac receive interrupt status register table 7-22. bmrxstat register registers address r/w description reset value bmrxstata 0xf00a0024 r/w bdma/mac rx interrupt status register 0x00000000 bmrxstatb 0xf00c0024 r/w bdma/mac rx interrupt status register 0x00000000 table 7-23. bdma/mac receive interrupt status register description bit number bit name description [0] missed roll (missroll) this bit is set when the missed error counter rolls over. whenever this bit is set, the misscnt register should be read to clear this bit. writing by arm doesn?t affect the rx interrupt. [1] alignment error (alignerr) this bit is set if the frame length in bits is not a multiple of eight and the crc is invalid. for the mac rx control mode of mignorecrc, this bit is not set. [2] crc error (crcerr) this bit is set if the crc at the end of frame did not match the computed value, or else the phy asserted rx_er during frame reception. [3] overflow error (overflow) this bit is set if the mac rxfifo was full when it needed to store a received byte. [4] long error (longerr) this bit is set if the mac received a frame longer than 1518 bytes. (it is not set if the long enable bit in the receive control register, macrxcon, is set.) [5] parity error (rxparerr) this bit is set if a parity error is detected in the mac rxfifo. [6] ? factorial test bit [15:7] reserved not applicable. [16] bdma rx done in every received frames (brxdone) this bit is set each time the bdma receiver moves one received data frame to memory. this bit must be cleared for the next frame interrupt generation. [17] bdma rx not owner (brxno) this bit is set when bdma is not the owner and the reception process is stop. [18] bdma rx maximum size over (brxmso) this bit is set when the value of received frame size is larger than one of the rx frame maximum size. [19] bdma rxbuff full (brxfull) this bit is set when the bdma rxbuff is in the full-flag state. [20] early notification (brxearly) this bit is set when the bdma moves the length/ether-type field of the current frame to the external memory. [21] one more frame data in bdma rxbuff (brxfrf), read-only this bit is set whenever an additional data frame is received in the bdma receive buffer. [26:22] number of frames in brxbuff (brxnfr), read-only these bits appear number of frames in brxbuff. [31:27] reserved not applicable S3C2500B ethernet c ontroller 7- 23 7.4.1.11 bdma receive frame size register table 7-24. bdmarxlen register registers address r/w description reset value bdmarxlena 0xf00a0028 r/w receive frame size undefined bdmarxlenb 0xf00c0028 r/w receive frame size undefined table 7-25. bdma receive frame size register description bit number bit name description [11:0] bdma rx buffer size (brxbs) this register value specifies the buffer size allocated to each buffer descriptor. thus, for an incoming frame larger than the brxbs, multiple buffer descriptors are used for the frame reception. note: brxbs value has to keep multiples of 16 in byte unit. for long packet reception larger than 1518 bytes, the brxbs should be at least 4 bytes larger than the brxmfs or less than 1518 bytes for the reception with a single or multiple buffer descriptor, respectively. [15:12] reserved not applicable [27:16] bdma maximum rx frame size (brxmfs) this register value controls how many bytes per frame can be saved to memory. if the received frame size exceeds these values, an error condition is reported. note: brxmfs value has to keep multiples of 16 in byte unit. [31:28] reserved not applicable ethernet controller S3C2500B 7- 24 7.4.2 mac relative special register 7.4.2.1 mac transmit control frame status the transmit control frame status register, cftxstat provides the status of a mac control frame as it is sent to a remote station. this operation is controlled by the msdpause bit in the transmit control register, mactxcon. it is the responsibility of the bdma engine to read this register and to generate an interrupt to notify the system that the transmission of a mac control packet has been completed. table 7-26. cftxstat register registers address r/w description reset value cftxstata 0xf00a0030 r transmit control frame status 0x00000000 cftxstatb 0xf00c0030 r transmit control frame status 0x00000000 table 7-27. transmit control frame register description bit number bit name description [15:0] mactxstat[15:0] a 16-bit value indicating the status of a mac control packet as it is sent to a remote station. read by the bdma engine. S3C2500B ethernet c ontroller 7- 25 7.4.2.2 mac control register the mac control register provides global control and status information for the mac. the mlink10 bit is a status bit. all other bits are mac control bits. mac control register settings affect both transmission and reception. after a reset is complete, the mac controller clears the reset bit. not all phys support full-duplex operation. (setting the mac loopback bit overrides the full-duplex bit.) also, some 10m-b/s phys may interpret the loop 10 bit to control different functions, and manipulate the link10 bit to indicate a different status condition. table 7-28. maccon register registers address r/w description reset value maccona 0xf00b0000 r/w mac control 0x00000000 macconb 0xf00d0000 r/w mac control 0x00000000 table 7-29. mac control register description bit number bit name description [0] halt request (mhaltreq) set this bit to stop data frame transmission and reception as soon as tx/rx of any current frames has been completed. [1] halt immediate (mhaltimm) set this bit to immediately stop all transmission and reception. [2] software reset (mreset) set this bit to reset all mac control and status register and mac state machines. this bit is automatically cleared. [3] full-duplex if the phy chip advertising full-duplex, set this bit. in this case, collision does not detected. [4] mac loopback (mloopback) set this bit to cause transmission signals to be presented as input to the receive circuit without leaving the controller. [5] reserved not applicable [6] mii-off use this bit to select the connection mode. if this bit is set to one, 10m-bits/s interface will select the 10m-bits/s endec. otherwise, the mii will be selected. [7] loop 10 mb/s (mloop10) if this bit is set, the loop_10 external signal is asserted to the 10m-b/s endec. [11:8] reserved not applicable. [12] mdc-off clear this bit to enable the mdc clock generation for power management. if it is set to one, the mdc clock generation is disabled. [14:13] reserved not applicable. [15] link status 10 mb/s (mlink10), read-only this bit value is read as a buffered signal on the link 10 pin. [31:16] reserved not applicable. ethernet controller S3C2500B 7- 26 7.4.2.3 cam control register the three acceptance bits (mstation, mgroup, and mbroad) in the cam control register are used to override the address comparison mode by the compare enable bit(mcompen). by setting the cam control register, it is possible to accept frames with all types of destination addresses. the three types of destination address are as follows: ? broadcast address: defined as ff-ff-ff-ff-ff-ff. ? unicast (station) address: addresses with an even first byte. for example, 00-ff-ff-ff-ff-ff. ? multicast (group) address: addresses with an odd first byte, but not the broadcast address. for example, 01- 00-00-00-00-00. cam comparison mode : mcompen = '1', mnegcam = '0' the cam controller compares the destination address of the incoming frame with the cam addresses enabled by the cam enable (camen) register. the controller accepts only the frames with the matched destination addresses. negative cam comparison mode : mcompen = '1', mnegcam = '1' the address comparison is same as the cam comparison mode. but, the cam controller rejects the frames with the matched destination addresses and accepts frames with the address outside the cam address enabled. no cam comparison mode : mcompen = '0' the cam controller accepts frames with all types of destination addresses. table 7-30. camcon register registers address r/w description reset value camcona 0xf00b0004 r/w cam control 0x00000000 camconb 0xf00d0004 r/w cam control 0x00000000 table 7-31. cam control register description bit number bit name description [0] station accept (mstation) set this bit to accept unicast (i.e. station) frames. [1] group accept (mgroup) set this bit to accept multicast (i.e. group) frames. [2] broadcast accept (mbroad) set this bit to accept broadcast frames. [3] negative cam (mnegcam) set this bit to enable the negative cam comparison mode. [4] compare enable (mcompen) set this bit to enable the cam comparison mode. [31:5] reserved not applicable. S3C2500B ethernet c ontroller 7- 27 7.4.2.4 mac transmit control register table 7-32. mactxcon register registers address r/w description reset value mactxcona 0xf00b0008 r/w transmit control 0x00000000 mactxconb 0xf00d0008 r/w transmit control 0x00000000 table 7-33. mac transmit control register description bit number bit name description [0] transmit enable (mtxen) set this bit to enable transmission. to stop transmission immediately, clear the transmit enable bit to '0'. [1] transmit halt request (mtxhalt) set this bit to halt the transmission after completing the transmission of any current frame. [2] suppress padding (mnopad) set this bit not to generate pad bytes for frames of less than 64 bytes. [3] suppress crc (mnocrc) set this bit to suppress addition of a crc at the end of a frame. [4] fast back-off (mfback) set this bit to use faster back-off times for testing. [5] no defer (mnodef) set this bit to disable the defer counter. (the defer counter keeps counting until the carrier sense (crs) bit is turned off.) [6] send pause (msdpause) set this bit to send a pause command or other mac control frame. the send pause bit is automatically cleared when a complete mac control frame has been transmitted. writing a '0' to this register bit has no effect. [7] mii 10m-b/s sqe test mode enable (msqen) set this bit to enable mii 10m-b/s sqe test mode. [31:8] reserved not applicable. ethernet controller S3C2500B 7- 28 7.4.2.5 mac transmit status register a transmission status flag is set in the transmit status register, mactxstat, whenever the corresponding event occurs. in addition, an interrupt is generated if the corresponding enable bit in the transmit control register is set. a mac txfifo parity error sets txparerr, and also clears mtxen, if the interrupt is enabled. table 7-34. mactxstat register registers address r/w description reset value mactxstata 0xf00b000c r/w transmit status 0x00000000 mactxstatb 0xf00d000c r/w transmit status 0x00000000 table 7-35. mac transmit status register description bit number bit name description [7:0] ? these bits are equivalent to the bmtxstat.7-0 [11:8] transmission collision count (mcollcnt) this 4-bit value is the count of collisions that occurred while successfully transmitting the frame. [12] transmission deferred (mtxdefer) this bit is set if transmission of a frame was deferred because of a delay during transmission. [13] signal quality error (sqeerr) according to the ieee802.3 specification, the sqe signal reports the status of the pma (mau or transceiver) operation to the mac layer. after transmission is complete and 1.6 ms has elapsed, a collision detection signal is issued for 1.5 ms to the mac layer. this signal is called the sqe test signal. the mac sets this bit if this signal is not reported within the ifg time of 6.4ms. [14] transmission halted (mtxhalted) this bit is set if the mtxen bit is cleared or the mhaltimm bit is set [15] paused (mpaused) this bit is set if transmission of frame was delayed due to a pause being received. [31:16] reserved not applicable. S3C2500B ethernet c ontroller 7- 29 7.4.2.6 mac receive control register table 7-36. macrxcon register registers offset r/w description reset value macrxcona 0xf00b0010 r/w receive control 0x00000000 macrxconb 0xf00d0010 r/w receive control 0x00000000 table 7-37. mac receive control register description bit number bit name description [0] receive enable (mrxen) set this bit to '1' to enable mac receive operation. if '0', stop reception immediately. [1] receive halt request (mrxhalt) set this bit to halt reception after completing the reception of any current frame. [2] long enable (mlongen) set this bit to receive frames with lengths greater than 1518 bytes. [3] short enable (mshorten) set this bit to receive frames with lengths less than 64 bytes. [4] strip crc value (mstripcrc) set this bit to check the crc, and then strip it from the message. [5] pass control frame (mpassctl) set this bit to enable the passing of control frames to a mac client. [6] ignore crc value (mignorecrc) set this bit to disable crc value checking. [31:7] reserved not applicable. ethernet controller S3C2500B 7- 30 7.4.2.7 mac receive status register a receive status flag is set in the mac receive status register, macrxstat, whenever the corresponding event occurs. when a status flag is set, it remains set until another packet arrives, or until software writes a ?1? to the flag to clear the status bit. if the corresponding interrupt enable bit in the receive control register is set, an interrupt is generated whenever a status flag is set. a mac receive parity error sets rxparerr, and also clears the mrxen bit (if an interrupt is enabled). table 7-38. macrxstat register registers address r/w description reset value macrxstata 0xf00b0014 r/w receive status 0x00000000 macrxstatb 0xf00d0014 r/w receive status 0x00000000 table 7-39. mac receive status register description bit number bit name description [7:0] ? these bits are equal to the bmrxstat.7-0 [8] short frame error (mrxshort) this bit is set if the frame was received with short frame. [9] receive 10-mb/s status (mrx10stat) this bit is set to '1' if the frame was received over the 7-wire interface or to '0' if the frame was received over the mii. [10] reception halted (mrxhalted) this bit is set if the mrxen bit is cleared or the mhaltimm bit is set. [11] control frame received (mctlrecd) this bit is set if the frame received is a mac control frame (type = 0x8808), if the cam recognizes the frame address, and if the frame length is 64 bytes. [31:12] reserved not applicable. S3C2500B ethernet c ontroller 7- 31 7.4.2.8 mac station management data register table 7-40. stadata register registers address r/w description reset value stadataa 0xf00b0018 r/w station management data 0x00000000 stadatab 0xf00d0018 r/w station management data 0x00000000 table 7-41. station management register description bit number bit name description [15:0] station management data. this register contains a 16-bit data value for the station management function. ethernet controller S3C2500B 7- 32 7.4.2.9 mac station management data control and address register the mac controller provides support for reading and writing station management data to the phy. setting options in station management registers does not affect the controller. some phys may not support the option to suppress preambles after the first operation. table 7-42. stacon register registers address r/w description reset value stacona 0xf00b001c r/w station management control and address 0x00006000 staconb 0xf00d001c r/w station management control and address 0x00006000 table 7-43. stacon register description bit number bit name description [4:0] phy register address (mphyregaddr) a 5-bit address, contained in the phy, of the register to be read or written. [9:5] phy address (mphyaddr) the 5-bit address of the phy device to be read or written. [10] write (mphywrite) to initiate a write operation, set this bit to '1'. for a read operation, clear it to '0'. [11] busy bit (mphybusy) to start a read or write operation, set this bit to '1'. the mac controller clears the busy bit automatically when the operation is completed. [12] reserved not applicable [15:13] mdc clock rate (mmdcrate) controls the mdc period. the default value is '011'. mdc period = mmdcrate 4 + 32 example) mmdcrate = 011, mdc period = 44 x (1/system clock) [31:16] reserved not applicable. S3C2500B ethernet c ontroller 7- 33 7.4.2.10 cam enable register the camen register indicates which cam entries are valid, using a direct comparison mode. up to 21 entries, numbered 0 through 20, may be active, depending on the cam size. if the cam is smaller than 21 entries, the higher bits are ignored. table 7-44. camen register registers address r/w description reset value camena 0xf00b0028 r/w cam enable 0x00000000 camenb 0xf00d0028 r/w cam enable 0x00000000 table 7-45. cam enable register description bit number bit name description [20:0] cam enable set the bits in this 21-bit value to selectively enable cam locations 20 through 0. to disable a cam location, clear the appropriate bit. [31:21] reserved not applicable. ethernet controller S3C2500B 7- 34 7.4.2.11 mac missed error count register the value in the missed error count register, misscnt, indicates the number of frames that were discarded due to various type of errors. together with status information on frames transmitted and received, the missed error count register and the two pause count registers provide the information required for station management. reading the missed error counter register clears the register. it is then the responsibility of software to maintain a global count with more bits of precision. the counter rolls over from 0x7fff to 0x8000 and sets the corresponding bit in the mac control register. it also generates an interrupt if the corresponding interrupt enable bit is set. if station management software wants more frequent interrupts, you can set the missed error count register to a value closer to the rollover value of 0x7fff. for example, setting a register to 0x7f00 would generate an interrupt when the count value reaches 256 occurrences. table 7-46. misscnt register registers address r/w description reset value misscnta 0xf00b003c r(clr)/w missed error count 0x00000000 misscntb 0xf00d003c r(clr)/w missed error count 0x00000000 table 7-47. missed error count register description bit number bit name description [15:0] missed error count (misserrcnt) the number of valid packets rejected by the mac unit because of mac rxfifo overflows, parity errors, or because the mrxen bit was cleared. this count does not include the number of packets rejected by the cam. [31:16] reserved not applicable. S3C2500B ethernet c ontroller 7- 35 7.4.2.12 mac received pause count register the received pause count register, pzcnt, stores the current value of the 16-bit received pause counter. table 7-48. pzcnt register registers address r/w description reset value pzcnta 0xf00b0040 r pause count 0x00000000 pzcntb 0xf00d0040 r pause count 0x00000000 table 7-49. received pause count register description bit number bit name description [15:0] pause count received the count value indicates the number of time slots the transmitter was paused due to the receipt of control pause operation frames from the mac. 7.4.2.13 mac remote pause count register table 7-50. rmpzcnt register registers address r/w description reset value rmpzcnta 0xf00b0044 r remote pause count 0x00000000 rmpzcntb 0xf00d0044 r remote pause count 0x00000000 table 7-51. remote pause count register description bit number bit name description [15:0] remote pause count the count value indicates the number of time slots that a remote mac was paused as a result of its sending control pause operation frames. ethernet controller S3C2500B 7- 36 7.4.2.14 content addressable memory (cam) register there are 21 cam entries for the destination address and the pause control frame. for the destination address cam value, one destination address consists of 6 bytes. using the 32-word space (32 4 bytes), you can therefore maintain up to 21 separate destination addresses. you use cam entries 0, 1, and 18 to send pause control frames. to send a pause control frame, you write the cam0 entry with the destination address, the cam1 entry with the source address, and the cam 18 entry with length/type, opcode, and operand. you then set the send pause bit in the mac transmit control register. table 7-52. cam register registers address r/w description reset value cama 0xf00b0080- 0xf00b00fc r/w cam content (32-word) undefined camb 0xf00d0080- 0xf00d00fc r/w cam content (32-word) undefined table 7-55. content address memory (cam) register description bit number bit name description [31:0] cam content the cpu uses the cam content register as data for destination address. to activate the cam function, you must set the appropriate enable bits in cam enable register. S3C2500B ethernet c ontroller 7- 37 7.5 ethernet operations 7.5.1 mac frame format table 7-2 lists the eight fields in a standard (ieee 802.3/ethernet frame). table 7-53. mac frame format description field name field size description preamble 7-byte the bits in each preamble byte are 10101010, transmitted from left to right. start frame delimiter (sfd) 1-byte the sfd bits are 10101011, transmitted from left to right. destination address 6-byte the destination address can be an individual address or a multicast (or broadcast) address. source address 6-byte the mac does not interpret the source address bytes. however, to qualify as a valid station address, the first bit transmitted (the lsb of the first byte) must be a ' 0 ' . length or type 2-byte the mac treats length fields greater than 1500-byte as type fields. byte values less than or equal to 1500 indicate the number of logical link control (llc) data bytes in the data field. the mac transmits the high-order byte first. logical link control (llc) data 46 to 1500-byte data bytes used for logical link control. pad 0 to 46-byte if the llc data is less than 46-byte long, the mac transmits pad bytes of all zeros. frame check sequence (fcs) 4-byte the fcs field contains a 16-bit error detection code that is computed as a function of all fields except the preamble, the sfd, and the fcs itself. the fcs - 32 polynomial function is as follows: ' x 32 + x 26 + x 23 +x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x 1 + 1 ' . ethernet controller S3C2500B 7- 38 packet (encoded on the medium) added by transmitter, stripped by receiver data frame (sent by user) added by transmitter optionaly stripped by receiver preamble s f d destination address source address length or type llc data pad fcs 4-byte 0 to 46- byte 46 to 1500 -byte 2-byte 6-byte 6-byte 1 7-bit llc header llc information field dsap ssap ctrl ip/x.25/...... snap dsap ssap ctrl oui pid ip/x.25/...... 1-byte 1-byte 1-byte 3-byte 2-byte dsap = destination service access point ctrl = control field oui = origanizationally unique identifier sfd = starting frame delimiter ssap = source service access point snap = subnetwork access protocol pid = protocol identifier llc = logical lick control fcs = frame check sequence or data frame (delivered to user) figure 7-5. fields of an ieee802.3/ethernet frame 7.5.1.1 options that affect the standard mac frame ? there are a number of factors and options that can affect the standard mac frame, as described in table 7- 2: ? some phys may deliver a longer or shorter preamble. ? short frame mode permits llc data fields with less than 46 bytes. options are available to suppress padding and to support the reception of short frames. ? long frame mode supports llc data fields with more than 1500 bytes. an option is also available to support to reception of long frames. ? 'no crc' mode suppresses the appending of a crc field. ? 'ignore crc' mode allows the reception of frames without valid crc fields. S3C2500B ethernet c ontroller 7- 39 7.5.1.2 destination address format bit 0 of the destination address is an address type designation bit. it identifies the address as either an individual or a group address. group addresses are sometimes called 'multicast' addresses and individual addresses are called 'unicast' addresses. the broadcast address is a special group address in the special hex format: ff-ff- ff-ff-ff-ff. bit 1 of the destination address distinguishes between locally or globally administered addresses. for globally administered or universal (u) addresses, the bit value is '0'. if an address is to be assigned locally, you must set this bit to '1'. for the broadcast address, this bit must also be set to '1'. 7.5.1.3 transmitting a frame to transmit a frame, the transmit enable bit in the transmit control register must be set and the transmit halt request bit must be zero. in addition, the halt immediate and halt request bits in the mac control register must be '0'. these conditions are normally set after any bdma controller initialization has occurred. the transmission state machine starts transmitting the data in the fifo, and will retain the first 64 bytes until after this station has acquired the net. at that time, the transmitter requests more data and transmits it until the signalling the end of data to be transmitted. the transmitter appends the calculated crc to the end of the frame. a frame transmit operation can be subdivided into two operations, 1) mii transmit interface operation, and 2) bdma/ mac transmit interface operation. 7.5.1.3.1. mii transmit operation the transmitter block consists of three state machines: the gap-ok state machine, the back-off state machine, and the main transmission state machine. the gap-ok state machine the gap-ok state machine tracks and counts the inter-gap timing between the frames. when not operating in full- duplex mode, it counts 96 bit times from the de-assertion of the carrier sense (crs) signal. if there is any traffic within the first 64 bit times, the gap-ok state machine reset itself and starts counting from zero. if there is any traffic in the last 1/3 of the inter-frame gap, the gap-ok state machine continues counting. following a successful transmission, a gap-ok is sent at the end of the next 96-bit times, regardless of the network traffic. in full-duplex mode, the gap-ok state machine starts counting at the end of the transmission and the gap-ok signal is sent at the end of the 96 bit times, regardless of the network traffic. ethernet controller S3C2500B 7- 40 the back-off state machine the back-off state machine implements the back-off and retry algorithm of the 802.3 csma/cd. when a collision is detected, the main transmission state machine starts the back-off state machine s counters and waits for the back-off time (including zero) to elapse. this time is a multiple of 512 bit times that elapse before the frame that caused the collision is re-transmitted. each time there is a collision (for one single frame), the back-off state machine increments an internal retry attempt counter. an 11-bit pseudo random number generator outputs a random number by selecting a subset of the value of the generator at any time. the subset is incremented by one bit for each subsequent attempt. this implementation is represented by the following equation: 0 =< random integer(r) < 2 k k = min (n, back-off limit (= 10)) 'r' is the number of slot times the mac must wait in case of a collision, and 'n' is the number of retry attempts. for example, after the first collision, 'n' is 1 and 'r' is a random number between 0 and 1. the pseudo random generator in this case is one-bit wide and gives a random number of either 0 or 1. after the second attempt, 'r' is a random number between 0 and 3. therefore, the state machine looks at the two least-significant bits of the random generator (n = 2), which gives a value between 0 and 3. attempt_count>= max_attempt? assemble mac frame carrier sense==on? wait for interframe gap (96-bit time), start tx with preamble + sfd collision detected? done. complete tx wait for back-off time: (=slot time x r), k = minimum (n, back-off limit (=10)) 0<=n ethernet controller S3C2500B 7- 42 tx_clk tx_en txd [3:0] crs p1 p2 p3 p4 p5 p6 p7 p8 col j1 j2 j3 j4 figure 7-8. timing for transmission with collision in preamble 7.5.1.3.2. bdma/mac interface operation for transmission the bdi transmit operation is a simple fifo mechanism. the bdma engine stores data to be transmitted, and the transmission state machine empties it when the mac successfully acquires the net. note that the two time domains intersect at the fifo controller. the writing and reading of data is asynchronous and on different clocks. reading is driven by either a 25mhz or a 2.5mhz tx_clk. writing is driven by system clock, which is asynchronous to tx_clk. after a reset, the mtxfifo is empty. to enable the transmission, the system must set the transmit enable bit in the mactxcon register. in addition, eight bytes of data must be present in the mtxfifo. the bdma engine can start stuffing data into the mtxfifo and then enable the transmit bit. (or it can enable the transmit bit first and then start stuffing data into the mtxfifo) the transmitting operation can only start if both of these conditions are met. 7.5.1.4. receiving a frame the receiver block, when enabled, constantly monitors a data stream coming either from the mii or, if in loop- back mode, from the transmitter block. the mii supplies from zero to seven bytes of preamble, followed by the start frame delimiter (sfd). the receiver block checks that the first nibbles received are preamble, and then looks for the sfd (10101011) in the first 8-byte. if it does not detect the sfd by then, it treats the frame as a fragment and discards it. the first nibble of destination address follows the sfd, lsb first. when it has received a byte, the receiver block generates parity, stores the byte with its parity in the mrxfifo. it combines subsequent nibbles into bytes and stores them in the fifo. S3C2500B ethernet c ontroller 7- 43 7.5.1.4.1. receive frame timing with/without error if, during frame reception, both rx_dv and rx_er are asserted, a crc error is reported for the current packet. as each nibble of the destination address is received, the cam block attempts to recognize it. after receiving the last destination address nibble, if the cam block rejects the packet, the receive block asserts the rx_toss signal, and discards any bytes not yet removed from the receive fifo that came from the current packet. if this operation leaves the fifo empty, it drops rx_rdy. figure 7-6 shows the mii receive data timing without error. the rx_dv signal, which entered the mii from the pcs layer, will be on when the pcs layer recovers the rx_clk from the receive bit stream and delivers the nibble data on rxd[3:0] data line. the rx_dv signal must be on before the starting frame delimiter (sfd) is received. when the rx_dv signal is on, the preamble and sfd parts of the frame header are delivered to mii, synchronized with the 25mhz rx_clk. (the carrier sense (crs) signal was turned on during receive frame.) as its response to the rx_er signal, the mii immediately inserts an alternative data bit stream into the receive data stream. as a result, the mac discards this received error frame using the fcs. ~ ~ ~ ~ ~ ~ ~ ~ rx_clk rx_dv rxd [3:0] crs rx_er ~ ~ ~ ~ preamble sfd da sfd figure 7-9. receiving frame without error ~ ~ ~ ~ ~ ~ ~ ~ rx_clk rx_dv rxd [3:0] crs rx_er ~ ~ ~ ~ preamble sfd da sfd figure 7-10. receiving frame with error ethernet controller S3C2500B 7- 44 7.5.1.4.2 bdma/mac interface operation for reception the bdi receive operation is a simple fifo mechanism. the bdma engine stores received data to mrxfifo, and the bdma rxbuff controller empties it when the bdma rxbuff has enough space left. note that the two time domains intersect at the fifo controller. the writing and reading of data is asynchronous and on different clocks. reading is driven by system clock, which is asynchronous to rx_clk. writing is driven by either a 25mhz or a 2.5mhz rx_clk. after a reset, the mrxfifo is empty. to enable the reception, the system must set the receive enable bit in the macrxcon register. if the bdma engine cannot transfer the received data to the brxbuff and memory due to the disabled bdma or the inaccessibility on the system bus, the mac rxfifo may overflow. carrier sense== on carrier sense = on, after detection sfd, store byte-stream in in fifo recognize address? move the byte stream in the fifo to the receive buffer memory frame too short ? frame too long? valid fcs ? interrput cpu for handing the frame mac drive software (software jobs for typical lan cards) discard the frame report error status yes no check ethertype or length field disassemble frame signal to upper layer figure 7-11. csma/cd receive operation S3C2500B ethernet c ontroller 7- 45 7.5.2 the mii station manager the mdio (management data input/output) signal line is the transmission and reception path for control/status information for the station management entity, sta. the sta controls and reads the current operating status of the phy layer. the speed of transmit and receive operations is determined by the management data clock, mdc. the frame structure of the sta that writes command to control registers, or which reads the status register of a phy device, is shown table 7-54. the phy address is defined as the identification (id) value of the various phy devices that may be connected to a single mac. register addresses can contain the id value for up to 32 types of phy registers. turn-around bits are used to regulate the turn-around time of the transmit/receive direction between the sta and a phy device. so that the sta can read the set value of a phy device register, it must transmit the frame data, up to a specific register address, to the phy device. during the write time (which is an undirected transmission), the sta transmits a stream of turn-around bits. as a result, by transmitting a write or read message to a phy device through the mdio, the sta can issue a request to set the operation or to read the operation status. as its response this message, the phy device resets itself, sets loop-back mode, selects active/non-active auto- negotiation process, separates the phy and mii electrically, and determines whether or not to activate the collision detection process. when it receives a read command, the phy reports the type of phy device such as 100 base-t4, fdx 100 base-x, hdx 100base-x, 10m-b/s fdx, or 10m-b/s hdx. table 7-54. sta frame structure description preamble start of frame operation code phy address register address turnaround data idle write (command) 11111111 (32-bit) 01 01 (write) 5-bit 5-bit 10 (2-bit) 16-bit (register value) z read (status) 11111111 (32-bit) 01 10 (read) 5-bit 5-bit z0 16-bit (register value) z direction: sta to phy direction: phy to sta ethernet controller S3C2500B 7- 46 7.5.3 full-duplex pause operations flow control can be done by the use of control frames. the receive logic in the flow control block recognise a mac control frame as follows: ? the current specification for full-duplex flow control specifies a special destination address for the pause operation frame. in order for the mac to receive frames that contain this special destination address, the address must be programmed in one of the cam entries. this cam entry must then be enabled, and the cam activated. some cam entries are also used when generating a flow control frame using the msdpause bit in the mactxcon register. ? the length/type field is a 2-octet field that shall contain the hexadecimal value: 88-08. the frame length must be at least 64 bytes, including crc. the crc must be valid, and the frame must contain a valid pause opcode and a parameter (pause period) field. if the length/type field does not have the special value specified for mac control frames, the mac takes no action, and the frame is treated as a normal frame. if the frame is marked as a mac control frame and pass-through is enabled, it is passed to the software drivers. user can set the control bit in the mac control register to generate a full-duplex pause operation or other mac control functions, even if the transmitter itself is paused. the command and status registers initiate the sending of a mac control frame, enable and disable mac control functions, and read the values of the flow control counters. (minframesize-160)/8 octets destination address source address length/type mac control parameters reserved (transmitted as zeroes) 6 octets 6 octets 2 octets 2 octets lsb msb b0 b7 mac control opcode octers within frame transmitted top-to-bottom bits within frame transmitted left-to-right figure 7-12. mac control frame format S3C2500B ethernet c ontroller 7- 47 7.5.3.1 transmit pause operation to enable a full-duplex pause operation, the special broadcast address for mac control frames must be programmed into the cam, and the corresponding cam enable bit set. the special broadcast address can be a cam location. to optimize the utilization cam entries, you can specify a preference for specific cam locations. this feature is described below. the mac receive circuit recognizes a full-duplex pause operation when the following conditions are met: ? the length/ type field has the special value for mac control frames, 0x8808. ? the cam detects the correcting destination address. ? the length of the frame is 64 bytes. ? the receiving crc is correct. ? the operation field specifies a pause operation. when a full-duplex pause operation is recognized, the mac receive circuit loads the operand value into the pause count register. it then signals both the mac and the bdma engine that the pause should begin at the end of the current frame, if any. the pause circuit maintains the pause counter, and decrements it to zero. it does this before it signals the end of the pause operation, and before allowing the transmit circuit to resume its operation. if a second full-duplex pause operation is recognized while the first operation is in effect, the pause counter is reset with the current operand value. note that a count value of zero may cause pre-mature termination of a pause operation that is already in progress. 7.5.3.2 remote pause operation to send a remote pause operation, follow these steps: 1. program cam location 0 with the destination address. 2. program cam location 1 with the source address. 3. program cam location 18 with length/type field, opcode, and operand. 4. program the 2 bytes that follow the operand with 0 000h. 5. program the three double words that follow cam location 18 with zeros. 6. write the transmit control register to set the msdpause bit. the destination address and source address are commonly used as the special broadcast address for mac control frames and the local station address, respectively. to support future uses of mac control frames, these values are fully programmable in the flow control 100/10m-bps ethernet mac. when the remote pause operation is completed, the transmit status is written to the transmit control frame status register. the bdma engine is responsible for providing an interrupt enable control. ethernet controller S3C2500B 7- 48 7.5.4 error signalling the error/abnormal operation flags asserted by the mac are arranged into transmit and receive groups. these flag groups are located either in the transmit status register (mactxstat) or the receive status register (macrxstat). a missed frame error counter is included for system network management purposes. normally, software does not have enough direct control to examine the status registers directly. therefore, the bdma engine must store the values in system memory so that they can be examined by software. 7.5.4.1 reporting of transmission errors a transmit operation terminates when the entire frame (preamble, sfd, data, and crc) has been successfully transmitted through the mii without a collision. in addition, the transmitter block detects and reports both the internal and the network errors. under the following conditions, the transmit operation will be aborted (in most cases). parity error the 8-bit of data incoming through the bdma has an optional parity bit. a parity bit also protects each byte in the mtxfifo. if a parity error occurs, the transmission is aborted. a detected parity error sets the txparerr bit in the bmtxstat register. mtxfifo underflow the 80-byte mtxfifo can handle a system latency of 640 bit times. an underflow of the mtxfifo during transmission indicates that the system cannot keep up with the demand of the mac, and the transmission is aborted. no carrier the carrier sense signal (crs) is monitored from the beginning of the start of frame delimiter (sfd) to the last byte transmitted. a nocarr indicates that crs was never present during transmission (a possible network problem), but the transmission will not be aborted. note that during loop-back mode, the mac is disconnected from the network, and a 'no crs' will not be detected. excessive collision error whenever the mac encounters a collision during transmit, it will back off, update the 'attempt counter' and retry the transmission later on. when the attempt counter reaches 16 (16 attempts that all resulted in a collision), the transmission is aborted. this indicates a network problem. late collision error normally, the mac would detect a collision (if one occurs) within the first 64 bytes of data that are transmitted, including the preamble and sfd. if a collision occurs after this time frame, a possible network problem is indicated. the error is reported to the transmission state machine, but the transmission is not aborted. instead, it performs a back-off, as usual. excessive deferral error during the first attempt to send a frame, the mac may have to defer the transmission because the network is busy. if this deferral time is longer than 32k-bit times, the transmission is aborted. excessive deferral errors indicate a possible network problem. S3C2500B ethernet c ontroller 7- 49 7.5.4.2 reporting of reception errors when it detects a start of frame delimiter (sfd), the mac starts putting data it has received from the mii into the mrxfifo. it also checks for internal errors (mrxfifo overruns) while reception is in progress. when the reception process is completed, the mac checks for external errors, such as frame alignment, length, crc, and frame too long. the following is a description of the types of errors that may occur during a receive operation: parity error a parity bit protects each byte in the mrxfifo. if a parity error occurs, it is reported to the mac. a detected parity error sets the rxparerr bit in the bmrxstat register. frame alignment error after receiving a frame, the receiver block checks that the incoming frame (including crc) was correctly framed on an 8-bit boundary. if it is not and if the crc is invalid, data has been disrupted through the network, and the receive block reports a frame alignment error. a crc error is also reported. crc error after receiving a frame, the receiver block checks the crc for validity, and reports a crc error if it is invalid. the phy informs the mac if it detects a medium error (such as a coding violation) by asserting the input pin rx_er. when the mac sees rx_er asserted, it sets crcerr bit of the bmrxstat register. frame too long the receiver block checks the length of the incoming frame at the end of reception (including crc, but excluding preamble and sfd). if the length is longer than the maximum frame size of 1518 bytes, the receiver block reports receiving a ?long frame? , unless long frame mode is enabled. the receiver can detect network-related errors such as crc, frame alignment, and length errors. it can also detect these types of errors in the following combinations: ? crc errors only ? frame alignment and crc errors only ? length and crc errors only ? frame alignment, length, and crc errors mrxfifo full during the reception, the incoming data are put into the mrxfifo temporarily before they are transferred to the system memory. if the mrxfifo is filled up because of excessive system latency or for other reasons, the receiver block sets the overrun bit in the bmrxstat register. mii error the phy informs the mac if it detects a medium error (such as a coding violation) by asserting the input pin rx_er. when the mac sees rx_er asserted, it sets crcerr bit of the receive status register. ethernet controller S3C2500B 7- 50 7.5.5 timing parameters for mii transactions the timing diagrams in this section conform to the guidelines described in the "draft supplement to ansi/ieee std. 802.3, section 22.3, signal characteristics." output valid tx_clk txd[3:0] tx_en 4.9ns min 28ns min figure 7-13. timing relationship of transmission signals at mii rx_clk rxd[3:0] rx_dv th: 5ns ts: 3ns input valid figure 7-14. timing relationship of reception signals at mii mdc mdio input valid ts: 15ns figure 7-15. mdio sourced by phy mdc mdio output valid th: 13ns figure 7-16. mdio sourced by sta S3C2500B hdlc controller 8- 1 8 hdlc controller 8.1 overview the S3C2500B has three high-level data link controllers (hdlcs) to support three-channel serial communica- tions. the hdlc module supports a cpu/data link interface that conforms to the synchronous data link control (sdlc) and high-level data link control (hdlc) standards. in addition, the following function blocks are integrated into the hdlc module: ? three-channel dma engine for tx/rx ? support buffer descriptors per frame ? digital phase-locked loop (dpll) block ? baud rate generator (brg) hdlc controller s3c 2500b 8- 2 8.2 features important features of the S3C2500B hdlc block are as follows: protocol features: ? flag detection and synchronization ? zero insertion and deletion ? idle detection and transmission ? fcs encoding and detection (16-bit) ? abort detection and transmission four address station registers and one mask register for address search mode selectable crc/no-crc mode automatic crc generator preset digital pll block for clock recovery baud rate generator nrz/nrzi/fm/manchester data formats for tx/rx ? loop-back and auto-echo mode ? tx and rx clock inversion tx and rx fifos with 8-word (8 x 32-bit) depth selectable 1-word or 4-word data transfer mode for tx/rx data alignment logic endian translation programmable interrupts modem interface hardware flow control buffer descriptor for tx / rx three-channel dma controller ? three channels for htxfifo and hrxfifo ? single or 4-word (4 x 32-bit) burst transfer mode ? maximum frame size allows for up to 64k bytes up to 10 mbps full-duplex operation using an external/internal clock hdlc frame length based on octets S3C2500B hdlc controller 8- 3 8.3 function descriptions figure 8-1 shows the hdlc module's function blocks. these function blocks are described in detail in the following sections. dma controlller address bus arbiter/ controller address data control tx fifo (8 words) flag/abort/idle generateor and transmitter receive shift register rx fifo (8 words) fcs generator zero insertion flag/abort/idle detection zero delection loop dpll dplloutr dplloutt rxd txc txd autoecho rxc mclk2 (= 66 mhz) brgout1 brgout2 word system bus hdlc control and status registers fcs checker encoder decoder remote serial port brg figure 8-1. hdlc module block diagram hdlc controller s3c 2500b 8- 4 8.3.1 hdlc frame format the hdlc transmits and receives data (address, control, information and crc field) in a standard format called a frame. all frames start with an opening flag (beginning of flag, bof, 7eh) and end with a closing flag (end of flag, eof, 7eh). between the opening and the closing flags, a frame contains an address (a) field, a control (c) field, an information (i) field (optional), and a frame check sequence (fcs) field (see table 8-1). table 8-1. hdlc data frame format opening flag address field control field information field frame check sequence field closing flag 01111110 8 bits per byte 8 bits per byte 8 bits per byte; variable length 16 bits 01111110 note : the address field can be extended up to four bytes using a optional software control setting. 8.3.1.1 flag (f) a flag is a unique binary pattern (01111110) that is used to delimit hdlc frames. this pattern is generated internally by the transmitter. an opening flag starts a frame and a closing flag ends the frame. opening flags and closing flags are automatically appended to frames. a single flag pattern can optionally serve as both the closing flag of one frame and the opening flag of the next one. this feature is controlled by the double-flag (ff), single-flag (f), or frame separator selection bit (the txsdfl bit in the hcon register). 8.3.1.2 order of bit transmission address field, control field, and information field bytes are transferred between the cpu and the hdlc module in parallel over the data bus. these bytes are transmitted and received lsb first. the 16-bit frame check sequence (fcs) field is, however, transmitted and received msb first. S3C2500B hdlc controller 8- 5 8.3.1.3 address (a) field the eight bits that follow the opening flag are called address (a) field. the address field are expendable. to extend this address byte, simply user-defined address write to the station address register. to check address byte against the incoming data, have to be used the mask register. if match occurred, the frame's data including address and crc(16-bit) into the hrxfifo and then moved to system memory. if it is not matched, simply discarded. S3C2500B allows up to 32-bits address. for instance, sdlc and lapb use an 8-bit address. lapd further divides its 16-bit address into different fields to specify various access points one piece of equipment. some hdlc-type protocol allows for extended addressing beyond 16-bit. 8.3.1.4 control (c) field the eight bits that follow the address field are called the control (link control, c) field. the S3C2500B hdlc module treats the control field in the same way as the information field. that is, it passes the eight bits to the cpu or memory during reception. the cpu is responsible for how the control field is handled and what happens to it. 8.3.1.5 information (i) field the information (i) field follows the control (c) field and precedes the frame check sequence (fcs) field. the information field contains the data to be transferred. not every frame, however, must actually contain information data. the word length of the i-field is eight bits in the S3C2500B hdlc module. and its total length can be extended by 8 bits until terminated by the fcs field and the closing flag. 8.3.1.6 frame check sequence (fcs) field the 16 bits that precede the closing flag comprise the frame check sequence (fcs) field. the fcs field contains the cyclic redundancy check character, crcc. the polynomial x16 + x12 + x5 + 1 is used both for the transmitter and the receiver. both the transmitter and the receiver polynomial registers are all initialized to 1 prior to calculating of the fcs. the transmitter calculates the frame check sequence of all address bits, control bits, and information fields. it then transmits the complement of the resulting remainder as the fcs value. the receiver performs a similar calculation for all address, control, and information bits, as well as for all the fcs fields received. it then compares the result to f0b8h. when a match occurs, the frame valid (rxfv) status bit is set to '1'. when the result does not match, the receiver sets the crc error bit (rxcrce) to '1'. the transmitter and the receiver automatically perform these fcs generation, transmission and checking functions. the S3C2500B hdlc module also supports no crc operation mode. in no crc mode, transmitter does not append fcs to the end of data and the receiver also does not check fcs. in this mode, the data preceding the closing flag is transferred to the hrxfifo. in crc mode, the fcs field is transferred to the hrxfifo. hdlc controller s3c 2500b 8- 6 8.4 protocol features 8.4.1 invalid frame a valid frame must have at least the a, c, and fcs fields between its opening and closing flags. even if no-crc mode is set, the frame size should not be less than 32 bits. there are three invalid frame conditions: ? short frame: a frame that contains less than 25 bits between flags. short frames are ignored. ? invalid frame: a frame with 25 bits or more, having a crc compare error or non- byte-aligned. invalid frames are transferred to the hrxfifo, then the invalid frame error flag (rxcrce, rxno in the status register) is set to indicate that an invalid frame has been received. ? aborted frame: a frame aborted by the reception of an abort sequence is handled as an invalid frame. 8.4.2 zero insertion and zero deletion the zero insertion and zero deletion feature, which allows the content of a frame to be transparent, is handled automatically by the hdlc module. while the transmitter inserts a binary '0' following any sequence of five 1s within a frame, the receiver deletes a binary '0' that follows a sequence of five 1s within a frame. 8.4.3 abort the function of early termination of a data link is called an abort. the transmitter aborts a frame by sending at least eight consecutive 1s immediately after the abort transmitter control bit (txabt in hcon) is set to '1'. (setting this control bit automatically clears the htxfifo.) the abort sequence can be extended up to (at least) 16 consecutive 1s by setting the abort extend control bit (txabtext in hcon) to '1'. this feature is useful for forcing the mark idle state. the receiver interprets the reception of seven or more consecutive 1s as an abort. the receiver responds the abort received as follows: ? an abort in an 'out of frame' condition: an abort has no meaning during the idle or the time fill ? an abort 'in frame' after less than 25 bits are received after an opening flag: under this condition, no field of the aborted frame is transferred to the hrxfifo. the hdlc module clears the aborted frame data in the receiver and flag synchronization. the aborted reception is indicated in the status register. ? an abort 'in frame' after 25 bits or more are received after an opening flag: in this condition, some fields of the aborted frame may be transferred to the hrxfifo. the abort status is set in the status register and the data of the aborted frame in the hrxfifo is cleared. flag synchronization is also cleared and the dma operation for receiving is aborted too. 8.4.4 idle and time fill when the transmitter is not transmitting a frame, it is in an idle state. the transmitter signals that it has entered an idle state in one of the following two ways: 1) by transmitting a continuous series of flag patterns (time fill), or 2) by transmitting a stream of consecutive 1s (mark idle). the flags and mark idle are not transferred to the hrxfifo. the flag or mark idle selection bit (txflag in hcon) controls this function: when txflag is '0', mark idle is selected; when txflagidle is '1', the time fill method is selected. S3C2500B hdlc controller 8- 7 8.4.5 fifo structure in both transmit and receive directions, 32-byte (8 word) deep fifos are provided for the intermediate storage of data between the serial interface and the cpu interface. 8.4.6 two-channel dma engine the hdlc module has a two-channel dma engine for tx/rx fifos. the dma tx channel programming and the rx channel programming are described in the transmitter and receiver operation sections, respectively. 8.4.7 baud rate generator the hdlc module contains a programmable baud rate generator(brg). the brg register contains a 16-bit time constant register, a 12-bit down counter for time constant value, two control bit to divide 16, and another two control bits to divide 16 or 32. a clock diagram of the brg is shown in figure 8-2. at a start-up, the flip-flop on the output is set in a high state, the value in the time constant register is loaded into the counter, and the counter starts counting down. the output of the baud rate generator may toggle upon reaching zero, the value in the time constant register is loaded into the counter, and the process is repeated. the time constant may be changed any time, but the new value does not take effect until the next load of the counter. the output of the baud rate generator may be used as either the transmit clock, the receive clock, or both. it can also drive the digital phase-locked loop. if the receive or transmit clock is not programmed to come from the txc pin, the output of the baud rate generator may be echoed out via the txc pin. the following formula relates the time constant to the baud rate where mclk2 or rxc is the baud rate generator input frequency in hz. brg generates 2 output signals, brgout1, brgout2, for transmit/receive clocks and the dpll input clock. brgout1 = (mclk2 or rxc) / (cnt0 + 1) / (16 cnt1 ) brgout2 = brgout1 / (1 or 16 or 32 according to cnt2 value of the hbrgtc) (mclk2 = mclk/2) brgout2 12-bit counter cnt0 brgclk divide by 1 or 16 cnt1 divide by 1 or 16 or 32 cnt2 rxc mclk2 brgout1 cnt0: hbrgtc [15:4] cnt1: hbrgtc [3:2] cnt2: hbrgtc [1:0] brgclk: hmode [19] figure 8-2. baud rate generator block diagram hdlc controller s3c 2500b 8- 8 the example in the following table assumes a 66mhz clock from mclk2, a 24.576mhz clock from rxc, showing a time constant for a number of commonly used baud rates. table 8-2. baud rate example of hdlc baud rate mclk2 = 66 mhz r c = 24.576 mhz (brgout2) cnt0 cnt1 cnt2 freq. dev. (%) cnt0 cnt1 cnt2 freq. dev. (%) 400k 164 0 0 400000 0.0 60 0 0 402885 0.7 600k 109 0 0 600000 0.0 40 0 0 599415 -0.1 800k 82 0 0 795181 -0.6 30 0 0 792774 -0.9 1000k 65 0 0 1000000 0.0 24 0 0 983040 -1.7 4000k 16 0 0 3882353 -2.9 5 0 0 4096000 2.4 6000k 10 0 0 6000000 0.0 3 0 0 6144000 2.4 8000k 7 0 0 8250000 3.1 2 0 0 8192000 2.4 10000k 6 0 0 9428571 -5.7 1 0 0 12288000 22.9 S3C2500B hdlc controller 8- 9 8.4.8 digital phase-locked loop (dpll) the hdlc module contains a digital phase-locked loop (dpll) function to recover clock information from a data stream with nrzi or fm encoding. the dpll is driven by a clock that is normally 32 (nrzi) or 16 (fm) times the data rate. the dpll uses this clock, along with the data stream, to construct the clock. this clock may then be used as the receive clock, the transmit clock, or both. figure 8-3 shows a block diagram of the digital phase-locked loop. it consists of a 5-bit counter, an edge detector and a pair of output decoders. edge detector count modifier decoder receive clock dplloutr hmode[18:16] 5-bit counter decoder transmit clock dplloutt rxd txc rxc mclk2 brgout1 brgout2 figure 8-3. dpll block diagram 8.4.9 clock usage method note: brgclk = hmode [19] dpllclk = hmode [18:16] txclk = hmode [22:20] rxclk = hmode [26:24] dplloutt dpllortr dpll txc rxc mclk2 brgout1 brgout2 dpllclk brgout1 brgout2 baud rate generator brgclk rxc mclk2 transmit data transmit clock txc rxc dplloutt brgout1 brgout2 transmitter txclk receive data receive clock txc rxc dplloutr brgout1 brgout2 receiver rxclk figure 8-4. clock usage method diagram hdlc controller s3c 2500b 8- 10 in the nrz/nrzi mode, the dpll source clock must be 32 times the data rates. in this mode, the transmit and receive clock outputs of the dpll are identical, and the clocks are phased so that the receiver samples the data in the middle of the bit cell. the dpll counts the 32x clock using an internal 5-bit counter. as the 32x clock is counted, the dpll searches the incoming data stream for edges (either positive or negative transition). the output of dpll is high while the dpll is waiting for an edge in the incoming data stream. when it detects a transition, the dpll starts the clock recovery operation. the first sampling edge of the dpll occurs at the counter value of 16 after the first edge is detected in the incoming data stream. the second sampling edge occurs following the next 16. when the transition of incoming data occurs at a count value other than 16, the dpll adjusts its clock outputs during the next 0 to 31 counting cycle by extending or shortening its count by one, which effectively moves the edge of the clock sampling the receive data closer to the center of the bit cell. the adding or subtracting of a count of 1 will produce a phase jitter of 5.63 degrees on the output. because the dpll uses both edges of the incoming signal for its clock source comparison, the mark-space ratio (50%) of the incoming signal must not deviate more than 1.5% of its baud rate if proper locking is to occur. in the fm mode, the dpll clock must be 16 times the data rate. the 5-bit counter in the dpll counts from 0 to 31, so the dpll makes two sampling clocks during the 0 to 31 counting cycle. the dpll output is low while the dpll is waiting for an edge in the incoming data stream. the first edge the dpll detects is assumed to be a valid clock edge. from this point, the dpll begins to generate output clocks. in this mode, the transmit clock output of the dpll lags the receive clock outputs by 90 degrees to make the transmit and receive bit cell boundaries the same, because the receiver must sample the fm data at a one- quarter and three-quarters bit time. you can program the 32x clock for the dpll to originate from one of the rxc input pins, from the txc pin, or from the baud rate generator output. you can also program the dpll output to be "echoed out" of the hdlc module over the txc pin(if the txc pin is not being used as an input). during idle time, you can set the txprmb in hcon to send the special pattern required for a remote dpll to lock the phase. in this case, the content of the hprmb register is sent repeatedly. the length of preamble is determined by txpl bit in hmode[10:8]. it is noticed that the frequency of the receive clock (rxc) should be slower than half of the internal system clock i.e., mclk/2. otherwise, the data transfer from receive fifo to memory could be lost. S3C2500B hdlc controller 8- 11 8.5 hdlc operational description the following sections describe the operation of the hdlc module. 8.5.1 hdlc initialization a power-on or reset operation initializes the hdlc module and forces it into the reset state. after a reset, the cpu must write a minimum set of registers, as well as any options set, based on the features and operating modes required. first, the configuration of the serial port and the clock mode must be defined. these settings include the following: ? data format select ? brg clock select ? dpll clock select ? transmit clock select ? receive clock select ? brg/dpll enable to use internal clock you must also set the clock for various components before each component is enabled. additional registers may also have to be programmed, depending on the features you select. all settings for the hdlc mode register, hmode, and the hdlc control register, hcon, must be programmed before the hdlc is enabled. to enable the hdlc module, you must write a '1' to the receiver enable bit and/or the transmitter enable bit. during normal operation, you can disable the receiver or the transmitter by writing a '0' to the rxen or txen bit, respectively. you can disable the receiver and hrxfifo or the transmitter and htxfifo by writing a '1' to the rxrs or txrs bit, respectively. hdlc controller s3c 2500b 8- 12 8.5.2 hdlc data encoding/decoding data encoding is utilized to allow the transmission of clock and data information over the same medium. this saves the need to transmit clocks and data over a separate medium as would normally be required for synchronous data. the hdlc provides four different data encoding methods, selected by bits in hcon1[18:16]. an example of these four encoding methods is shown in figure 8-5. 1 1 0 0 1 0 data nrz nrzi fm1 (biphase mark) fm0 (biphase space) manchester nrz, nrzi type txclock data rxclock fm0/fm1/ manchester type txclock data rxclock bit cell level: high = 1 low = 0 no change = 1 change = 0 bit center transition: transition = 1 no transition = 0 no transition = 1 transition = 0 high low = 1 low high = 0 figure 8-5. data encoding methods and timing diagrams S3C2500B hdlc controller 8- 13 8.5.3 hdlc data setup and hold timing with clock you can see the timing of txd and rxd in terms of txc and rxc hdlc clock in figure 8-6. table 8-3. hdlc data setup and hold timing symbol condition min typ max unit ttxdf txd falling edge delay time 9.82 10.66 ns trxdf txd falling edge delay time 1.0 ns 40ns 9.82ns 10.66ns 0.2ns 1.0ns txc txd rxc rxd figure 8-6. hdlc data setup and timing diagrams tx data will be sent with delayed 9.82nsec to 10.66nsec from the falling edge of tx clock. the data of the red period should not be changed. that is, the rxd should be stable from 0.2nsec to 1.0nsec after rxc rising edge. (it does not allow data transition during this period) the rxc will be rx(receiver) clock through rx clock selection part with some delay. and this rxc delay is larger then rxd delay. in figure 8-6, the dotted-clock is real internal rx clock used by the receiver. therefore, there should not be transit in rx data to avoid setup or hold violation. hdlc controller s3c 2500b 8- 14 8.5.4 hdlc transmitter operation the htxfifo register cannot be pre-loaded when the transmitter is disabled. after the hdlc tx is enabled, the flag or mark idle control bit (txflag in hcon) is used to select either the mark idle state (inactive idle) or the flag 'time fill' (active idle) state. this active or inactive idle state will continue until data is loaded into the htxfifo. the content of the hprmb register can be sent out by setting the txprmb in hcon for the remote dpll before the data is loaded into the htxfifo. the length of preamble to be transmitted is determined by txpl bits in hmode. the availability of data in the htxfifo is indicated by the htxfifo available bit (txfa in hstat) under the control of the 4-word transfer mode bit (tx4wd in hcon). when you select 1-word transfer mode (not 4-word select mode), one word can be loaded into the htxfifo (assuming the txfa bit is set to '1'). when you select 4-word transfer mode, four successive words can be transferred to the fifo if the txfa bit is set to '1'. the ncts (clear-to-send) input, nrts (request-to-send), and ndcd (data-carrier-detect) are provided for a modem or other hardware peripheral interface. in auto enable mode, ndcd becomes the receiver enable. however, the receiver enable bit must be set before the ndcd pin is used in this manner. the txfc status bit (in hstat) can cause an interrupt to be generated upon frame completion (this bit is set when there is no data in htxfifo and when the closing flag or an abort is transmitted). note you can use transmitter interrupt mode or transmitter dma mode for transmitting the frame. transmitter interrupt mode writes tx data to txfifo by cpu. transmitter dma mode writes tx data to txfifo by hdma. note if you use transmitter interrupt mode, then you must set the preamble, txnocrc, little-endian mode to hcon[23], hcon[26], and hmode[5]. if you use transmitter dma mode, then you must set the preamble, txnocrc, little-endian mode to transmit buffer descriptor. S3C2500B hdlc controller 8- 15 8.5.4.1 transmitter interrupt mode the first byte of a frame (the address field) should be written into the tx fifo at the 'frame continue' address. then, the transmission of the frame data starts automatically. the bytes of the frame continue to be written into the tx fifo as long as data is written to the 'frame continue' address. the hdlc logic keeps track of the field sequence within the frame. the frame is terminated when the last frame data is written to the tx fifo's 'frame terminate' address. the fcs field is automatically appended by hardware, along with a closing flag. data for a new frame can be loaded into the tx fifo immediately after the previous frame data, if txfa is '1'. the closing flag can serve as the opening flag of the next frame or separate opening and closing flags can be transmitted. if a new frame is not ready to be transmitted, a flag time fill or mark idle pattern is transmitted automatically. if the tx fifo becomes empty at any time during the frame transmission, an underrun occurs and the transmitter automatically terminates the frame by transmitting an abort. the underrun state is indicated when the transmitter underrun status bit (txu) is '1'. whenever you set the transmission abort control bit (txabt in hcon), the transmitter immediately aborts the frame (transmits at least eight consecutive 1s), clearing the tx fifo. if the transmission abort extension control bit (txabtext) is set at the time, an idle pattern (at least 16 consecutive 1s) is transmitted. an abort or idle in an out- of-frame condition can be useful to gain 8 or 16 bits of delay time between read and write operations. 8.5.4.2 transmitter dma mode to use dma operation without cpu intervention, you have to make tx buffer descriptor in advance. and set the dma tx buffer descriptor pointer(dmatxptr) register to the address of the first buffer descriptor, set the tx buffer descriptor maximum count (txbdmaxcnt) register which shows the maximum buffer descriptor counts, and then dma tx channel should be enabled. when tx underrun or cts lost condition occurs during dma operation, dma tx enable bit(hcon[6]) is cleared and dma tx operation is stopped. this situation is reported to system with dtxabt bit set(hstat[22]). in case of tx underrun, abort signal sent and then idle pattern is sent if txen bit is set. in case of cts lost, txd output goes high state as long as cts remains high level. hdlc controller s3c 2500b 8- 16 8.5.5 hdlc receiver operation the hdlc receiver is provided with data and a pre-synchronized clock by means of the rxd and the internal dpll clock, the txc pin, or the rxc pin. the data is a continuous stream of binary bits. one of the characteristics of this bit stream is that a maximum of five consecutive 1s can occur unless an abort, flag, or idle condition occurs. the receiver continuously searches (bit-by-bit) for flags and aborts. when a flag is detected, the receiver synchronizes the frame to the flag timing. if a series of flags is received, the receiver re-synchronizes the frame to each successive flag. if the frame is terminated because of a short frame condition (frame data is less than 32 bits after an opening flag), the frame is simply ignored. noise on the data input line (rxd) during time fill can cause this kind of invalid frame. the received data which is clocked by the external txc or rxc, or by an internal dpll or brg source enters a 56-bit or 32-bit shift register before it is transferred into the hrxfifo. synchronization is established when a flag is detected in the first eight locations of the shift register. when synchronization has been achieved, data is clocked through to the last byte location of the shift register where it is transferred into the hrxfifo. in 1-word transfer mode, when the hrxfifo available bit (rxfa) is '1', data is available at least in one-word. in 4-word transfer mode, the rxfa is '1' when data is available in the last four fifo register locations (registers 4, 5, 6, and 7). the ndcd input is provided for a modem or other hardware interface. if autoen bit in hcon[28] is set to '1', the receiver operation is dependent on the ndcd input level. otherwise, receiver operation is free of the ndcd input level.. 8.5.5.1 receiver interrupt mode whenever data is available in the hrxfifo, an interrupt is generated by rxfa (if the interrupt is enabled). the cpu reads the hdlc status register either in response to the interrupt request or in turn during a polling sequence. when the received data available bit(rxfa) is '1', the cpu can read the data from the hrxfifo. if the cpu reads normal data or address data from the hrxfifo, the rxfa bit is automatically cleared. in crc mode, the 16 bits preceding the closing flag are regarded as the fcs and checked by hardware, and they are transferred to the hrxfifo. also, in no crc mode, without the hardware checking, all data bits preceding the closing flag are transferred to the hrxfifo. when the closing flag is sent to the receiver, the frame is terminated. whatever data is present in the most significant byte of the receiver, the shift register is right justified and transferred to the hrxfifo. the frame boundary pointer, which is explained in the hrxfifo register section, is set simultaneously in the hrxfifo. when the last byte of the frame appears at the 1-word or 4-word boundary location of the hrxfifo, depending on the settings of the rx4wd control bit, the frame boundary pointer sets the frame valid status bit (if the frame is completed with no error) or the rxcrce status bit(if the frame was completed, but with a crc error). if the frame reception is completed, an rxcrce interrupt (for a frame error) or an rxfv interrupt (for normal state) is generated. at this point, the cpu can read the rx remaining bytes (rxrb) status bits to know how many bytes of this frame still remain in the hrxfifo. when you set the frame discontinue control bit (the incoming frame discard control bit) to '1', the receiver discards the current frame data without dropping the flag synchronization. you can use this feature to ignore a frame with a non-matched address. S3C2500B hdlc controller 8- 17 8.5.5.2 receiver dma mode to use dma operation without cpu intervention, you have to make rx buffer descriptor in advance. and set the dma rx buffer descriptor pointer(dmarxptr) register to the address of the first buffer descriptor, set the rx buffer descriptor maximum count (rxbdmaxcnt) register which shows the maximum buffer descriptor counts, and then dma rx channel should be enabled. 8.5.6 hardware flow control last txclock txd rts cts ~ ~ figure 8-7. ncts already asserted when ncts is active and there exists data to be transmitted in tx fifo, nrts enters low, allowing data transmission. at the beginning of the data is an open flag while at the end a closing flag. if the frame being transferred discontinues, nrts goes back to the high after the data transmission is completed. txclock txd rts cts data 14 - 22 cycles 5 - 13 cycles ~ ~ figure 8-8. cts lost during transmission when the condition of ncts is shifted from low to high, it is detected at the falling edge of tx clock, where nrts also goes high. for about 5 to 13 cycles after nrts enters high, the data transmission continues. nrts remains high for a maximum of 22 cycles and goes back to the low condition if there remains any data to be transmitted in htxfifo. if ncts is still high even when nrts went back to low, not the data in htxfifo but a mark idle pattern is transmitted when autoen bit set to one. hdlc controller s3c 2500b 8- 18 txclock txd rts cts data 5 - 12 cycles ~ ~ figure 8-9. cts delayed on if ncts remains still high for a while after nrts enters low to allow data transmission from htxfifo, the data transmission starts 5-12 cycles after ncts is shifted to low S3C2500B hdlc controller 8- 19 8.5.7 memory data structure the flow control to the hdlc controller uses two data structures to exchange control information and data. ? transmit buffer descriptor ? receive buffer descriptor each tx dma buffer descriptor has the following elements. ? buffer data pointer ? ownership bit ? control field for transmitter ? status field for tx ? transmit buffer length each rx dma buffer descriptor has the following elements. ? buffer data pointer ? ownership bit ? status field for rx ? accumulated received buffer length for a frame hdlc controller s3c 2500b 8- 20 8.5.8 data buffer descriptor rx bdma function is enabled by drxen bit(hcon[7]). when rx bdma is enabled, the bdma fetches the rx buffer data pointer and owner bit of the next word. then it checks the ownership of the buffer descriptor. if the owner bit is ?1?, then bdma owns the buffer descriptor, and bdma waits until rx. frame is received. if the entire frame is received successfully, the status bits in the receive buffer descriptor are set to indicate the received frame status. the ownership bit in the buffer descriptor pointer is cleared by the cpu which has the ownership and an interrupt may now be generated. after stores the states, the bdma fetches next buffer data pointer and owner bit of the next word. if the owner bit is ?0?(when bdma checks the owner of the buffer descriptor), then it has two options: ? skip to the next buffer descriptor when drxnstsk/dtxnstsk bit is '1'(not owner skip) ? generate an interrupt and halt the dma operation when drxstsk/dtxnstsk bit is '0'(not owner stop) you must set hbrxbdmaxcnt/hbtxbdmaxcnt register which shows the maximum buffer descriptor counts. and if all buffer descirptors are used by the received frames or by the transmitted frames, then first rx/tx buffer descritptor is fetched by the bdma. as bdma receives the data, the software sets the maximum frame length register. if the received data is longer than the value of the maximum frame length register, this frame is ignored and the flv bit is set. the software also sets the dma rx buffer descriptor pointer to point to a chain of buffer descriptors, all of which have their ownership bit. the dma controller can be started to set the dma rx enable bit in the control register. when a frame is received, it is moved into memory at the address specified by the dma rx data buffer pointer. if a frame is longer than the value of the rxbuf size register, then the next buffer descriptors are fetched to receive the frame. that is, to handle a frame, one or more buffer descriptors could be used. please note that no configurable offset or page boundary calculation is required. the received frame is moved to the buffer memory whose address is pointed to by the buffer data pointer until the end of frame, or until the length exceeds the maximum frame length configured.if the length exceeds the maximum frame length configured, the frame length violated bit is set. during transmission, the two-byte frame length at the tx buffer descriptor is moved to the dma internal tx register. after transmission, the tx status is saved in the tx buffer descriptor. after stores the status, the bdma controller fetches the next buffer descriptor and the owner bit and the control bits of the next word. when the dma tx buffer descriptor register points to the first buffer descriptor, the transmitter starts transmitting the frame data from the buffer memory to tx fifo. S3C2500B hdlc controller 8- 21 8.6 buffer descriptor 8.6.1 transmit buffer descriptor 31 15 0 buffer pointer o tx control bits buffer length 26 25 22 [31:0] buffer data pointer [15:0] buffer length tx control bits [16] preamble (p) 0 = no preamble 1 = preamble [17] txnocrc mode (n) 0 = crc mode 1 = no crc mode [18] little-endian mode (e) 0 = big-endian 1 = little-endian [19] last (l) 0 = this is not the last buffer in the frame 1 = this is the last buffer int the frame [20] buffer data pointer decrement (d) 0 = increment 1 = decrement [22:21] widget alignment control (wa) 00 = no invalid bytes 01 = 1 invalid bytes 10 = 2 invalid bytes 11 = 3 invalid bytes tx status bit these bit may be regarded as valid when the l bit (in tx control bit) is set [26] transmission completion (t) 0 = normal 1 = one frame completed [31]ownership (o) 0 = cpu 1 = dma 16 23 27 t figure 8-10. transmit buffer descriptor hdlc controller s3c 2500b 8- 22 8.6.2 receive buffer descriptor 31 15 0 buffer pointer o rx control bits buffer length 24 [31:0] buffer data pointer [15:0] buffer length rx status bits these bits may be regarded as valid when l bit(in rx status bit) is set [16] cd lost (cd) 0 = normal 1 = cd lost occurs [17] crc error (ce) 0 = normal 1 = crc error occurs to the frame received [18] non-octet aligned frame (no) 0 = normal 1 = non-octet aligned frame is received [19] overrun (ov) 0 = normal 1 = the received frame overruns [20] dpll two miss (dtm) 0 = normal 1 = dpll two miss clock occurs [21] rx abort (abt) 0 = normal 1 = the received frame aborted [22] first in frame (f) 0 = this buffer descriptor status is not the first to the frame 1 = this buffer descriptor status is the first to the frame [23] last in frame (l) 0 = this buffer descriptor status is not the last to the frame 1 = this buffer descriptor status is the last to the frame [24] frame length violation (flv) 0 = normal 1 = this received frame length exceeds the value of the maximum frame length register [31] ownership (o) 0 = cpu 1 = dma 23 16 figure 8-11. receive buffer descriptor S3C2500B hdlc controller 8- 23 rx buffer descriptor start address pointer buffer data pointer #1 status buffer length buffer data #1 unused buffer data #2 unused buffer data #n unused rx bufsize register value rx bufsize register value note: 1. buffer length is accumulated until the last bit is set in status. buffer data pointer indicates the buffer memory start address. 2. after hrxbdmaxcnt buffer descriptors used, the rx buffer descriptor address pointer points start address. buffer data pointer #2 status buffer length buffer data pointer #n status buffer length 0 31 hrxbdmaxcnt = #n . . . . . . . . . . . . figure 8-12. data structure of the receive data buffer hdlc controller s3c 2500b 8- 24 8.7 hdlc special registers the hdlc special registers are defined as read-only or write-only registers according to the direction of information flow. the addresses of these registers are shown in table 8-4 and 8-5. the transmitter fifo register can be accessed using two different addresses, the frame terminate address and the frame continue address. the functions of these addresses are discussed in detail in the fifo section below. table 8-4. hdlc channel a special registers registers address r/w description reset value hmodea 0 f0100000 r/w hdlc mode register 0 00000000 hcona 0 f0100004 r/w hdlc control register 0 00000000 hstata 0 f0100008 r/w hdlc status register 0 00000000 hintena 0 f010000c r/w hdlc interrupt enable register 0 00000000 htxfifoca (frame continue) 0 f0100010 w htxfifo frame continue register ? htxfifota (frame terminate) 0 f0100014 w htxfifo frame terminate register ? hrxfifoa 0 f0100018 r hrxfifo entry register 0 00000000 hbrgtca 0 f010001c r/w hdlc brg time constant register 0 00000000 hprmba 0 f0100020 r/w hdlc preamble register 0 00000000 hsar0a 0 f0100024 r/w hdlc station address 0 0 00000000 hsar1a 0 f0100028 r/w hdlc station address 1 0 00000000 hsar2a 0 f010002c r/w hdlc station address 2 0 00000000 hsar3a 0 f0100030 r/w hdlc station address 3 0 00000000 hmaska 0 f0100034 r/w hdlc mask register 0 00000000 hdmatxptra 0 f0100038 r/w dma tx buffer descriptor pointer 0 ffffffff hdmarxptra 0 f010003c r/w dma rx buffer descriptor pointer 0 ffffffff hmflra 0 f0100040 r/w maximum frame length register 0 xxxx0000 hrbsra 0 f0100044 r/w receive buffer size register 0 xxxx0000 hsynca 0xf0100048 r/w hdlc sync register 0 xxxxxx7e tcona 0xf010004c r/w transparent control register 0 xxxx0000 htxbdcnta 0 f01000c0 r tx buffer descriptor count register 0 xxxxx000 hrxbdcnta 0 f01000c4 r rx buffer descriptor count register 0 xxxxx000 htxmaxbdcnta 0 f01000c8 r/w tx buffer descriptor maximum count register 0 xxxxxfff hrxmaxbdcnta 0 f01000cc r/w rx buffer descriptor maximum count register 0 xxxxxfff S3C2500B hdlc controller 8- 25 table 8-5. hdlc channel b special registers registers address r/w description reset value hmodeb 0 f0110000 r/w hdlc mode register 0 00000000 hconb 0 f0110004 r/w hdlc control register 0 00000000 hstatb 0 f0110008 r/w hdlc status register 0 00000000 hintenb 0 f011000c r/w hdlc interrupt enable register 0 00000000 htxfifocb (frame continue) 0 f0110010 w htxfifo frame continue register ? htxfifotb (frame terminate) 0 f0110014 w htxfifo frame terminate register ? hrxfifob 0 f0110018 r hrxfifo entry register 0 00000000 hbrgtcb 0 f011001c r/w hdlc brg time constant register 0 00000000 hprmbb 0 f0110020 r/w hdlc preamble register 0 00000000 hsar0b 0 f0110024 r/w hdlc station address 0 0 00000000 hsar1b 0 f0110028 r/w hdlc station address 1 0 00000000 hsar2b 0 f011002c r/w hdlc station address 2 0 00000000 hsar3b 0 f0110030 r/w hdlc station address 3 0 00000000 hmaskb 0 f0110034 r/w hdlc mask register 0 00000000 hdmatxptrb 0 f0110038 r/w dma tx buffer descriptor pointer 0 ffffffff hdmarxptrb 0 f011003c r/w dma rx buffer descriptor pointer 0 ffffffff hmflrb 0 f0110040 r/w maximum frame length register 0 xxxx0000 hrbsrb 0 f0110044 r/w receive buffer size register 0 xxxx0000 hsyncb 0 f0110048 r/w hdlc sync register 0xxxxxxx7e tconb 0 f011004c r/w transparent control regsiter 0 xxxx0000 htxbdcntb 0 f01100c0 r tx buffer descriptor count register 0 xxxxx000 hrxbdcntb 0 f01100c4 r rx buffer descriptor count register 0 xxxxx000 htxmaxbdcntb 0 f01100c8 r/w tx buffer descriptor maximum count register 0 xxxxxfff hrxmaxbdcntb 0 f01100cc r/w rx buffer descriptor maximum count register 0 xxxxxfff hdlc controller s3c 2500b 8- 26 table 8-6. hdlc channel c special registers registers address r/w description reset value hmodec 0 f0120000 r/w hdlc mode register 0 00000000 hconc 0 f0120004 r/w hdlc control register 0 00000000 hstatc 0 f0120008 r/w hdlc status register 0 00000000 hintenc 0 f012000c r/w hdlc interrupt enable register 0 00000000 htxfifocc (frame continue) 0 f0120010 w htxfifo frame continue register ? htxfifotc (frame terminate) 0 f0120014 w htxfifo frame terminate register ? hrxfifoc 0 f0120018 r hrxfifo entry register 0 00000000 hbrgtcc 0 f012001c r/w hdlc brg time constant register 0 00000000 hprmbc 0 f0120020 r/w hdlc preamble register 0 00000000 hsar0c 0 f0120024 r/w hdlc station address 0 0 00000000 hsar1c 0 f0120028 r/w hdlc station address 1 0 00000000 hsar2c 0 f012002c r/w hdlc station address 2 0 00000000 hsar3c 0 f0120030 r/w hdlc station address 3 0 00000000 hmaskc 0 f0120034 r/w hdlc mask register 0 00000000 hdmatxptrc 0 f0120038 r/w dma tx buffer descriptor pointer 0 ffffffff hdmarxptrc 0 f012003c r/w dma rx buffer descriptor pointer 0 ffffffff hmflrc 0 f0120040 r/w maximum frame length register 0 xxxx0000 hrbsrc 0 f0120044 r/w receive buffer size register 0 xxxx0000 hsyncc 0 f0120048 r/w hdlc sync register 0 xxxxxx7e tconc 0 f012004c r/w transparent control register 0 xxxx0000 htxbdcntc 0 f01200c0 r tx buffer descriptor count register 0 xxxxx000 hrxbdcntc 0 f01200c4 r rx buffer descriptor count register 0 xxxxx000 htxbdmaxcntc 0 f01200c8 r/w tx buffer descriptor maximum count register 0 xxxxxfff hrxbdmaxcntc 0 f01200cc r/w rx buffer descriptor maximum count register 0 xxxxxfff S3C2500B hdlc controller 8- 27 8.7.1 hdlc global mode register table 8-7. hmodea, hmodeb, and hmodec register registers address r/w description reset value hmodea 0 f0100000 r/w hdlc mode register 0 00000000 hmodeb 0 f0110000 r/w hdlc mode register 0 00000000 hmodec 0 f0120000 r/w hdlc mode register 0 00000000 table 8-8. hmode register description bit number bit name description [0] multi-frame in htxfifo in dma operation (mff) if this bit is set, more than one frame can be loaded into htxfifo. in this case, the frame size may be less than the fifo size. [1] reserved not applicable. [2] rx clock inversion (rxcinv) if this bit set to '0', the receive clock samples the data at the rising edge. if this bit set to '1', the receive clock samples the data at the falling edge. [3] tx clock inversion (txcinv) if this bit set to '0', the transmit clock shifts the data at the falling edge. if this bit set to '1', the transmit clock shifts the data at the rising edge. [4] rx little-endian mode (rxlittle) this bit determines whether the data is in little- or big-endian format. hrxfifo is in little-endian. if this bit is set to '0', then the data on the system bus should be in big-endian. therefore the bytes will be swapped in big-endian. [5] tx little-endian mode (txlittle) this bit determines whether tx data is in little or big endian (txlittle) format. htxfifo is in little-endian. if this bit is set to '1', the data on the system bus is little endian. if this bit is set to '0', the data on the system bus is in big-endian. (that is, the data bytes are swapped to be little endian format.) it is used only by the transmitter interrupt mode, not by the transmitter dma mode. (see 8-14) [6] rx transparent mode (rxtrans) if this bit set to one, hdlc rx operates transparent mode. otherwise, operates hdlc mode [7] tx transparent mode (txtrans) if this bit set to one, hdlc rx operates transparent mode. otherwise, operates hdlc mode [10:8] tx preamble length (txpl) these bits determine the length of preamble to be sent before the opening flag when the txprmb bit is set in the control register. 000 1byte, 001 2bytes, ..., and 111 8bytes will be sent. [11] reserved not applicable hdlc controller s3c 2500b 8- 28 table 8-8. hmode register description (continued) bit number bit name description [14:12] data formats (df) when the df bits are '000', data is transmitted and received in the nrz data format. when df is '001', the nrzi (zero complement) data format is selected. df = '010' selects the fm0 data format, df = '011' the fm1 data format, and df = '100' the manchester data format. [15] rtr/rts mode select (rtrnrts) rtr, rts mode select bit. when rtrnrts is ?0?, the mode is rts(request to send), when rtrnrts is ?1?, the mode is rtr(received to ready). [18:16] dpll clock select (dpllclk) using this setting, you can configure the clock source for dpll to one of the following pins: txc, rxc, mclk2, brgout1, or brgout2. to select one of these pins, set the dpllclk bits to '000', '001', '010', '011', or '100', respectively. [19] brg clock select (brgclk) if this bit is '1', mclk2 is selected as the source clock for the baud rate generator (brg). if this bit is '0', the external clock at the rxc pin is selected as the brg source clock. [22:20] tx clock select (txclk) using this setting, you can configure the transmit clock source to one of the following pins: txc, rxc, dplloutt, brgout1, or brgout2. to select one of these pins, set the txclk bits to '000', '001', '010', '011', or '100', respectively. [26:24] rx clock select (rxclk) using this setting, you can configure the receive clock source to one of the following pins: txc, rxc, dplloutr, brgout1, or brgout2. to select one of these pins, set the rxclk bits to '000', '001', '010', '011', or '100', respectively. [30:28] txc output pin select (txcops) if you do not use the clock at the txc pin as the input clock(dpllclk, txclk, rxclk must not ?000? ), you can use the txc pin to monitor txclk, rxclk, brgout1, brgout2, dplloutt, and dplloutr. to select the clock you want to monitory, set the txcops to '000', '001', '010', '011', or '100', '101' respectively. [31] reserved not applicable. S3C2500B hdlc controller 8- 29 [0] muilt-frame in txfifo in dma operation (mff) 0 = single frame in txfifo 1 = multi frame in txfifo [1] reserved [2] rx clock inversion (rxcinv) 0 = rx clock rising 1 = rx clock falling [3] tx clock inversion (txcinv) 0 = tx clock falling 1 = tx clock rising [4] rx little-endian mode (rxlittle) 0 = the rx data on the system bus is in big-endian format. 1 = the rx data on the system bus is in little-endian format. [5] tx little-endian mode (txlittle) 0 = the tx data on the system bus is in big-endian format. 1 = the tx data on the system bus is in little-endian format. [6] rx transparent mode (rxtrans) 0 = the rx operates hdlc mode 1 = the rx operates transparent mode [7] tx transparent mode (txtrans) 0 = the tx operates hdlc mode 1 = the tx operates transparent mode [10:8] tx preamble length (txpl) 000 = 1 byte 100 = 5 byte 001 = 2 byte 101 = 6 byte 010 = 3 byte 110 = 7 byte 011 = 4 byte 111 = 8 byte [11] reserved [14:12] data format (df) 000 = nrz data format 001 = nrzi 010 = fm0 001 = fmi 100 = manchester 31 0 3 4 5 1 2 txc ops 30 28 27 26 23 22 20 19 15 14 10 24 18 16 12 11 8 7 6 rxclk txclk b r g c l k dpll clk df t x l i t t l e txpl r x l i t t l e t x c i n v r x c i n v m f f r t r n r t s t x t r a n s r x t r a n s [15] rtrnrts 0 = request to send 1 = receive to ready [18:16] dpll clock select (dpllclk) 000 = txc pin 001 = rxc pin 010 = mclk2 011 = brgout1 100 = brgout2 [19] brg clock select (brgclk) 0 = rxc pin is selected. 1 = mclk2 is selected. [22:20] tx clock select (txclk) 000 = txc pin 001 = rxc pin 010 = dplloutt 011 = brgout1 100 = brgout2 [26:24] rx clock select (rxclk) 000 = txc pin 001 = rxc pin 010 = dplloutt 011 = brgout1 100 = brgout2 [27] reserved [30:28] txc output pin select (txcops) this pin is used for output only when it is not used as an input clock for the dpll, txclk, or rxclk. 00 0 = tx clock 001 = rx clock 010 = brgout1 011 = brgout2 100 = dplloutt 101 = dplloutr [31] reserved figure 8-13. hmode register hdlc controller s3c 2500b 8- 30 8.7.2 hdlc control register table 8-9. hcona , hconb, and hconc register registers address r/w description reset value hcona 0 f0100004 r/w hdlc channel a control register 0x00000000 hconb 0 f0110004 r/w hdlc channel b control register 0x00000000 hconc 0 f0120004 r/w hdlc channel c control register 0x00000000 table 8-10. hcon register description bit number bit name description [0] tx reset (txrs) set this bit to '1' to reset the tx block. tx block comprises htxfifo and a transmitter block. [1] rx reset (rxrs) set this bit to '1' to reset the rx block. rx block comprises hrxfifo and a receiver block. [2] dma tx reset (dtxrs) set this bit to '1' to reset the dma tx block. [3] dma rx reset (drxrs) set this bit to '1' to reset the dma rx block. [4] tx enable (txen) when the txen bit is '0', the transmitter enters a disabled state and the line becomes high state. in this case, the transmitter block is cleared except for the htxfifo and the status bits associated with transmit operation are cleared. data cannot be loaded into the htxfifo. if this bit is set to '1', the idle pattern is sent continuously. in this case, the data can be loaded into htxfifo, and then sent. [5] rx enable (rxen) when the rxen bit is '0', the receiver enters a disabled state and can not detect the flag pattern, if any. in this case, receiver block is cleared except for the hrxfifo and the status bits associated with receiver operation are cleared. data cannot be received. if this bit is set to '1', the flag pattern is detected. in this case, the data received can be loaded into the hrxfifo, and moved to system memory. [6] dma tx enable (dtxen) the dtxen bit lets the hdlc tx operate on a bus system in dma mode. when dma tx is enabled, an interrupt request caused by txfa status is inhibited and the hdlc does not use the interrupt request to request a data transfer. dma tx monitors the htxfifo and fills the htxfifo. this bit is auto disabled when tx underrun occurs, or cts lost, or next buffer descriptor pointer reach null, or the owner bit is not dma mode when dtxstsk bit is set. if tx underrun occurs, dtxabt(in hstat) bit set, and abort signal sended. if cts lost occurs, dtxabt bit set and txd output goes high state as long as cts remains high level. S3C2500B hdlc controller 8- 31 table 8-10. hcon register description (continued) bit number bit name description [7] dma rx enable (drxen) the drxen bit lets the hdlc rx operate on a bus system in dma mode. when dma rx is enabled, an interrupt request caused by the rxfa status is inhibited, and the hdlc does not use the interrupt request to request a data transfer. dma rx monitors the hrxfifo and moves the data from the hrxfifo to memory. this bit is automatically disabled when the next buffer descriptor pointer becomes null, or the owner bit is not in dma mode when the dtxstsk bit is set. [8] dpll enable (dpllen) setting this bit enables the dpll, causing the dpll to enter search mode. in search mode, the dpll searches for a locking edge in the incoming data stream. after dpll is enabled (in nrzi mode for example), the dpll starts sampling immediately after the first edge is detected. (in fm mode, the dpll examines the clock edge of every other bit to decide what correction must be made to remain in sync.) if the dpll does not detect an edge during the expected window, it sets the one clock missing bit. if the dpll does not detect an edge after two successive attempts, it sets the two clock missing bit and the dpll automatically enters the search mode. to reset both clocks missing latches, you can disable and re- enable the dpll using the reset rx status. [9] brg enable (brgen) this bit controls the operation of the baud rate generator (brg). to enable the brg counter, set the brgen bit to '1'. to inhibit counting, clear the bit to '0'. [10] tx 4 word mode (tx4wd) when this bit is '0', and txfa bit in status register is '1', it is indicated that tx fifo is empty for 1 word. it means that 1-word data can be loaded to tx fifo. similarly, when this bit is '1', the same status register bit indicate that 4 words of data can be loaded to tx fifo without reading the status bit for a second time. specifically, the status register bit affected by the 1-word or 4-word transfer setting are the transmit data available (txfa) bit. [11] rx 4 word mode (rx4wd) when this bit is '0', and the rxfa bit in the status register is '1', it is indicated that rx fifo has 1-word data. it means that 1 word data can be moved to memory. similarly, when this bit is '1', the same status register bit indicates that 4 words of data can be moved in the memory without reading the status bit for a second time. specifically, the status register bit affected by the 1-word or 4-word transfer setting are the receive data available (rxfa) bit, and the residue bytes status bits, rxrb[3:0]. hdlc controller s3c 2500b 8- 32 table 8-10. hcon register description (continued) bit number bit name description [13:12] rx widget alignment (rxwa) these bits determine how many bytes are invalid in the first memory word of the frame to be received. the invalid bytes are inserted when the word is assembled in the hrxfifo. 00 = no invalid byte 01 = 1 invalid byte 10 = 2 invalid bytes 11 = 3 invalid bytes [14] dma tx stop or skip (dtx n stsk) this bit determines a dma tx stop or skip when dma has not the ownership associated with the tx buffer descriptor. dma tx is disabled in this condition when this bit is not set. (0 = not owner tx stop, 1 = not owner tx bd skip) [15] dma rx stop or skip (drx n stsk) this bit determines a dma rx stop or skip when dma has not the ownership associated with the rx buffer descriptor. if this bit is not set, dma rx is disabled. (0 = not owner rx stop, 1 = not ower rx bd skip) [16] dma rx memory address decrement (drxmadec) this bit determines whether the address is incremented or decremented. if this bit is set to '1', then the address will be decremented. [17] tx flag idle (txflag) this bit selects the flag 'time fill' mode (active idle) or the mark idle mode (inactive idle) for the transmitter. the selected active or inactive idle state continues until data is sent (after nreset has return to high level). the flag idle pattern is 7eh; the mark idle pattern is ffh. [18] tx single flag (txsflag) this bit controls whether separate closing and opening flags are transmitted in succession to delimit frames. when this bit is '0', independent opening and closing flags are transmitted in order to separate frame. when this bit is set to '1', the closing flag of the current frame serves as the opening flag of the next frame. [19] tx loop-back mode (txloop) this bit is used for self-testing. if this bit is set to '1', the transmit data output (txd) is internally connected to the receiver data input (rxd). in loop-back mode, ncts and ndcd inputs are ignored. for normal operation, this bit should always be '0'. [20] rx echo mode (rxecho) setting this bit to '1' selects the auto-echo mode of operation. in this mode, the txd pin is connected to rxd as in local loop-back mode, but the receiver still monitors the rxd input. [21] tx abort extension (txabtext) when this bit is set to '1', the abort pattern that is initiated when txabt = '1' is extended to at least 16 bits of 1s in succession, and the mark idle state is entered. [22] tx abort (txabt) when this bit is set to '1', an abort sequence of at least eight bits of 1s is transmitted. the abort is initiated and the htxfifo is cleared. txabt is then cleared automatically by hardware. S3C2500B hdlc controller 8- 33 table 8-10. hcon register description (continued) bit number bit name description [23] tx preamble (txprmb) when this bit is set to '1', the content of the hprmb register is transmitted as many txpl bit values in interrupt mode instead of mark idle or time fill mode. this is useful for sending the data needed by the dpll to lock the phase. it is used only by the transmitter interrupt mode, not by thetransmitter dma mode. (see 8-14) [24] tx data terminal ready (txdtr) the txdtr bit directly controls the ndtr output state. setting this bit forces the ndtr pin to low level. when you clear the txdtr bit, ndtr goes high. [25] rx frame discontinue (rxdiscon) when this bit is set, the frame currently received is ignored and the data in this frame is discarded. only the last frame received is affected. there is no effect on subsequent frames, even if the next frame enters the receiver when the discontinue bit is set. this bit is automatically cleared after a cycle. [26] tx no crc (txnocrc) when this bit is set to '1', the crc is not appended to the end of a frame by hardware. it is used only by the transmitter interrupt mode, not by the transmitter dma mode. (see 8-14) [27] rx no crc (rxnocrc) when this bit is set to '1', the receiver does not check for crc by hardware. (crc data is always moved to the hrxfifo.) [28] auto enable (autoen) this bit programs the function of both ndcd and ncts. however, txen and rxen must be set before the ncts and ndcd pins can be used. when this bit is '0', if the ncts becomes high, the transmitter sends mark idle pattern. however, though the ndcd becomes high, the receiver can receive the data. when this bit is '1', if the ncts becomes high, the transmitter send mark idle but clears the htxfifo and the tx block. if ndcd becomes high, the receiver can't operate, and the hrxfifo and rx blocks are cleared. [29] transparent rx stop (trxstop) this bit reset value is zero. if this bit set to one, the receive operation is ended in transparent mode. and then the receiver start to search sync. if this bit set to one in hdlc mode, rxfifo cleared except for receiver. so, the data in receiver can be moved to rx fifo at this time. [30] transmit reverse (txrev) if this bit set to one, the data will be sent msb first. if this bit set to zero, lsb first. [31] receive reverse (rxrev) if this bit set to one, the received data will be msb first. if this bit set to zero, lsb first. hdlc controller s3c 2500b 8- 34 [0] tx reset (txrs) 0 = normal 1 = txfifomand tx block are reset. [1] rx reset (rxrs) 0 = normal operation 1 = rxfifo and tx block are reset. [2] dma tx reset (dtxrs) 0 = normal operation 1 = dma tx block is reset. [3] dma rx reset (drxrs) 0 = normal operation 1 = dma rx block is reset. [4] tx enable (txen) 0 = tx disabled 1 = tx enabled [5] rx enable (rxen) 0 = rx disabled 1 = rx enabled [6] dma tx enable (dtxen) 0 = dma tx disabled 1 = dma tx enabled [7] dma rx enable (drxen) 0 = dma rx disabled 1 = dma rx enabled [8] dpll enable (dpllen) 0 = disable 1 = enable; dpll enters search mode for a locking edge in the incoming data stream. [9] brg enable (brgen) 0 = brg counter is inbibited. 1 = brg counter is enabled. [10] tx 4 word burst mode (tx4wd) 0 = 1-word mode selected. 1 = 4-word mode selected. [11] rx 4 word burst mode (rx4wd) 0 = 1-word mode selected. 1 = 4-word mode selected. [13:12] rx widget algnment (rxwa) 00 = no invalid byte 01 = 1 invalid byte 10 = 2 invalid byte 11 = 3 invalid byte [14] dma tx stop or skip (dtxstsk) 0 = dma tx stops when dma not owner bit is set. 1 = dma tx skips when dma not owner bit is set. [15] dma rx stop or skip (drxstsk) 0 = dma rx stops when dma not owner bit is set. 1 = dma rx skips when dma not owner bit is set. [16] dma rx memory address decrement (drxmadec) 0 = address is incremented. 1 = address is decremented. [17] tx flag idle (txflag) 0 = enter mark idle mode (a bit pattern of consecutive ones) 1 = enter time fill mode (a bit pattern of consecutive opening (closing) flag, as in string 01111110 01111110...... 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 a u t o e n r x e n t x e n r x d i s c o n r x n o c r c t x n o c r c t x d t r t x p r m b t x a b t t x a b t e x t r x e c h o t x l o o p t x s f l a g t x f l a g d r x m a d e c d r x s t s k d t x s t s k r x 4 w d t x 4 w d b r g e n d p l l e n d r x e n d t x e n r x w a d t x r s r x r s d r x r s t x r s r x r e v t x r e v t r x s t o p figure 8-14. hdlc control register (hcon) S3C2500B hdlc controller 8- 35 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 a u t o e n r x e n t x e n r x d i s c o n r x n o c r c t x n o c r c t x d t r t x p r m b t x a b t t x a b t e x t r x e c h o t x l o o p t x s f l a g t x f l a g d r x m a d e c d r x s t s k d t x s t s k r x 4 w d t x 4 w d b r g e n d p l l e n d r x e n d t x e n r x w a d t x r s r x r s d r x r s r x r e v t x r e v t r x s t o p t x r s [18] tx single flat (txsflag) 0 = double flag mode (a closing & opening flags are used to separate frames) 1 = single flag mode (only one flags are used to separate frames) [19] tx loop-back mode (txloop) 0 = normal operation. 1= the tramsmit data output is internally connected to the receiver data input for self testing . [20] rx echo mode (rxecho) 0 = disable tx auto-echo mode. 1 = enable rx echo mode. [21] tx abort extension (txabtext) 0 = at least eight consecutive 1's are transmitted. 1 = at least 16 consecutive 1's are transmitted. [22] tx abort (txabt) 0 = normal 1 = enable (at least eight consecutive 1's are transmitted.) [23] tx preamble (txprmb) 0 = transmit a mark idle is time fill bit pattern. 1 = transmit the content of hprmb [24] tx data terminology ready (txdtr) 0 = ndtr goes high level. 1 = ndtr goes low level. [25] rx frame discontinue (txdiscon) 0 = normal 1 = ignore the currently received frame [26] tx no crc (txnocrc) 0 = disable 1 = crc is not appended by hardware. [27] rx no crc (rxnocr) 0 = disable 1 = receiver does not check crc by hardware. (crc is treated as data in any case) [28] auto enable (autoen) 0 = normal operation. even if the ncts or ndcd become high, the transmitter can send tx data and the receiver can receive rx data. 1 = if the ndcd or ncts become high, the transmitter can not send tx data and the receiver can not receive rx data. [29] transparent rx stop (trxstop) 0 = normal 1 = stop receive operation. [30] tx reverse (txrev) 0 = normal 1 = send tx data reversly. [31] rx reverse (rxrev) 0 = normal operation 1 = receive rx data reversly. figure 8-14. hdlc control register (hcon) (continued) hdlc controller s3c 2500b 8- 36 8.7.3 hdlc status register (hstat) note reading the hdlc status register is a non-destructive process. the method used to clear a high-level status condition depends on the bit's function and operation mode(dma or interrupt). for details, please see the description of each status register. table 8-11. hstata, hstatb, and hstatc register registers address r/w description reset value hstata 0 f0100008 r/w hdlc channel a status register 0x00000000 hstatb 0 f0110008 r/w hdlc channel b status register 0x00000000 hstatc 0 f0120008 r/w hdlc channel c status register 0x00000000 8.7.4 summary there are two kinds of bits in a status register. 1. txfa, txcts, rxfa, rxdcd, rxfv, rxcrce, rxno, rxierr, and rxov bits are show each bit's status. these bits are set or cleared automatically according to the each bit status. 2. all other bits are cleared by the cpu writing '1' to each bit. S3C2500B hdlc controller 8- 37 table 8-12. hstat register description bit number bit name description [3:0] rx remaining bytes (rxrb) (rxrb + 1) indicates how many data bytes are valid in a 1-word or 4- word boundary when the receiver has received a complete frame. in 1- word transfer mode, the rxrb value is either 0, 1, 2, or 3. in 4-word mode, it is 0, 1, ..., 14, or 15. [4] tx frame complete (txfc) this status bit is automatically set to '1' when the two conditions are met: 1) there is no data in the tx fifo, and 2) either an abort or a closing flag is transmitted. you can clear this bit by writing '1' to this bit. [5] tx fifo available (txfa) if this bit is '1', the data to be sent can be loaded into the htxfifo register. in 1-word transfer mode, the txfa status bit is set to '1' when the first register of the htxfifo is empty. in 4-word transfer mode, txfa = '1' when the first four 32-bit registers of the htxfifo are empty. the txfa status condition is automatically cleared when htxfifo is no longer available. during dma tx operation, this bit is always '0', so not generating interrupt. [6] tx clear-to-send (txcts) the ncts input is projected to this status bit. if the level at the ncts input pin is low, this status bit is'1'. if ncts input pin is high level, txcts is '0'. this bit does not generate an interrupt. [7] tx stored clear-to-send (txscts) this bit is set to '1' each time a transition in ncts input occurs. you can clear this bit by writing '1' to this bit. [8] tx under-run (txu) when the transmitter runs out of data during a frame transmission, an underrun occurs and the frame is automatically terminated by transmitting an abort sequence. the underrun condition is indicated when txu is '1'. you can clear this bit by writing a '1' to this bit. [9] rx fifo available (rxfa) this status bit indicates when the data received can be read from the rx fifo. when rxfa is '1', it indicates that data (other than an address or a final data word) is available in the hrxfifo. in 1-word transfer mode, rxfa bit set to '1' when received data is available in the last fifo register. in 4-word transfer mode, it is set to '1' when the data received is available in the last four 32-bit fifo registers. even if the data reside in fifo for only two words, when the last bit is set, rx fifo is regarded as valid. (the received data available condition is cleared automatically when the data received is no longer available.) during dma rx operation, this bit is always '0', so does not generate an interrupt. [10] tx frame good (txfg) this bit set to one when one frame sent well. hdlc controller s3c 2500b 8- 38 table 8-12. hstat register description (continued) bit number bit name description [11] rx flag detected (rxfd) this bit is set to '1' when the last bit of the flag sequence is received. this bit generates an interrupt if enabled. you can clear this bit by writing a '1' to this bit. [12] rx data carrier detected (rxdcd) the dcd status bit mirrors the state of the ndcd input pin. if ndcd input pin is low, this status bit is '1'. if ndcd input pin is high, it is '0'. this bit does not generate an interrupt. [13] rx stored data carrier detected (rxsdcd) this bit is set to '1' when a transition in ndcd input occurs, and can generate interrupt, if enabled. you can clear this bit by writing a '1' to this bit. [14] rx frame valid (rxfv) this bit signals frame's ending boundary to the cpu and also indicates that no frame error occurred. it is set when the last data byte of a frame is transferred into the last location of the rx fifo and is available to be read. [15] rx idle (rxidle) the rxidle status bit indicates that a minimum of 15 consecutive 1s have been received. the event is stored in the status register and can be used to trigger a receiver interrupt. the rxidle bit continues to reflect the inactive idle condition until a '0' is received. you can clear this bit by writing a '1' to this bit. [16] rx abort (rxabt) the rxabt status bit is set to '1' when seven or more consecutive 1s (abort sequence) have been received. when an abort is received in an 'in-frame' condition, the event is stored in the status register triggering an interrupt request. you can clear this bit by writing a '1' to this bit. [17] rx crc error (rxcrce) the rxcrce status bit is set a frame is completed with a crc error. [18] rx non-octet align (rxno) the rxno bit is set to '1', if received data is non-octet aligned frame. [19] rx overrun (rxov) the rxov status bit is set to '1', if the data received is transferred into the hrxfifo when it is full, resulting in a loss of data. continued overruns destroy data in the first fifo register. [20] reserved not applicable. [21] reserved. not applicable. [22] dma tx abort (dtxabt) this bit is set to '1' when abort signal is sent due to the tx underrun or cts lost occurred. if this bit is set, dtxen(in hcon) bit cleared. you can clear this bit by writing '1' to this bit. S3C2500B hdlc controller 8- 39 table 8-12. hstat register description (continued) bit number bit name description [23] rx internal error (rxierr) this bit is set to '1' when received frame will be detected error possibility due to the receive clock is unstable. [24] dma rx frame done every received frame (drxfd) this bit is set when a dma rx operation has successfully operated a frame to memory from hrxfifo, and when the last byte of a frame has been written to memory. this bit generate interrupt when set to '1' to know a frame is received. you can clear this bit by writing '1' to this bit. [25] reserved not applicable. [26] dma rx not owner (drxno) this bit is set, when dma is not owner of the current buffer descriptor, and drxnstsk bit was set. in this case, dma rx is disabled and can generate interrupt, if enabled. if drxnstsk bit is zero, this bit is always zero. you can clear this bit by writing '1' to this bit. [27] dma tx frame done (dtxfd) in case of mff bit is '0' (default), when dna tx operation has successfully transferred rest byte of frame from tx fifo to destination, this bit will be set to ?1?. but if mff is set to ?1?, transceiver will keep sending the data until there is no data transfer from memory to txfifo. [28] reserved not applicable. [29] dma tx not owner (dtxno) this bit is set, when dma is not owner of the current buffer descriptor, and dtxnstsk bit was set. in this case, dma tx disabled and can generate interrupt, if enabled. if dtxnstsk bit is zero, this bit is always zero. you can clear this bit by writing '1' to this bit. [30] dpll one clock missing (dpllom) when operating in fm/manchester mode, the dpll sets this bit to '1' if it does not detect an edge in its first attempt. you can clear this bit by writing a '1' to this bit. [31] dpll two clock missing (dplltm) when it is operating in the fm/manchester mode, the dpll sets this bit to '1' if it does not detect an edge in two successive attempts. at the same time the dpll enters search mode. in nrz/nrzi mode, and while the dpll is disabled, this bit is always '0'. you can clear this bit by writing a '1' to this bit. hdlc controller s3c 2500b 8- 40 [3:0] rx remaining bytes (rxrb) at 1-word boundary: at 4-word boundary: 0000 = valid data byte is 1 0000 = valid data byte is 1 0001 = valid data byte is 2 . 0010 = valid data byte is 3 . 0011 = valid data byte is 4 1111 = valid data byte is 16 [4] tx frame complete (txfc) 0 = normal operation 1 = automatically set; if two conditions are met: 1) tx fifo is empty. 2) an abort or a closing flag is transmitted. [5] tx fifo available (txfa) 0 = tx fifo is not available. 1 = tx fifo is available. (that is, the data to be transmitted can now be loaded into the tx fifo.) [6] tx clear-to send (txcts) 0 = level at the ncts input pin is high. 1 = level at the ncts input pin is low. [7] tx stored clear-to-send (txscts) 0 = normal operation 1 = a transition occured at the ncts input. (this transition can be used to trigger an interrupt.) [8] tx underrun (txu) 0 = normal operation 1 = the transmitter ran out of data during transmission. [9] rx fifo available (rxfa) 0 = normal operation 1 = data is available in the rxfifo. [10] tx frame good (txfg) 0 = normal operation 1 = tx data sent well [11] rx flag detected (rxfd) 0 = normal operation 1 = this bit is set, when the last bit of the flag sequence is received. [12] rx data-carrier-detected (rxdcd) 0 = ndcd input pin is high 1 = ndcd input pin is low [13] rx stored data-carrier-detected (rxsdcd) 0 = normal operation 1 = when a transition of the ndcd input occurs, this bit is set. [14] rx frame valid (rxfv) 0 = normal operation 1 = the last data byte if a frame is transferred into the last location of rxfifo. [15] rx idle (rxidle) 0 = normal operation 1 = a minimum 15 consecutive 1's have been received. 31 0 3 4 5 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 t x f a t x f c d t x f d d r x n o d r x f d r x i e r r d t x a b t r x o v r x n o r x c r c e r x a b t r x i d l e r x f v r x f d r x f a t x u t x s c t s t x c t s r x s d c d r x r b d p l l t m d p l l o m d t x n o r x d c d t x f g figure 8-15. hdlc status register S3C2500B hdlc controller 8- 41 [16] rx abort (rxabt) 0= normal operation 1 = seven or more consecutive 1s have been received, in-frame condition. [17] rx crc error (rxcrce) 0 = normal operation 1 = a frame rx operation is completed with a crc error. [18] rx non-octet align (rxno) 0 = received frame is octet. 1 = received frame is not octet. [19] rx overrun (rxov) 0 = normal operation 1 = received data is transferred into the rxfifo when it is full. [20] reserved [21] reserved [22] dma tx abort (dtxabt) 0 = normal operation 1 = abort signal is sended and dma tx enable bit is cleared. [23] rx internal error (rxierr) 0 = normal operation 1 = received frame is not stable due to receive clock is unstable. [24] dma rx frame done every received frame (drxfd) 0 = normal operation 1 = dma rx operation has successfully transferred a frame from rxfifo to buffer memory. [25] reserved [26] dma rx not owner (drxno) 0 = dma has the ownership. 1 = cpu has the ownership. [27] dma tx frame done (dtxfd) 0 = normal operation 1 = dma tx operation has successfully transferred a frame from memory to txfifo. [28] reserved [29] dma tx not owner (dtxno) 0 = dma has the ownership. 1 = cpu has the ownership. [30] dpll one clock missing (dpllom) 0 = normal operation 1 = set in fm/machester mode when dpll does not detect an edge on the first entry. [31] dpll two clock missing (dplltm) 0 = normal operation 1 = dpll was not detected on two consecutive edges an search mode sas entered. 31 0 3 4 5 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 t x f a t x f c d t x f d d r x n o d r x f d r x i e r r d t x a b t r x o v r x n o r x c r c e r x a b t r x i d l e r x f v r x f d r x f a t x u t x s c t s t x c t s r x s d c d r x r b d p l l t m d p l l o m d t x n o r x d c d t x f g figure 8-15. hdlc status register (continued) hdlc controller s3c 2500b 8- 42 8.7.5 hdlc interrupt enable register (hinten) table 8-13. hintena, hintenb, and hintenc register registers address r/w description reset value hintena 0 f010000c r/w hdlc interrupt enable register 0x00000000 hintenb 0 f011000c r/w hdlc interrupt enable register 0x00000000 hintenc 0 f012000c r/w hdlc interrupt enable register 0x00000000 table 8-14. hinten register description bit number bit name description [3:0] reserved ? [4] txfcie tx frame complete interrupt enable [5] txfaie tx fifo available to write interrupt enable [6] reserved ? [7] txsctsie cts transition has occurred interrupt enable [8] txuie tx under-run has occurred interrupt enable [9] rxfaie rx fifo available to read interrupt enable [10] txfgie tx frame good interrupt enable [11] rxfdie rx flag detected interrupt enable [12] reserved ? [13] rxsdcdie dcd transition interrupt enable [14] rxfvie rx frame valid interrupt enable [15] rxidleie idle detected interrupt enable [16] rxabtie abort detected interrupt enable [17] rxcrceie crc error frame interrupt enable [18] rxnoie non-octet aligned frame interrupt enable [19] rxovie rx overrun interrupt enable [20] reserved ? [21] reserved ? [22] dtxabtie dma tx abort interrupt enable [23] rxierrie rx internal error interrupt enable [24] drxfdie dma rx frame done interrupt enable [25] reserved ? [26] drxnoie dma rx not owner interrupt enable [27] dtxfdie dma tx frame done every transmitted frame interrupt enable [28] reserved ? [29] dtxnoie dma tx not owner interrupt enable [30] dpllomie dpll one clock missing interrupt enable [31] dplltmie dpll two clocks missing interrupt enable S3C2500B hdlc controller 8- 43 31 0 3 4 5 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 t x f a i e t x f c i e d t x f d i e d r x n o i e d r x f d i e r x i e r r i e d t x a b t i e r x o v i e r x n o i e r x c r c e i e r x a b t i e r x i d l e i e r x f v i e r x f d i e r x f a i e t x u i e t x s c t s i e r x s d c d i e d p l l t m i e d p l l o m i e d t x n o i e t x f g i e [3:0] reserved [4] tx frame complete interrupt enable (txfcie) [5] tx fifo available to write interrupt enable (txfaie) [6] reserved [7] cts transition has occurred interrupt enable (txsctie) [8] transmit underrun has occured interrupt enable (txuie) [9] rxfifo available to read interrupt enable (rxfaie) [10] tx frame good interrupt enable (txfgie) [11] flag detected interrupt enable (rxfdie) [12] reserved [13] dcd transition interrupt enable (rxsdcdie) [14] valid frame interruopt enable (rxfvie) [15] idle detected interruot enable (rxidleie) [16] abort detected interrupt enable (rxabtie) [17] crc error frame interrupt enable (rxcrceie) [18] non-dctet aligned frame interrupt enable (rxnoie) [19] rx overrun interrupt enable (rxovie) [20] reserved [21] reserved [22] dma tx abort interrupt enable (dtxabtie) [23] rx internal error interrupt enable (rxierrien) [24] dma rx frame done every received frame interrupt enable (drxfdie) [25] reserved [26] dma rx not owner interrupt enable (drxnoie) [27] dma tx frame done every received frame interrupt enable (dtxfdie) [28] reserved [29] dma tx not owner interrupt enable (dtxnoie) [30] dpll one missing interrupt enable (dpllomie) [31] dpll two missing interrupt enable (dplltmie) figure 8-16. hdlc interrupt enable register hdlc controller s3c 2500b 8- 44 8.7.6 hdlc tx fifo (htxfifo) the tx fifo consists of eight 32-bit registers that are used for buffer storage of data to be transmitted. data is always transferred from a full register to an empty adjacent register. the tx fifo can be addressed at two different register addresses: the 'frame continue' address and the 'frame terminate' address. each register has four pointers, data valid pointer bit (4 bits), last pointer bit, nocrc pointer bit, preamble pointer bit. the data valid pointer bit indicates whether each byte is valid or not. the last byte pointer bit indicates whether the frame to be sent has the frame last byte or not. the nocrc pointer bit determines whether the crc data is to be appended or not by hardware. when a valid data byte is written to the 'frame continue' address, the data valid pointer is set, but the last byte pointer is not set. when a valid data byte is written to the 'frame terminate' address, the data valid pointer and last byte pointer are set together. to reset these pointers, you write a '1' to either the txabt bit or the txrs bit in the hcon register. in dma mode, when the dma controller writes data to the htxfifo, tx buffer descriptor buffer length field value must be pre-set. however, if the last bit is set in buffer descriptor, the last byte pointer in htxfifo is also set. this means the last byte of the frame is in htxfifo. if the transmitted frame is longer than the buffer length field value, the last byte pointer will not be set, and the next buffer descriptor having the last byte pointer bit will be used. the pointers continue shifting through the fifo. when the transmitter detects a positive transition in the data valid pointer at the last location of the fifo, it initiates a frame with an opening flag. when it detects a negative transition in the last byte pointer at the last location of the fifo, it closes the frame, appending the crc and a closing flag follows. the status of the tx fifo is indicated by the transmitter fifo register available (txfa) status bit. when txfa = '1', the tx fifo is available for loading data and data can be loaded into it. (this function is controlled by the tx4wd bit.) the htxfifo is reset by writing a '1' to the tx reset, or the txabt bit or by the nreset. during a reset operation, the txfa status bit is suppressed and data loading is inhibited. 8 tx data txfifo data valid (4-bit) 8-bit 8-bit 8-bit 8-bit last (1-bit) nocrc preamble figure 8-17. hdlc tx fifo function diagram S3C2500B hdlc controller 8- 45 8.7.7 hdlc rx fifo (hrxfifo) the rx fifo consists of eight 32-bit registers that are used for the buffer storage of the data received. data bytes are always transferred from a full register to an adjacent empty register. each register has pointer bits that indicate the frame status. when these pointers appear at the last 1-word or 4-word fifo location, they update the last bit(indicating the last of a frame), the overrun bit, the crc error bit, or non-octet aligned bit. the hrxfifo data available (rxfa) status bits indicate the current state of the hrxfifo. when the hrxfifo data status bit is '1', the hrxfifo is ready to be read. the hrxfifo data status is controlled by the 4-word or 1- word transfer selection bit (rx4wd). when an overrun occurs, the overrun frame of the hrxfifo is no longer valid. an 'in frame' abort or a high level on ndcd input with the autoen bit in hcon is set to '1', the frame is cleared in the hrxfifo. (the last byte of the previous frame, which is separated by the frame boundary pointer, is retained). data in hrxfifo should be read by word size. the hrxfifo is cleared by the rx reset bit set to '1', an abort signal received, or nreset. rx data rxfifo data valid 8-bit 8-bit 8-bit 8-bit last ov crce no figure 8-18. hdlc rx fifo function diagram hdlc controller s3c 2500b 8- 46 8.7.8 hdlc brg time constant registers (hbrgtc) table 8-15. hbrgtca and hbrgtcb register registers address r/w description reset value hbrgtca 0 f010001c r/w hdlc brg time constant register 0x00000000 hbrgtcb 0 f011001c r/w hdlc brg time constant register 0x00000000 hbrgtcc 0 f012001c r/w hdlc brg time constant register 0x00000000 the hdlc brg time constant register value can be changed at any time, but the new value does not take effect until the next time the constant is loaded into the down counter. no attempt is made to synchronize the loading of the time constant into hbrgtc while the clock is driving the down counter. for this reason, you should first disable the baud rate generator before loading the new time constant into the hbrgtc register. the formula for determining the appropriate time constant for a given baud rate is shown below. the desired rate is shown in bits per second. this formula shows how the counter decrements from n down to zero-plus-one cycles for reloading the time constant. this value is then fed to a toggle flip-flop to generate the square wave output. brgout1 = (mclk2 or rxc)/(cnt0 + 1)/(16 cnt1 ) brgout2 = brgout1/(1 or 16 or 32 according to cnt2 value of the hbrgtc) 31 15 16 [1:0] time constant value for cnt2 00 = divide by 1 01 = adivide by 16 10 = divide by 32 [3:2] time constant value for cnt1 00 = divide by 1 01 = divide by 16 [15:4] time constant value for cnt0 0 18 17 3 4 1 2 cnt0 cnt1 19 21 20 cnt2 22 23 24 25 26 27 28 29 30 figure 8-19. hdlc brg time constant register S3C2500B hdlc controller 8- 47 8.7.9 hdlc preamble constant register (hprmb) the hprmb register is used to meet the dpll requirements for phase-locking. the preamble pattern is transmitted as many tx preamble length bit values in hmode[10:8] when the tx preamble bit (txprmb) is '1', and then the tx preamble bit is cleared automatically. the opening flag follows this preamble pattern, and the data will be transmitted. table 8-16. hprmba and hprmbb register registers address r/w description reset value hprmba 0 f0100020 r/w hdlc preamble constant register 0x00000000 hprmbb 0 f0110020 r/w hdlc preamble constant register 0x00000000 hprmbc 0 f0120020 r/w hdlc preamble constant register 0x00000000 [1:0] preamble pattern 31 0 21 preamble pattern 22 23 24 25 26 27 28 29 30 16 18 17 19 20 11 13 12 14 15 7 8 10 9 figure 8-20. hdlc preamble constant register the reference for the preamble pattern of each data mode is as follows: table 8-17. preamble reference pattern data mode preamble pattern nrz aa nrzi 00 fm0 ff fm1 00 manchester aa hdlc controller s3c 2500b 8- 48 8.7.10 hdlc station address registers (hsadr0-3) and hmask register each hdlc controller has five 32-bit registers for address recognition: four station address registers and one mask register. generally, the hdlc controller reads the address of the frame from the receiver, to check it against the four station address values, and then masks the result with the user-defined hmask register. a "1" in the hmask register represents a bit position for which an address comparison should occur. a "0" represents a masked bit position. if you check the address up to four bytes, the hmask register value should be 0xffffffff. dependent on the hmask register value, the frame's address is compared. if the address is not matched, this frame is discarded. table 8-18. hsadr and hmask register registers address r/w description reset value hsadr0a 0 f0100024 r/w hdlc station address 0 0x00000000 hsadr1a 0 f0100028 r/w hdlc station address 1 0x00000000 hsadr2a 0 f010002c r/w hdlc station address 2 0x00000000 hsadr3a 0 f0100030 r/w hdlc station address 3 0x00000000 hmaska 0 f0100034 r/w hdlc address mask register 0x00000000 hsadr0b 0 f0110024 r/w hdlc station address 0 0x00000000 hsadr1b 0 f0110028 r/w hdlc station address 1 0x00000000 hsadr2b 0 f011002c r/w hdlc station address 2 0x00000000 hsadr3b 0 f0110030 r/w hdlc station address 3 0x00000000 hmaskb 0 f0110034 r/w hdlc address mask register 0x00000000 hsadr0c 0 f0120024 r/w hdlc station address 0 0x00000000 hsadr1c 0 f0120028 r/w hdlc station address 1 0x00000000 hsadr2c 0 f012002c r/w hdlc station address 2 0x00000000 hsadr3c 0 f0120030 r/w hdlc station address 3 0x00000000 hmaskc 0 f0120034 r/w hdlc address mask register 0x00000000 hmask hsadr0 hsadr1 hsadr2 hsadr3 0xffffffff 0xabcdefgh 0xffffffff 0xabcdefgh 0xabcdefgh note: recognize one 32-bit address and the 32-bit broadcast address hmask hsadr0 hsadr1 hsadr2 hsadr3 0xff000000 0x55xxxxxx 0x55xxxxxx 0x55xxxxxx 0x55xxxxxx note: recognize a single 8-bit address figure 8-21. address recognition S3C2500B hdlc controller 8- 49 31 15 16 station address byte register and mask register [31:24] first address byte [23:16] second address byte [15:8] third address byte [7:0] fourth address byte 0 7 8 fourth byte 23 24 third byte second byte first byte figure 8-22. hdlc station address and hmask register 8.7.11 dma tx buffer descriptor pointer register the dma transmit buffer descriptor pointer register contains the address of the tx buffer data pointer on the data to be sent. during a dma operation, the buffer descriptor pointer is updated by the next buffer data pointer. table 8-19. dma tx buffer descriptor pointer registers registers address r/w description reset value hdmatxptra 0 f0100038 r/w dma tx buffer descriptor pointer 0xffffffff hdmatxptrb 0 f0110038 r/w dma tx buffer descriptor pointer 0xffffffff hdmatxptrc 0 f0120038 r/w dma tx buffer descriptor pointer 0xffffffff 31 [25:0] dma tx buffer descriptor pointer 0 dma tx buffer descriptor pointer 25 26 27 28 29 30 figure 8-23. dma tx buffer descriptor pointer hdlc controller s3c 2500b 8- 50 8.7.12 dma rx buffer descriptor pointer register the dma receive buffer descriptor pointer register contains the address of the rx buffer data pointer on the data to be received. during a dma operation, the buffer descriptor pointer is updated by the next buffer data pointer. table 8-20. dma rx buffer descriptor pointer registers registers address r/w description reset value hdmarxptra 0 f010003c r/w dma rx buffer descriptor pointer 0xffffffff hdmarxptrb 0 f011003c r/w dma rx buffer descriptor pointer 0xffffffff hdmarxptrc 0 f012003c r/w dma rx buffer descriptor pointer 0xffffffff 31 [25:0] dma rx buffer descriptor pointer 0 dma rx buffer descriptor pointer 25 26 27 28 29 30 figure 8-24. dma rx buffer descriptor pointer 8.7.13 maximum frame length register the hdlc controller checks the length of an incoming frame against the user-defined value in dma mode. if the frame received exceeds this register value, the frame is discarded, and flv(frame length violated) bit is set in the buffer descriptor belonging to that frame. table 8-21. hdmatxcnt and hdmarxcnt registers registers address r/w description reset value hmflra 0 f0100040 r/w maximum frame length 0xxxxx0000 hmflrb 0 f0110040 r/w maximum frame length 0xxxxx0000 hmflrc 0 f0120040 r/w maximum frame length 0xxxxx0000 31 15 16 [15:0] maximum frame length 0 18 17 19 21 20 maximum frame length 22 23 24 25 26 27 28 29 30 figure 8-25. maximum frame length register S3C2500B hdlc controller 8- 51 8.7.14 receive buffer size register the rx buffer size register contains the 16-bit user-defined value. this user-defined count value determines the buffer size for one buffer descriptor. if incoming hdlc frame is longer than the rx buffer size register value, the next buffer descriptor having the rx buffer size value will be used. table 8-22. dma rx buffer size register registers address r/w description reset value hrbsra 0 f0100044 r/w receive buffer size register 0xxxxx0000 hrbsrb 0 f0110044 r/w receive buffer size register 0xxxxx0000 hrbsrc 0 f0120044 r/w receive buffer size register 0xxxxx0000 31 15 16 [15:0] receive buffer size register 0 18 17 19 21 20 receive buffer size 22 23 24 25 26 27 28 29 30 figure 8-26. dma receive buffer size register 8.7.15 synchronization register the hdlc synchronous register content will be sent during flag idle in hdlc mode. in mark idle mode, this register content can not used. however, in transparent mode with in-line sync, this register value used for searching sync pattern . this sync pattern is used as like opening or closing flag. in-line sync or out-line sync determined by autoen bit value. if autoen bit is set to zero, it is determined to in-line sync in transparent mode. table 8-23. synchronization register registers address r/w description reset value hsynca 0xf0100048 r/w hdlc sync register 0x7e hsyncb 0xf0110048 r/w hdlc sync register 0x7e hsyncc 0xf0120048 r/w hdlc sync register 0x7e 31 15 16 [7:0] sync pattern 0 18 17 12 13 14 9 10 11 7 8 19 21 20 sync pattern 22 23 24 25 26 27 28 29 30 figure 8-27. hdlc synchronization register hdlc controller s3c 2500b 8- 52 8.7.16 transparent control register the hdlc transparent register controls the transparent data flow. this is composed with data sampling field and rts control field. table 8-24. transparent control register registers address r/w description reset value tcona 0xf010004c r/w transparent control register 0xxxxx0000 tconb 0xf011004c r/w transparent control register 0xxxxx0000 tconc 0xf012004c r/w transparent control register 0xxxxx0000 bit number bit name description [1:0] data sampling (ds) these bit values determine which data bits are regarded as valid after the ndcd state active. 00 = the first valid bit is d4, 01 = the first valid bit is d3, 10 = d2 and 11 = d1. see figure 8-28, data sampling method. [3:2] reserved not applicable. [4] rts control(rts) it this bit set to one, the nrts pin goes low. [31:5] reserved not applicable. data ndcd rxc sampled here if ds value is 01. d1 d2 d4 d5 d6 d7 d8 d3 figure 8-28. data sampling method S3C2500B hdlc controller 8- 53 8.7.17 tx buffer descriptor count register tx buffer descriptor count register which shows how many tx buffer descriptor is used. table 8-25. htxbdcnta, htxbdcntb, and htxbdcntc register registers address r/w description reset value htxbdcnta 0 f01000c0 r tx buffer descriptor count register 0 xxxxx000 htxbdcntb 0 f01100c0 r tx buffer descriptor count register 0 xxxxx000 htxbdcntc 0 f01200c0 r tx buffer descriptor count register 0 xxxxx000 8.7.18 rx buffer descriptor count register rx buffer descriptor count register which shows how many rx buffer descriptor is used. table 8-26. hrxbdcnta, hrxbdcntb, and hrxbdcntc register registers address r/w description reset value hrxbdcnta 0 f01000c4 r rx buffer descriptor count register 0 xxxxx000 hrxbdcntb 0 f01100c4 r rx buffer descriptor count register 0 xxxxx000 hrxbdcntc 0 f01200c4 r rx buffer descriptor count register 0 xxxxx000 hdlc controller s3c 2500b 8- 54 8.7.19 tx buffer descriptor maximum count register tx buffer descriptor maximum count register sets tx buffer descriptor maximum counts. for example, if you set the htxbdmaxcnt register to "0xfff", then you can use 1(2 0 ) buffer descriptor. if you set the htxbdmaxcnt register to "0xffe", "0xffc", "0xff8", "0xff0", "0xfe0", then you can use 2(2 1 ), 4(2 2 ), 8(2 3 ), 16(2 4 ), 32(2 5 ) buffer descriptor for each buffer descriptor maximum count register setting. you can set the htxbdmaxcnt register up to "0x800", so you can use maximum 2048(2 11 ) buffer descriptors. after htxbdmaxcnt buffer descriptor used, the tx buffer descriptor address pointer points the start address. table 8-27. htxbdmaxcnta, htxbdmaxcntb, and htxbdmaxcntc register registers address r/w description reset value htxbdmaxcnta 0 f01000c8 r/w tx buffer descriptor maximum count control register 0 xxxxxfff htxbdmaxcntb 0 f01100c8 r/w tx buffer descriptor maximum count control register 0 xxxxxfff htxbdmaxcntc 0 f01200c8 r/w tx buffer descriptor maximum count control register 0 xxxxxfff 8.7.20 rx buffer descriptor maximum count register rx buffer descriptor maximum count register sets rx buffer descriptor maximum counts. for example, if you set the hrxbdmaxcnt register to "0xfff", then you can use 1(2 0 ) buffer descriptor. if you set the hrxbdmaxcnt register to "0xffe", "0xffc", "0xff8", "0xff0", "0xfe0", then you can use 2(2 1 ), 4(2 2 ), 8(2 3 ), 16(2 4 ), 32(2 5 ) buffer descriptor for each buffer descriptor maximum count register setting. you can set the hrxbdmaxcnt register up to "0x8002 1 , so you can use maximum 2048(2 11 ) buffer descriptors. after hrxbdmaxcnt buffer descriptor used, the rx buffer descriptor address pointer points the start address. table 8-28. hrxbdmaxcnta, hrxbdmaxcntb, and hrxbdmaxcntc register registers address r/w description reset value hrxbdmaxcnta 0 f01000cc r/w rx buffer descriptor maximum count control register 0 xxxxxfff hrxbdmaxcntb 0 f01100cc r/w rx buffer descriptor maximum count control register 0 xxxxxfff hrxbdmaxcntc 0 f01200cc r/w rx buffer descriptor maximum count control register 0 xxxxxfff S3C2500B iom2 contr oller 9 - 1 9 iom2 & tsa controller 9.1 overview the iom2-bus is an industry standard serial bus for interconnecting telecommunication ics. the S3C2500B includes the iom2 controller to enable a modular interface to the terminal network such as an isdn interface. 9.2 features iom2 terminal mode support inter device communication via ic channel tic bus access control monitor channel collision control optional signals such as bcl and strb bus deactivation/activation via c/i0 bus reversal iom2 controller s3c 2500b 9- 2 9.3 iom2 bus the iom2 bus provides a symmetrical full-duplex communication link, containing user data, control/programming, and status channels. both the line card and terminal portions of the iom2 standard utilize the same basic frame and clocking structure, but differ in the number and usage of the individual channels. the various channels are time-multiplexed over a four-wire serial interface. data is clocked by a data rate clock(dcl) that operates at twice the data rate. frames are delimited by an 8-khz frame synchronization clock(fsc). data is carried over data upstream(du) and data downstream(dd) signals. three additional signals are specified in the terminal mode to facilitate connecting components that do not directly support iom2. these are a 1x-bit rate clock (bcl), and two serial data strobes that identify the location of the b channels (sds1 and sds2). the S3C2500B includes two optional signals, bcl and sds1. sds1 is called strb in S3C2500B. in S3C2500B, the terminal mode operation is supported but line-card mode is not supported. figure9-1 shows the iom2 channel structure in terminal mode. b1 b2 d ci0 ic1 ic2 mon0 ci1 mon1 b1 b2 d ci0 ic1 ic2 mon0 ci1 mon1 bac tad s/g a/b mx mr mx mr mx mr mx mr fsc du dd strb dcl bcl figure 9-1. iom2 channel structure in terminal du, dd 768 kbit/s (du = data upstream = output, dd = data downstream = input) dcl 1536 khz input (double data rate) fsc 8 khz input bcl 768 khz output strb strobe signal for non-iom2 device S3C2500B iom2 contr oller 9 - 3 9.3.1 b channels the b1 and b2 provide two clear 64 kbit/s user data channels to/from the network. 9.3.2 d channel the 16 kbit/s d channel provides a connection between the layer-2 and layer-1 components 9.3.3 monitor channels there are two programming channels, monitors 0 and 1, each channel has an associated pair of mx and mr handshake bits that control data flow. 9.3.4 command and indicate channels three command and indicate channels, c/i0, c/i1, and c/i2 provide real-time status between devices connected via the iom2 bus. 9.3.5 intercommunication channels two intercommunication data channels, ic1 and ic2 provide 64 kbit/s data paths between user devices. 9.3.6 tic bus one d- channel accesses bus , tic bus. the tic function is implemented using 4 bits of the c/i2 channel, and allows multiple layer2 devices to individually gain access to the d and c/i channels located in the first sub-frame. iom2 controller s3c 2500b 9- 4 9.3.7 channel operation 9.3.7.1 monitor channel operation the monitor channel is a handshake protocol for high speed information exchange between S3C2500B and other devices. the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using mx (monitor transmit) and mr (monitor receive). for example, data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted repeatedly once per 8-khz frame until the transfer is acknowledged via the mr bit. receiver transmitter mx mr 1st byte mr mx md (1st byte) acknowledge mx: monitor transmit bit, active low mr: monitor receive bit, active low md: monitor data 2nd byte mx md (2nd byte) mr mr mr mr nth byte acknowledge acknowledge mx md (nth byte) mx md (nth byte) mr mr end of trnasmission mx md (2nd byte) mx mx end of trnasmission (eom) figure 9-2. monitor channel handshake protocol S3C2500B iom2 contr oller 9 - 5 the monitor protocol is illustrated in figure9-2. before the data in iom2mtd register is transmitted, the iom2 controller should verify that the transmission is idle, that is, mx/mr is inactive ("1") for two or more than 2 frames. when idle status is detected, the iom2 controller forces the mx bit to go active ("0"), indicating the presence of valid monitor data in the corresponding frame. as a result, the receiver stores the monitor data and generates mrxba(monitor rx buffer available) interrupt. when the iom2mrd is read by the cpu in response to the interrupt, the receiver forces mr bit to go active ("0"), indicating the acknowledge of received data. in response to the acknowledge, the transmitter generates mtxba(monitor tx buffer available) interrupt and the cpu writes data to iom2mtd. the mx bit is still in the active. the transmitter indicates a new byte in monitor channel by returning the mx bit active after sending it once in the inactive state. when the mrxba interrupt is generated and the cpu read out the iom2mrd, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate an mtxba interrupt. when the last byte has been transmitted and acknowledged, the cpu set the mtxeom(end of message request) to "1". this enforces inactive state in the mx bit. two frames of mx inactive indicate the end of a message. when the mx bit is received in the inactive state in two consecutive frames, the receiver generates the mrxeom(end of message received) interrupt and enforces an inactive state in the mr bit. this terminates the monitor channel transmission. 9.3.7.2 transmission error during the transmission process, the transmission is aborted only if errors in the mx/mr handshake protocol occur. an abort is indicated by setting the mr bit inactive for two or more frames. the transmitter must react with eom. this situation is illustrated in the following figure9-3. eom abort request transmitter mx receiver mr figure 9-3. abortion of monitor channel transmission iom2 controller s3c 2500b 9- 6 9.3.7.3 monitor channel collision detection when more than two devices is attached to iom2-bus, the S3C2500B resolves the collision by waiting inactive in the mx/mr bits before sending and a per bit check on the transmitted data. monitor channel access priority is determined by the address of the monitor message contained in the first monitor byte transmitted. once the transmitter detects inactive and starts to transmit the first byte, a per bit check is performed on each transmitted monitor bit. if any bit mismatches, the transmitter immediately withdraws from the monitor channel by setting the all remaining bits to 1, the monitor channel collision detection interrupt is generated and the transmitter reverts back to waiting for the idle condition. 9.3.7.4 c/i channel operation the c/i0 channel carries the commands and indications between the S3C2500B and layer-1 device to control the activation/deactivation procedures. c/i0 channel access may be arbitrated via in the tic bus access protocol. the cpu have access to c/i0 channel by using two registers, iom2citd0(in transmit direction) and iom2cird0(in receive direction). the data written to iom2citd0 is continuously transmitted until new data is to be sent. the iom2 receiver generates interrupt whenever the receive data changes and is stable for two frames (double last look criterion). the c/i1 channel carries the real time status information between the S3C2500B and iom2 devices other than layer-1 device. the c/i1 channel is accessed via iom2citd1 and iom2cird1. S3C2500B iom2 contr oller 9 - 7 9.3.7.5 tic bus access the tic bus capability enables more than one device to access iom2 bus. the arbitration mechanism is implemented in the last byte of channel2 of iom2 interface. this allows external communication controllers (up to 7) to access the c/i0 and d channel in the channel0 of iom2 interface. the tic bus access is enabled by setting the ticen to "1". an access request to the tic bus may either be generated by the software (cpu access to the c/i channel) or by the hdlc controller (transmission of hdlc frame in the d channel). a software access request to the bus is activated by setting the breq bit to "1". in the case of an access request, the iom2 controller checks the bac (bit 5 of du last byte of channel2) for the status "bus free" (bac = 1). if the bus is free, the iom2 controller starts to transmit its own tic bus address programmed in the iom2tba register. when the iom2 controller transmits the tic bus address tad on du, it compares the bit with the value on du. if any bit mismatches, that is, a sent bit set to "1" is read back as "0", the iom2 controller withdraws immediately from the tic bus. if more than one device attempt to access the bus simultaneously, the one with the lowest address values wins. if all the tic bus address bits match, the tic bus is immediately occupied by the iom2 controller by setting the bac to "0" in the subsequent frame until the access request is withdrawn. figure 9-4 shows the channel2 of iom2 interface. bus access 0 = occupied 1 = accessible bac tad tic bus address figure 9-4. structure of last byte of channel 2 on du when the tic bus is occupied by one device, the bus is identified to other devices as occupied via the bac ("0"). after a successful bus access, the iom2 controller is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two consecutive frames. if none of the devices connected to the iom interface request access to the d and c/i channels, the tic bus address 7 will be present. the device with this address will therefore have access, by default, to the d and c/i channels. iom2 controller s3c 2500b 9- 8 the availability of the s/t interface d-channel is indicated in bit5 "stop/go" of the dd last byte of channel2 (figure 9-5). s/g a/b stop/go available/blocked figure 9-5. structure of last byte of channel 2 on dd the iom2 controller checks the s/g bit to determine if the d channel is available to access. if the d channel is available (s/g=0), an hdlc frame is transmitted. if the d channel is busy with other device, the iom2 controller should halt the transmission. bits 7 and 6 are the d channel echo bits from the s-interface (echo back the two d channel bits of the current frame) and are used to determine d channel collisions. the echo bits are compared with the sent d channel bits to determine if a collision has occurred. the iom2 controller does not support the a/b bit. 9.3.7.6 ic channel operation the iom2 controller can have access to two ic channels by reading the iom2icrd and writing the iom2ictd register. only one channel must be accessed at a time since the iom2 controller has registers for one channel. the ic channel0 is accessed by setting the icsel bit to "0". because the data output is open-drain, the unused ic channel and all high bits of the chosen ic channel are placed in a high-impedance state (unless used by an hdlc frame). 9.3.7.7 pin direction reversal the data signals on the iom2 bus are defined as data upstream (du) and data downstream (dd). in terminal mode, a device may be required to transmit both upstream and downstream, based on which channel is being transmitted at any one time. as a result, the actual data pins of the S3C2500B iom2 interface need to be both inputs and outputs. when the dbrev bit in iom2con is set, the du pin is used to receive downstream data and the dd pin is used to send upstream data. 9.3.7.8 strobe signals the optional iom2 signals, bcl and strb, are used by non-iom2 devices on the iom2 bus. bcl is a 1x clock running at 768 khz and used as the data clock. strb is used to specify a strobe of an appropriate time slot for non-iom2 device. the start and stop position of strb is programmed by iom2strb register S3C2500B iom2 contr oller 9 - 9 9.4 tsa (time slot assigner) 9.4.1 overview the S3C2500B includes three time-slot-assigners (tsa), which provide flexible data path control between the three hdlcs and external interfaces. a variety of data interface can be supported by the S3C2500B with the tsa : raw data communication equipment (dce), pulse code modulation (pcm) highway (non-multiplexed mode and multiplexed mode) and isdn oriented modular interface (iom2). each tsa can be programmed to select one between dce and pcm highway (non-multiplexed) interface. besides dce/pcm highway, interface a can afford iom2 interface to multiplex data from each hdlc channel on hdlca pad interface and interface b can afford pcm highway (multiplexed) interface to multiplex data from each hdlc channel on hdlcb pad interface. in dce interface, the internal hdlc can directly be connected to the external serial interface. in pcm highway and iom2 interface, the tsa is located between the hdlc and the external serial interface. by intervening in-between, the tsa provides the appropriate hdlc clocks during its programmed timeslot within an 8-khz frame. the tsa can support a maximum data rate of up to 10 mbps with hdlcs. in pcm highway interface, up to 156 time-slots can be supported with credible data transfer. although the S3C2500B can support up to 4096 bit positions (12bit programmable), this requires a lower frequency of fsc or a high frequency of clock rates. the iom2 is pin-multiplexed with hdlca pins and the pcm highway (multiplexed) is pin-multiplexed with hdlcb pin interface and the hdlcc pins are dedicated to dce interface. 9.4.2 tsa block diagram hdlca hdlcb hdlcc mux mux mux tsa iom2 tsa tsa dcea tdma dceb tdmb dcec tdmc dce/iom2/ pcm(non-multiplexed) interface dce/pcm(multiplexed)/ pcm(non-multiplexed) interface dce/ pcm(non-multiplexed) interface figure 9-6. tsa block diagram iom2 controller s3c 2500b 9- 10 9.4.3 hdlc external pin multiplexed signals hdlc external pins are multiplexed among the various operating modes. the mode bits in tsaxcon determines operating mode of each tsa and hdlc external pins are automatically configured according to mode bits as follows. table 9-1. hdlc external pin multiplexed signals channel external interface default signal dce pcm iom2 multiplexed non-multiplexed a dce_txca pcm_fsca iom2_fsc dce_txca dce_txda pcm_txda iom2_du dce_txda dce_rxca pcm_dcla iom2_dcl dce_rxca dce_rxda pcm_rxda iom2_dd dce_rxda b dce_txcb pcm_fscb pcm_fscb ? dce_txcb dce_txdb pcm_txdb pcm_txdb ? dce_txdb dce_rxcb pcm_dclb pcm_dclb ? dce_rxcb dce_rxdb pcm_rxdb pcm_rxdb ? dce_rxdb c dce_txcc pcm_fscc ? dce_txcc dce_txdc pcm_txdc ? dce_txdc dce_rxcc pcm_dclc ? dce_rxcc dce_rxdc pcm_rxdc ? dce_rxdc 9.4.4 operation the time slot assigner (tsa) controllers are configured as follows: 1. configure the tsaxcon register. ? define the start bit position for each tsa. ? define the stop bit position for each tsa. ? determine operating mode for e ach tsa (dce, pcm highway (non-multiplexed or multiplexed), and iom2 interface) 2. enable tsa by setting tsaen bit in iom2con[13] to "1". 3. program each intended hdlc channel 9.4.4.1 clock divide in pcm mode, the tsa provides each hdlc channel with proper clock according to its programmed timeslot. in this process, the clock frequency is either the same as or 1/2 times that of the external clock. when the divide bit in tsaxcon is set to "1", each hdlc channel is provided with half frequency clock of external clock and the tx data is shifted out every two external clock. when the divide bit in tsaxcon is "0", each hdlc channel is provided with the external clock and the tx data is shifted out every one clock. S3C2500B iom2 contr oller 9 - 11 9.5 iom2 special registers table 9-2. iom2 special registers register address r/w description reset value iom2con 0xf0130000 r/w control register 0x00000000 iom2stat 0xf0130004 r/w status register 0x00000080 iom2inten 0xf0130008 r/w interrupt enable register 0x00000000 iom2tba 0xf013000c r/w tic bus address 0x00000007 iom2ictd 0xf0130010 r/w ic channel tx buffer 0x000000ff iom2icrd 0xf0130014 r/w ic channel rx buffer 0x00000000 iom2citd0 0xf0130018 r/w c/i0 channel tx buffer 0x0000000f iom2cird0 0xf013001c r/w c/i0 channel rx buffer 0x00000000 iom2citd1 0xf0130020 r/w c/i1 channel tx buffer 0x0000003f iom2cird1 0xf0130024 r/w c/i1 channel rx buffer 0x00000000 iom2mtd 0xf0130028 r/w monitor channel tx buffer 0x000000ff iom2mrd 0xf013002c r/w monitor channel rx buffer 0x000000ff tsaacon 0xf0130030 r/w tsa a control register 0x00000000 tsabcon 0xf0130034 r/w tsa b control register 0x00000000 tsaccon 0xf0130038 r/w tsa c control register 0x00000000 iom2strb 0xf013003c r/w iom2 strobe set register 0x00000000 iom2 controller s3c 2500b 9- 12 9.5.1 iom2con register table 9-3. iom2con register (control register) register address r/w description reset value iom2con 0xf0130000 r/w control register 0x00000000 bit number bit name description [0] iom2 enable (iom2en) 0 = disable, 1 = enable [1] data bus reverse (dbrev) 0 = dd: downstream, du: upstream 1 = dd: upstream, du: downstream [2] monitor channel enable (men) 0 = monitor channel is disabled 1 = monitor channel transmission is allowed [3] tic bus enable (ticen) 0 = tic bus access is disabled 1 = tic bus access is enabled [4] d channel collision control enable (dcolen) 0 = ignore the echo bit 1 = the echo bit from the transceiver is compared to detect d channel collision. [5] monitor channel abort request (mar) 0 = auto cleared after transmitting mr abort 1 = the remote transmitter is forced to abort the current transmission. this enforces the local receiver to set the mr bit to "1". [6] monitor channel address valid (mav) 0 = cleared before the first byte is received. 1 = the cpu indicates the monitor receiver that the first byte address received is valid. [7] monitor channel sends end-of- message (mtxeom) 0 = cleared after the eom is sent. 1 = the monitor transmitter is forced to send an end- of-message(eom). [8] bus request for c/i0 (breq) 0 = the tic bus is released. 1 = the iom2 controller starts to access the tic bus for c/i0 channel. [9] monitor channel select (msel) 0 = monitor channel 0 is selected 1 = monitor channel 1 is selected [10] ic channel select (icsel) 0 = ic0 is selected 1 = ic1 is selected [11] awake request (awake) 0 = normal 1 = the iom2 controller pulls du to low, which requests the transceiver to deliver dclk. [12] test loop back (loop) 0 = normal 1 = the dd and du are internally connected together. the data from the transceiver will not be forwarded to the iom2 controller. [13] tsa enable 0 = tsa disabled 1 = tsa enable [14] transceiver type select(ttsel) 0 = transceiver that transmit dcl rising edge after fsc rising edge 1 = transceiver that transmit dcl rising edge before fsc rising edge S3C2500B iom2 contr oller 9 - 13 [0] iom2 enable (iom2en) 0 = disable 1 = enable [1] data bus reverse (dbrev) 0 = du: upstream dd: downstream 1 = du: downstream dd: upstream [2] monitor enable (men) 0 = disable 1 = enable [3] tic bus enable (ticen) 0 = disable 1 = enable [4] d-channel collision enable (dcolen) 0 = disable 1 = enable [5] monitor abort request (mar) 0 = normal 1 = abort request asserted [6] monitor address valid (mav) 0 = address received is not valid 1 = address received is valid [7] monitor transmit end of frame (mtxeom) 0 = normal 1 = monitor sends end-of-frame [8] bus request (breq) 0 = normal 1 = request tic bus to send c/i0 data [9] monitor channel select (msel) 0 = monitor 0 selected 1 = monitor 1 selected [10] ic channel select (icsel) 0 = ic 0 selected 1 = ic 1 selected [11] awake (awake) 0 = normal 1 = request the transceiver to deliver dcl [12] loopback (loop) 0 = normal 1 = loopback mode [13] tsa enable (tsaen) 0 = disable 1 = enable [14] transceiver type select (ttsel) 0 = transceiver that transmit dcl rising edge after fsc rising edge 1 = transceiver that transmit dcl rising edge beforefsc rising edge l o o p m a r d c o l e n a w a k e i c s e l m s e l b r e q m t x e o m m a v m e n d b r e v t i c e n i o m 2 e n t s a e n t t s e l 31 0 3 4 5 1 2 10 9 13 12 11 8 7 6 15 14 figure 9-7. iom2 control register iom2 controller s3c 2500b 9- 14 9.5.2 iom2 status register table 9-4. iom2stat register (status register) register address r/w description reset value iom2stat 0xf0130004 r/w status register 0x00000080 bit number bit name description [0] c/i0 channel buffer available (ci0ba) 0 = c/i0 receive data is not valid 1 = iom2ci0rd is valid to read [1] reserved [2] c/i1 channel buffer available (ci1ba) 0 = c/i1 receive data is not valid 1 = iom2ci1rd is valid to read [3] reserved [4] monitor channel receive end-of- message (mrxeom) 0 = the eom has not arrived. 1 = the eom has arrived on the monitor channel, which indicates that the current message transfer has concluded. [5] monitor channel receive abort (mrxabt) 0 = normal 1 = the remote receiver has sent abort request because of transmission errors. in this case, the local transmitter should respond to this by sending eom (mx=1 during more than two frames). [6] monitor channel collision detected (mcol) 0 = normal 1 = the monitor channel collision has occurred. [7] monitor channel tx buffer available (mtxba) 0 = cleared when the iom2mtd is written. 1 = a new data can be written to iom2mtd. [8] monitor channel rx buffer available (mrxba) 0 = cleared when the iom2mrd is read. 1 = a new data has received on the monitor channel. [9] monitor channel tx abort received (mtxabt) 0 = normal 1 = mointor channel tx abort is received. when the rx channel receives an abrupt disruption of handshake procedure, not a normal termination of handshake, during monitor channel transmission, this bit is set to "1". [10] ic channel buffer available (icba) 0 = cleared when the iom2icrd is read. 1 = a new data has received on the ic channel. [11] iom2 bus alive (alive) 0 = the iom2 bus is in the inactive state (dcl=1). 1 = the iom2 bus is in the active state (dclk is clocking). [12] new frame sync. newfsc 0 = cleared by cpu 1 = fsc detected S3C2500B iom2 contr oller 9 - 15 [0] ci 0 buffer available (ci0ba) 0 = normal 1 = ci0 buffer available [1] reserved [2] ci 1 buffer available (ci1ba) 0 = normal 1 = ci1 buffer available [3] reserved [4] monitor received end of frame (mrxeom) 0 = normal 1 = monitor channel transmission terminated successfully [5] monitor received abort (mrxabt) 0 = normal 1 = monitor channel transmission aborted [6] monitor collision (mcol) 0 = normal 1 = monitor channel collision detected [7] monitor transmit buffer available (mtxba) 0 = normal 1 = monitor tx buffer empty [8] monitor receive buffer available (mrxba) 0 = normal 1 = monitor rx buffer data ready [9] monitor transmit abort detected (mtxabt) 0 = normal 1 = monitor channel tx abort received [10] ic buffer available (icba) 0 = normal 1 = ic buffer available [11] alive (alive) 0 = iom2 bus is in the inactive state (dcl=1). 1 = iom2 bus is in the active state (dclk is clocking). [12] newfsc (newfsc) 0 = normal 1 = fsc rising edge detected 31 0 3 4 5 1 2 10 9 13 12 11 8 7 6 m r x a b t m r x e o m a l i v e i c b a m t x a b t m r x b a m t x b a m c o l c i 1 b a c i 0 b a n e w f s c figure 9-8. iom2 status register iom2 controller s3c 2500b 9- 16 9.5.3 iom2 interrupt enable register table 9-5. iom2inten register (interrupt enable register) register address r/w description reset value iom2inten 0xf0130008 r/w interrupt enable register 0x00000000 bit number bit name description [0] ci0baie c/i0 channel buffer available interrupt enable [1] [2] ci1baie c/i1 channel buffer available interrupt enable [3] [4] mrxeomie monitor channel receive end-of-message interrupt enable [5] mrxabtie monitor channel receive abort interrupt enable [6] mcolie monitor channel collision detected interrupt enable [7] mtxbaie monitor channel tx buffer available interrupt enable [8] mrxbaie monitor channel rx buffer available interrupt enable [9] mtxabtie monitor channel tx abort interrupt enable [10] icbaie ic channel buffer available interrupt enable [11] aliveie iom2 bus alive interrupt enable [12] newfscie new frame sync interrupt enable S3C2500B iom2 contr oller 9 - 17 [0] ci 0 buffer available interrupt enable (ci0baie) 0 = disable 1 = enable [1] reserved [2] ci 1 buffer available interrupt enable (ci1baie) 0 = disable 1 = enable [3] reserved [4] monitor received end of frame interrupt enable (mrxeomie) 0 = disable 1 = enable [5] monitor received abort interrupt enable (mrxabtie) 0 = disable 1 = enable [6] monitor collision interrupt enable (mcolie) 0 = disable 1 = enable [7] monitor transmit buffer available interrupt enable (mtxbaie) 0 = disable 1 = enable [8] monitor receive buffer available interrupt enable (mrxbaie) 0 = disable 1 = enable [9] monitor transmit abort detected interrupt enable (mtxabtie) 0 = disable 1 = enable [10] ic buffer available interrupt enable (icbaie) 0 = disable 1 = enable [11] alive interrupt enable (aliveie) 0 = disable 1 = enable [12] newfsc interrupt enable (newfscie) 0 = disable 1 = enable 31 0 3 4 5 1 2 10 9 13 12 11 8 7 6 m r x a b t i e m r x e o m i e a l i v e i e i c b a i e m t x a b t i e m r x b a i e m t x b a i e m c o l i e c i 1 b a i e c i 0 b a i e n e w f s c i e figure 9-9. iom2 interrupt enable register iom2 controller s3c 2500b 9- 18 9.5.4 iom2 tic bus address register table 9-6. iom2tba register (tic bus address register) register address r/w description reset value iom2tba 0xf013000c r/w tic bus address 0x00000007 bit number bit name description [2:0] tic bus address (tba) this field defines device-specific address used to gain access to tic bus for d and c/i0 channel. [31:3] reserved. 31 15 16 [2:0] tic bus address 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 2 tba 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-10. iom2 tic bus address register S3C2500B iom2 contr oller 9 - 19 9.5.5 iom2 ic channel transmit data register table 9-7. iom2ictd (iom2 ic channel transmit data register) register address r/w description reset value iom2ictd 0xf0130010 r/w ic channel transmit data 0x000000ff bit number bit name description [7:0] ictd transmit data [31:8] reserved. 31 15 16 [7:0] ic channel transmit data 0 18 17 12 13 14 9 10 11 7 8 ictd 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-11. iom2 ic channel transmit data register table 9-8. iom2icrd (iom2 ic channel receive data register) register address r/w description reset value iom2icrd 0xf0130014 r/w ic channel receive data 0x00000000 bit number bit name description [7:0] icrd receive data [31:8] reserved. 31 15 16 [7:0] ic channel receive data 0 18 17 12 13 14 9 10 11 7 8 icrd 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-12. iom2 ic channel receive data register iom2 controller s3c 2500b 9- 20 9.5.6 iom2 c/i0 channel transmit data register table 9-9. iom2citd0 (iom2 c/i0 channel transmit data register) register address r/w description reset value iom2citd0 0xf0130018 r/w c/i0 channel transmit data 0x0000000f bit number bit name description [3:0] citd0 this field includes the data to be transmitted on the c/i0 channel. the data is continuously transmitted until a new code is loaded. [31:4] reserved. 31 15 16 [3:0] c/i0 channel transmit data 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 citd0 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-13. iom2 c/i0 channel transmit data register table 9-10. iom2cird0 (iom2 c/i0 channel receive data register) register address r/w description reset value iom2cird0 0xf013001c r/w c/i0 channel receive data 0x00000000 bit number bit name description [3:0] cird0 this field includes the data received on the c/i0 channel. this data is sure to be valid by double last look criterion (valid during two successive frames). [31:4] reserved. 31 15 16 [3:0] c/i0 channel receive data 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 cird0 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-14. iom2 c/i0 channel receive data register S3C2500B iom2 contr oller 9 - 21 9.5.7 iom2 c/i1 channel transmit data register table 9-11. iom2citd1 (iom2 c/i1 channel transmit data register) register address r/w description reset value iom2citd1 0xf0130020 r/w c/i1 channel transmit data 0x0000003f bit number bit name description [5:0] citd1 this field includes the data to be transmitted on the c/i1 channel. the data is continuously transmitted until a new code is loaded. [31:6] reserved. 31 15 16 [5:0] c/i1 channel transmit data 0 18 17 12 13 14 9 10 11 6 7 8 5 citd1 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-15. iom2 c/i1 channel transmit data register 9.5.8 iom2 c/i1 channel receive data register table 9-12. iom2cird1 (iom2 c/i1 channel receive data register) register address r/w description reset value iom2cird1 0xf0130024 r/w c/i1 channel receive data 0x00000000 bit number bit name description [5:0] cird1 this field includes the data received on the c/i1 channel. this data is sure to be valid by double last look criterion (valid during two successive frames). [31:6] reserved. 31 15 16 [5:0] c/i1 channel receive data 0 18 17 12 13 14 9 10 11 6 7 8 5 cird1 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-16. iom2 c/i1 channel receive data register iom2 controller s3c 2500b 9- 22 9.5.9 iom2 monitor channel transmit data register table 9-13. iom2mtd (iom2 monitor channel transmit data register) register address r/w description reset value iom2mtd 0xf0130028 r/w monitor channel transmit data 0x000000ff bit number bit name description [7:0] mtxd this field includes the data to be transmitted on the monitor channel selected by msel if men = 1. [31:8] reserved. 31 15 16 [7:0] monitor channel transmit data 0 18 17 12 13 14 9 10 11 7 8 mtd 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-17. iom2 monitor channel transmit data register 9.5.10 iom2 monitor channel receive data register table 9-14. iom2mrd (iom2 monitor channel receive data register) register address r/w description reset value iom2mrd 0xf013002c r/w monitor channel receive data 0x00000000 bit number bit name description [7:0] mrxd this field includes the data received on the monitor channel selected by msel if men = 1. this data is sure to be valid by double last look criterion (valid during two successive frames). [31:8] reserved. 31 15 16 [7:0] monitor channel receive data 0 18 17 12 13 14 9 10 11 7 8 mrd 19 21 20 22 23 24 25 26 27 28 29 30 figure 9-18. iom2 monitor channel receive data register S3C2500B iom2 contr oller 9 - 23 9.5.11 tsa a control register table 9-15. tsaacon (tsa a control register) register address r/w description reset value tsaacon 0xf0130030 r/w tsa a control register 0x00000000 bit number bit name description [11:0] start the location of start bit of time slot assigned to hdlca [23:12] stop the location of stop bit of time slot assigned to hdlca [25:24] mode 00 = dce 01 = pcm highway (non-multiplexed) 10 = iom2 11 = pcm highway (multiplexed) [26] divide 0 = hdlc clock is the same clock as the external clock 1 = hdlc clock is 1/2 times the external clock [31:27] reserved. 31 [11:0] the location of start bit of time slot [23:12] the location of stop bit of time slot [25:24] mode 00 = dce 01 = pcm highway (non-multiplexed) 10 = iom2 11 = pcm highway (multiplexed) [26] divide 0 = 1 x clock mode 1 = 0.5 x clock mode 0 12 11 start 23 24 25 26 27 28 29 30 div mode stop figure 9-19. tsa a control register iom2 controller s3c 2500b 9- 24 9.5.12 tsa b control register table 9-16. tsabcon (tsa b control register) register address r/w description reset value tsabcon 0xf0130034 r/w tsa b control register 0x00000000 bit number bit name description [11-0] start the location of start bit of time slot assigned to hdlcb [23-12] stop the location of stop bit of time slot assigned to hdlcb [25-24] mode 00 = dce 01 = pcm highway (non-multiplexed) 10 = iom2 11 = pcm highway (multiplexed) [26] divide 0 = hdlc clock is the same clock as the external clock 1 = hdlc clock is 1/2 times the external clock [31-27] reserved. 31 [11:0] the location of start bit of time slot [23:12] the location of stop bit of time slot [25:24] mode 00 = dce 01 = pcm highway (non-multiplexed) 10 = iom2 11 = pcm highway (multiplexed) [26] divide 0 = 1 x clock mode 1 = 0.5 x clock mode 0 12 11 start 23 24 25 26 27 28 29 30 div mode stop figure 9-20. tsa b control register S3C2500B iom2 contr oller 9 - 25 9.5.13 tsa c control register table 9-17. tsaccon (tsa c control register) register address r/w description reset value tsaccon 0xf0130038 r/w tsa c control register 0x00000000 bit number bit name description [11:0] start the location of start bit of time slot assigned to hdlcc [23:12] stop the location of stop bit of time slot assigned to hdlcc [25:24] mode 00 = dce 01 = pcm highway (non-multiplexed) 10 = iom2 11 = pcm highway (multiplexed) [26] divide 0 = hdlc clock is the same clock as the external clock 1 = hdlc clock is 1/2 times the external clock [31:27] reserved. 31 [11:0] the location of start bit of time slot [23:12] the location of stop bit of time slot [25:24] mode 00 = dce 01 = pcm highway (non-multiplexed) 10 = iom2 11 = pcm highway (multiplexed) [26] divide 0 = 1 x clock mode 1 = 0.5 x clock mode 0 12 11 start 23 24 25 26 27 28 29 30 div mode stop figure 9-21. tsa c control register iom2 controller s3c 2500b 9- 26 9.5.14 iom2strb (strobe register) table 9-18. iom2strb (strobe register) register address r/w description reset value iom2strb 0xf013003c r/w strobe register 0x00000000 bit number bit name description [7:0] start the location of start bit of time slot assigned to strb [15:8] stop the location of stop bit of time slot assigned to strb [31:16] reserved 31 15 16 [7:0] the location of start bit of time slot [15:8] the location of stop bit of time slot 0 18 17 7 8 start 19 21 20 22 23 24 25 26 27 28 29 30 stop figure 9-22. iom2 strobe register S3C2500B usb controller 10- 1 10 usb function controller 10.1 overview usb products are easy to use for end users. electrical details, such as bus termination, are isolated from end users and plug and play is supported. there?re other merits for users; self identifying peripherals, automatic mapping function to driver, auto configuration, dynamically attach and detach and reconfiguration, and so on. usb architecture is suitable for wide range of workloads and applications. various device can be attached which bandwidths ranging from a few kbps (bits per sec) to several mbps. this also supports multiple connections at the same time, up to 127 physical devices, including usb hub. usb architecture can be used for real-time data transfer, such as audio and video, with isochronous transfer. on the other hand, asynchronous transfer type is supported over the same set of wires. other merits of usb architecture are listed below: wide range of packet size wide range of device data rates by accommodating packet buffer size and latencies error handling / fault recovery mechanism built into protocol support for identification of faulty devices suitable for development of low cost peripherals low cost cables and connectors easy architecture upgrade with multiple usb host controllers in a system usb controller s3c2 500b 10- 2 10.2 features important features of the s3c2510 usb block are as follows: fully compliant to usb 1.1 specification supports only full speed function (12mbps) complete device configuration compatible with both openhci and intel uhci standards support 5 endpoints (control, 2 interrupt, 2 data endpoints) ep0: 64 bytes control/status endpoint ep1/2: 32 bytes interrupt endpoint (in/out) ep3/4: 64 bytes data endpoints (in/out) 32/64 byte data endpoints support gdma interface supports bulk data transfer crc16 generation and crc5/crc16 checking suspend/resume control disconnect state generation. S3C2500B usb controller 10- 3 10.3 function descriptions 10.3.1 usb bus topology and physical connection there are two kinds of cable connectors, a type for hub downstream port, and b type for device(or called as function, node). so end users easily connect cable. usb cable physically contains 4 lines, 2 lines for signal d+/d-, 2 lines for power-supply to bus-powered device such as mouse, keyboard. usb 1.1 spec compatibly manufactured cables could be used for usb 2.0 compliant product. all cables in markets are not made to fit 1.1 spec correctly, but there is no problem for 1.1 or 1.0 compliant products except 2.0 products. usb architecture uses bus tree topology. there is only one host controller in a root and the hub which lies right next to host controller is called root hub. ibm-compatible pc with 2 usb ports means that there?re one host and a root hub which has one upstream port from host controller and two downstream ports outside pc. south-bridge chips in pcs, such as 82371ab/eb, contains usb host controller and root hub. compound devices can be designed; a monitor that has a crt and a hub. mouse or keyboard is attached to downstream ports of this monitor-inside hub. maximum 5 hubs can lie between a host controller and a function because of signal delay. 10.3.2 frame generation frame divides time slot into 1ms units and the separators are sofs (start-of-frames). host broadcasts one sof packet at a normal rate of once every 1.00ms 0.0005ms. all iso eps in all devices can one in/out per 1ms time period. the sof packet consists of sync, pid, frame number, crc. the host transmits the lower 11 bits of the current frame number in each sof token transmission. when requested from the host controller, the current frame number is the frame number in existence at the time the request was fulfilled. the current frame number as returned by the host (host controller or hcd) is at least 32 bits, although the host controller itself is not required to maintain more than 11 bits. frame n-1 sof sof sof sof eof interval (frame n-1) frame n eof interval (frame n) frame n+1 eof interval (frame n+1) figure 10-1. sof packets all full-speed functions, including hubs, receive the sof packets. frame timing sensitive functions, which do not need to keep track of frame number (e.g. a hub), need only decode the sof pid; they can ignore the frame number and its crc. if a function needs to track frame number, it must comprehend both the pid and the time stamp. full-speed devices that have no particular need for bus-timing information may ignore the sof packet. the sof token holds the highest priority access to the bus. babble circuitry in hubs electrically isolates any active transmitters during the end-of-frame (eof) interval, providing an idle bus for the sof transmission. usb controller s3c2 500b 10- 4 stereo audio low speed bulk stereo audio stereo audio stereo audio stereo audio stereo audio stereo audio stereo audio stereo audio stereo audio low speed bulk bulk bulk bulk bulk bulk bulk bulk bulk sof tx voice rx voice tx line rx line interrupt, control, low speed scanner figure 10-2. usb 1.1 frame model 10.3.3 packet formats all packets begin with a synchronization (sync) field, which is a coded sequence that generates a maximum edge transition density. the sync field appears on the bus as idle followed by the binary string ?kjkjkjkk?, in its nrzi encoding. it is used by the input circuitry to align incoming data with the local clock and is defined to be eight bits in length. sync serves only as a synchronization mechanism and is not shown in the following packet diagrams. the last two bits in the sync field are a marker that is used to identify the end of the sync field and, by inference, the start of the pid. the pid indicates the type of packet and, by inference, the format of the packet and the type of error detection applied to the packet. the host and all functions must perform a complete decoding of all received pid fields. any pid received with a failed check field or which decodes to a non-defined value is assumed to be corrupted and it, as well as the remainder of the packet, is ignored by the packet receiver. if a function receives an otherwise valid pid for a transaction type or direction that it does not support, the function must not respond. for example, an in-only endpoint must ignore an out token. function endpoints are addressed using two fields: the function address field and the endpoint field. the function address (addr) field specifies the function, via its address, that is either the source or destination of a data packet, depending on the value of the token pid. cyclic redundancy checks (crcs) are used to protect all non-pid fields in token and data packets. in this context, these fields are considered to be protected fields. the pid is not included in the crc check of a packet containing a crc. all crcs are generated over their respective fields in the transmitter before bit stuffing is performed. handshake packets are used to report the status of a data transaction and can return values indicating successful reception of data, command acceptance or rejection, flow control, and halt conditions. S3C2500B usb controller 10- 5 pid 8 bits addr endp crc5 pid data crc16 pid pid frame number crc5 7 bits 4 bits 5 bits 8 bits 0-1023 bytes 16 bits token (in/out) data (toggle) 8 bits handshake/low speed preamble 8 bits 11 bits 5 bits start of frame figure 10-3. usb frame format 10.3.4 bit stuffing and nrzi coding the usb employs nrzi data encoding when transmitting packets. in nrzi encoding, a ?1? is represented by no change in level and a ?0? is represented by a change in level. the high level represents the j state on the data lines in nrzi encoding and j state means that d+ is 5v and d- is 0v. a string of zeros causes the nrzi data to toggle each bit time. a string of ones causes long periods with no transitions in the data. in order to ensure adequate signal transitions, the transmitting device employs bit stuffing when sending a packet on usb. a zero is inserted after every six consecutive ones in the data stream before the data is nrzi encoded, to force a transition in the nrzi data stream. this gives the receiver logic a data transition at least once every seven bit times to guarantee the data and clock lock. bit stuffing is enabled beginning with the sync pattern and throughout the entire transmission. the data ?one? that ends the sync pattern is counted as the first one in a sequence. bit stuffing by the transmitter is always enforced, without exception. if required by the bit stuffing rules, a zero bit will be inserted even if it is the last bit before the end-of-packet (eop) signal. 10.3.5 bulk transactions the bulk transfer type is designed to support devices that need to communicate relatively large amounts of data at highly variable times where the transfer can use any available bandwidth. requesting a pipe with a bulk transfer type provides the requester with the following: ? access to the usb on a bandwidth-available basis ? retry of transfers, in the case of occasional delivery failure due to errors on the bus ? guaranteed delivery of data, but no guarantee of bandwidth or latency. bulk transfers occur only on a bandwidth-available basis. for a usb with large amounts of free bandwidth, bulk transfers may happen relatively quickly; for a usb with little bandwidth available, bulk transfers may trickle out over a relatively long period of time. a bulk pipe is a stream pipe and, therefore, always has communication flowing either into or out of the host for a given pipe. if a device requires bi-directional bulk communication flow, two bulk pipes must be used, one in each direction. usb controller s3c2 500b 10- 6 10.3.6 control transactions control transfers are bursty, non-periodic, host software-initiated request/response communication, typically used for command/status operations. control transfers allow access to different parts of a device. control transfers are intended to support configuration/command/status type communication flows between client software and its function. a control transfer is composed of a setup bus transaction moving request information from host to function, zero or more data transactions sending data in the direction indicated by the setup transaction, and a status transaction returning status information from function to host. the status transaction returns ?success? when the endpoint has successfully completed processing the requested operation. control transfers are supported via bi-directional communication flow over message pipes. as a consequence, when a control pipe is configured, it uses both the input and output endpoint with the specified endpoint number. 10.3.7 isochronous transactions in non-usb environments, isochronous transfers have the general implication of constant-rate, error-tolerant transfers. in the usb environment, requesting an isochronous transfer type provides the requester with the following: ? guaranteed access to usb bandwidth with bounded latency ? guaranteed constant data rate through the pipe as long as data is provided to the pipe ? in the case of a delivery failure due to error, no retrying of the attempt to deliver the data. while the usb isochronous transfer type is designed to support isochronous sources and destinations, it is not required that software using this transfer type actually be isochronous in order to use the transfer type. an isochronous pipe is a stream pipe and is, therefore, always uni-directional. an endpoint description identifies whether a given isochronous pipe?s communication flow is into or out of the host. if a device requires bi- directional isochronous communication flow two isochronous pipes must be used, one in each direction. 10.3.8 interrupt transactions the interrupt transfer type is designed to support those devices that need to send or receive small amounts of data infrequently, but with bounded service periods. requesting a pipe with an interrupt transfer type provides the requester with the following: ? guaranteed maximum service period for the pipe ? retry of transfer attempts at the next period, in the case of occasional delivery failure due to error on the bus. an interrupt pipe is a stream pipe and is therefore always uni-directional. an endpoint description identifies whether a given interrupt pipe?s communication flow is into or out of the host. S3C2500B usb controller 10- 7 10.4 usb block descriptions 10.4.1 usb block overview usb block is compatible with usb spec 1.1. there're 5 eps (endpoint) with ep0 for control transfer. this block uses two input clocks, 133mhz and 48mhz. 133mhz clock is used to special registers access and usb-to-system bus interfacing. 48mhz clock is used for sie. 12mhz clock is generated from 48mhz and used for transmitting data throughout physical cable. fiq / irq interrupt routine should be used for usb service. max packet size is programmable with special registers. transceiver sie i/f 8 8 mux apb i/f apb bus 32 endpoint 0 fifo endpoint 1 fifo endpoint 2 fifo endpoint 3 fifo endpoint 4 fifo general function interface special registers sie 32 32 8 d+(out) d-(out) d+(in) d-(in) rxd figure 10-4. usb core block diagram 10.4.2 sie (serial interface engine) block the sie is the front-end of this hardware and handles most of the protocol described in chapter 8 of the usb specification. the sie typically comprehends signaling up to the transaction level. the functions that it handles could include: packet recognition, transaction sequencing sop, eop, reset, resume signal detection/generation clock/data separation nrzi data encoding/decoding and bit-stuffing crc generation and checking (token and data) packet id (pid) generation and checking/decoding serial-parallel/parallel-serial conversion usb controller s3c2 500b 10- 8 sie transceiver fun_sync_detect rxd fun_crc crc_out nrzi_dec_out fun_rst_detect vpin vmin fun_dpll dpll_rxd rxd fun_eop_detect vpin vmin xrxd syn_vpin rxd fun_pid_dec shiftreg_out[7:0] fun_shiftreg nrzi_dec_out dpll_rxd tx_mux_out[7:0] shiftreg_out[7:0] fun_bit_stuff vpout vmout data_in fun_tx_mux tx_mux_out[7:0] tx_buf_out[7:0] rx_data[7:0] tx_data figure 10-5. sie block diagram S3C2500B usb controller 10- 9 10.5 usb special registers the usb special registers are defined as read-write or read-only or write-only registers according to the direction of information flow. the addresses of these registers are shown in table 10-1. table 10-1. usb registers register address r/w description reset value usbfa 0xf00e0000 r/w usb function address register 0x00000000 usbpm 0xf00e0004 r/w usb power management register 0x00000000 usbintr 0xf00e0008 r/w usb interrupt register 0x00000000 usbintre 0xf00e000c r/w usb interrupt enable register 0x0000041f usbfn 0xf00e0010 r usb frame number register 0x00000000 usbdisconn 0xf00e0014 r/w usb disconnect timer register 0x00000001 usbep0csr 0xf00e0018 r/w usb endpoint 0 common status register 0x00000001 usbep1csr 0xf00e001c r/w usb endpoint 1 common status register 0x00000401 usbep2csr 0xf00e0020 r/w usb endpoint 2 common status register 0x00000401 usbep3csr 0xf00e0024 r/w usb endpoint 3 common status register 0x00000401 usbep4csr 0xf00e0028 r/w usb endpoint 4 common status register 0x00000401 0xf00e002c reserved usbwcep0 0xf00e0030 r/w usb write count register for endpoint 0 0x00000000 usbwcep1 0xf00e0034 r/w usb write count register for endpoint 1 0x00000000 usbwcep2 0xf00e0038 r/w usb write count register for endpoint 2 0x00000000 usbwcep3 0xf00e003c r/w usb write count register for endpoint 3 0x00000000 usbwcep4 0xf00e0040 r/w usb write count register for endpoint 4 0x00000000 0xf00e0044 - 0xf00e007c reserved usbep0 0xf00e0080 r/w usb endpoint 0 fifo undefined usbep1 0xf00e0084 r[w] usb endpoint 1 fifo undefined usbep2 0xf00e0088 r[w] usb endpoint 2 fifo undefined usbep3 0xf00e008c r[w] usb endpoint 3 fifo undefined usbep4 0xf00e0090 r[w] usb endpoint 4 fifo undefined note: the mark of ?r[w]? in r/w column means that each register can be set in read or write mode, but once it is set to one mode, it cannot operate in the other mode. for example, usbep1 is set to ?r? in setup time, it can be read but not be written. so, if you want to write something in usbep1 after it is set to r mode, you must re-setup the register to 'w' mode. usb controller s3c2 500b 10- 10 10.5.1 usb function address register this register maintains the usb device address assigned by the host. the mcu writes the value received through a set_address descriptor to this register. this address is used for the next token. table 10-2. usbfa register register address r/w description reset value usbfa 0xf00e0000 r/w usb function address register 0x00000000 table 10-3. usbfa register description bit number bit name mcu usb description [6:0] usb function address field (usbfaf) r/w r the mcu write the address to these bits. [7] usb address update (usbaup) s r/c the mcu sets this bit whenever it updates the usb function address field (usbfaf) in this register. the usbfaf is used after the status phase of a control transfer, which is signaled by the clearing of the data end bit in the endpoint 0 csr. [31:8] reserved S3C2500B usb controller 10- 11 31 0 7 faf [6:0] function address field (faf) [7] address update (aup) [31:8] reserved a u p 6 8 figure 10-6. usbfa register usb controller s3c2 500b 10- 12 10.5.2 usb power management register this register is used for suspend, resume, reset and data-swapping signaling. the different bits in this register are explained below: table 10-4. usbpm register register address r/w description reset value usbpm 0xf00e0004 r/w usb power management register 0x00000000 table 10-5. usbpm register description bit number bit name mcu usb description [0] suspend enable (suse) r/w r 0 = disable suspend mode (default). 1 = enable suspend mode if this bit is a zero, the device will not enter suspend mode. [1] suspend mode (susm) r/c r/w this bit is set by the usb when it enters suspend mode. it is cleared under the following conditions: ? the mcu clears the usb resume bit, to end resume signaling. ? the mcu reads usb interrupt register for the usb resume interrupt. [2] resume (ru) r/w r the mcu sets this bit for a duration of 10ms(maximum of 15ms) to initiate a resume signaling. the usb generates resume signaling while this bit is set in suspend mode. [3] reset (rst) r s the usb set this bit if reset signaling is received from the host. this bit remains set as long as reset signaling persists on the bus. [4] tx data swap r/w r 0 = disable tx data swap. (from usb to sie) 1 = enable tx data swap. if this bit is a one, the device will swap transmitted data. [5] rx data swap r/w r 0 = disable rx data swap. (from sie to usb) 1 = enable rx data swap. if this bit is a one, the device will swap received data. [6] reserved [7] iso update (isou) r/w r used for iso mode only. if set, gfi waits for a sof token from the time usbinrdy was set to send the packet. if an in token is received before a sof token, then a zero length data packet will be sent. [31:8] reserved S3C2500B usb controller 10- 13 31 0 1 2 3 7 [0] suspend enable (suse) 0 = suspend mode disable 1 = suspend mode enable [1] suspend mode (susm) 0 = normal operation 1 = suspend state [2] resume (ru) 0 = normal or suspend state 1 = resume signal generation in suspend state [3] reset (rst) 0 = normal operation 1 = reset received state [4] tx data swap (tds) 0 = normal operation 1 = transmit data swap [5] rx data swap (rds) 0 = normal operation 1 = receive data swap [6] reserved [7] iso update (isou) 0 = iso data updated (zero data packet send) 1 = iso data updated [31:8] reserved s u s e r s t i s o u s u s m r u t d s r d s 4 6 8 5 figure 10-7. usbpm register usb controller s3c2 500b 10- 14 10.5.3 usb interrupt register there?re five endpoints (ep0 - ep4) each bit in this register corresponds to the respective endpoint number. all interrupts corresponding to endpoints whose direction is programmable (mode = in/out), are mapped to this register. this register maintains interrupt status of bus signaling condition viz. suspend resume reset disconnect table 10-6. usbintr register register address r/w description reset value usbintr 0xf00e0008 r/w usb interrupt register 0x00000000 S3C2500B usb controller 10- 15 table 10-7. usbintr register description bit number bit name mcu usb description [0] ep0interrupt (ep0i) r/c s this bit corresponds to endpoint 0 interrupt. the usb sets this bit under the following conditions: 1. ordy bit is set. 2. inrdy bit is cleared. 3. ststall bit is set. 4. setend bit is set. 5. dend bit is cleared (indicates end of control transfer) [4:1] ep1interrupt - ep4interrupt (ep1i - ep4i) r/c s for bulk endpoints: the usb sets this bit under the following conditions: 1. iinrdy bit is cleared. 2. fifo is flushed. 3. oststall/ iststall is set. for iso endpoints: the usb sets this bit under the following conditions: 1. iunder bit is set. 2. iinrdy bit is cleared. 3. fifo is flushed. 4. oststall/ iststall is set. note: conditions 1 and 2 are mutually exclusive [7:5] reserved [8] suspend interrupt (susi) r/c s the usb sets this bit when it receives suspend signaling. this bit is set whenever there is no activity for 3ms on the bus. thus, if the mcu does not stop the clock after the first suspend interrupt, it will be continue to be interrupted every 3ms as long as there is no activity on the usb bus. by default this interrupt is disabled. [9] resume interrupt (resi) r/c s the usb sets this bit, when it receive resume signaling, while in suspend mode. if the resume is due to a usb reset, then the mcu is first interrupted with a resume interrupt. once the clocks resume and the se0 condition persists for 3ms, usb reset interrupt will be asserted. [10] reset interrupt (rsti) r/c s the usb sets this bit, when it receives reset signaling. [11] disconnect interrupt (disci) r/w c the usb sets this bit, when it finishes disconnect operation. [31:12] reserved usb controller s3c2 500b 10- 16 11 31 0 1 2 3 4 [0] ep0 interrupt (ep0i) 0 = no ep0 interrupt 1 = ep0 interrupt generated [1] ep1 interrupt (ep1i) 0 = no ep1 interrupt 1 = ep1 interrupt generated [2] ep2 interrupt (ep2i) 0 = no ep2 interrupt 1 = ep2 interrupt generated [3] ep3 interrupt (ep3i) 0 = no ep3 interrupt 1 = ep3 interrupt generated [4] ep4 interrupt (ep4i) 0 = no ep4 interrupt 1 = ep4 interrupt generated [7:5] reserved [8] suspend interrupt (susi) 0 = no suspend interrupt 1 = suspend interrupt generated [9] resume interrupt (resi) 0 = no resume interrupt 1 = resume interrupt generated [10] reset interrupt (rsti) 0 = no reset interrupt 1 = reset interrupt generated [11] disconnect interrput (disci) 0 = no interrupt 1 = interrupt generated after disconnect operation [31:12] reserved 8 9 10 e p 0 i s u s i r e s i r s t i e p 1 i e p 2 i e p 3 i e p 4 i d i s c i 12 7 5 figure 10-8. usbintr register S3C2500B usb controller 10- 17 10.5.4 usb interrupt enable register corresponding to each usb interrupt register (usbintr), there is an interrupt enable bit at usb interrupt enable register (usbintre). by default all interrupts are disbled. table 10-8. usbintre register register address r/w description reset value usbintre 0xf00e000c r/w usb interrupt enable register 0x0000041f table 10-9. usbintre register description bit number bit name mcu usb description [4:0] ep0 interrupt enable - ep4 interrupt enable (ep0ien - ep4ien) r/w r if bit = 0, the corresponding interrupt is disabled. if bit = 1, the corresponding interrupt is enabled. [7:5] reserved [8] suspend interrupt enable (susien) r/w r if bit = 0, the corresponding interrupt is disabled. if bit = 1, the corresponding interrupt is enabled. [9] reserved [10] reset interrupt enable (rstien) r/w r if bit = 0, the corresponding interrupt is disabled. if bit = 1, the corresponding interrupt is enabled. [11] disconnect interrupt enable (discien) r/w r if bit = 0, the corresponding interrupt is disabled. if bit = 1, the corresponding interrupt is enabled. [31:12] reserved usb controller s3c2 500b 10- 18 31 11 10 0 1 2 3 4 [0] endpoint 0 interrupt enable (ep0ien) 0 = endpoint 0 interrupt disable 1 = endpoint 0 interrupt enable [1] endpoint 1 interrupt enable (ep1ien) 0 = endpoint 1 interrupt disable 1 = endpoint 1 interrupt enable [2] endpoint 2 interrupt enable (ep2ien) 0 = endpoint 2 interrupt disable 1 = endpoint 2 interrupt enable [3] endpoint 3 interrupt enable (ep3ien) 0 = endpoint 3 interrupt disable 1 = endpoint 3 interrupt enable [4] endpoint 4 interrupt enable (ep4ien) 0 = endpoint 4 interrupt disable 1 = endpoint 4 interrupt enable [7:5] reserved [8] suspend interrupt enable (susien) 0 = suspend interrupt disable 1 = suspend interrupt enable [9] reserved [10] reset interrupt enable (rstien) 0 = reset interrupt disable 1 = reset interrupt enable [11] disconnect interrupt enable (discien) 0 = disconnect interrupt disable 1 = disconnect interrput enable [31:12] reserved 8 9 e p 0 i e n e p 1 i e n e p 2 i e n e p 3 i e n e p 4 i e n d i s c i e n s u s i e n r s t i e n 12 7 5 figure 10-9. usbintre register S3C2500B usb controller 10- 19 10.5.5 usb frame number register these registers maintain the frame number within sof packet. frame number within sof packet are 11bits. table 10-10. usbfn register register address r/w description reset value usbfn 0xf00e0010 r usb frame number register 0x00000000 table 10-11. usbfn register descriptions bit number bit name mcu usb description [10:0] frame number (fn) r w frame number from sof packet. [31:11] reserved 31 0 10 [10:0] frame number (fn) [31:11] reserved 11 fn figure 10-10. usbfn register usb controller s3c2 500b 10- 20 10.5.6 usb disconnect timer register this register turns usb bus into disconnected state. first, you set the disconnect interval time in the connect register. next, set the enable bit usbdisconn[31]. then, the disconnect logic keeps the line state in se0(single ended zero). after that interval time, any hub can detect our device as just connected. finally, bus reset will be started again. you could calculate wait time period by below cntvle table. table 10-12. cntvle table 22 21 ? ? 2 1 0 disconnect time (2 (cntvle+7) 20.8333ns) x x x x x 1 02.67 m s x x x x 1 0 05.33 m s x x x 1 0 0 10.67 m s x 1 0 0 0 0 05.59 s 1 0 0 0 0 0 11.18 s note: 'x' means "don't care". table 10-13. usbdisconn register register address r/w description reset value usbdisconn 0xf00e0014 r/w usb disconnect register 0x00000001 table 10-14. usbdisconn register description bit number bit name mcu usb description [22:0] count value (cntvle) r/w ? disconnect duration time value [30:23] reserved [31] disconnect operation start (disstrt) w c 0 = no operation 1 = both d+/d- go to 0 and all usb registers can?t be read/written until usbintr[11] is set. S3C2500B usb controller 10- 21 31 0 22 [22:0] count value (cntvle) [23:30] reserved [31] disconnet operation start (disstrt) 0 = no operation 1 = both d+/d- go to 0 and all usb registers r/w blocked. cntvle d i s s t r t 30 21 figure 10-11. usbdisconn register usb controller s3c2 500b 10- 22 10.5.7 usb endpoint 0 common status register this register includes the control bits, status bits, and max packet size value for endpoint 0. table 10-15. usbep0csr register register address r/w description reset value usbep0csr 0xf00e0018 r/w usb endpoint 0 common status register 0x00000001 table 10-16. usbep0csr register description bit number bit name mcu usb description [3:0] maxp size value (maxp) r/w r if maxp[3:0] is 0000, then maxpsize is 0 byte if maxp[3:0] is 0001, then maxpsize is 8 bytes if maxp[3:0] is 0010, then maxpsize is 16 bytes if maxp[3:0] is 0011, then maxpsize is 24 bytes if maxp[3:0] is 0100, then maxpsize is 32 bytes if maxp[3:0] is 0101, then maxpsize is 40 bytes if maxp[3:0] is 0110, then maxpsize is 48 bytes if maxp[3:0] is 0111, then maxpsize is 56 bytes if maxp[3:0] is 1000, then maxpsize is 64 bytes [6:4] reserved [7] maxp size settable (maxpset) w ? 0 = usbep0csr[3:0] isn't overwritten when mcu writes a 32bit value to usbep0csr register. 1 = usbep0csr[3:0] is overwritten. [23:8] reserved [24] out packet ready (ordy) r s this is a read only bit. the usb sets this bit once a valid token is written to the fifo. an interrupt is generated when the usb sets this bit. the mcu clears this bit by writing a 1 to the svordy [25] in packet ready (inrdy ) r/s c the mcu sets this bit after writing a packet of data into endpoint 0 fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so the mcu can load the next packet. for a zero length data phase, the mcu sets inrdy and dend at the same time. [26] sent stall (ststall) r/c s the usb sets this bit if a control transaction is ended due to a protocol violation. an interrupt is generated when this bit is set. S3C2500B usb controller 10- 23 table 10-16. usbep0csr register description (continued) bit number bit name mcu usb description [27] data end (dend) r/s c the mcu sets this bit: 1. after loading the last packet of data into the fifo, at the same time inrdy is set. 2. while it clears ordy after unloading the last packet of data. 3. for a zero length data phase, when it clears ordy and sets inrdy. [28] setup end (setend) r s this is a read only bit the usb sets this bit when a control transfer ends before dend is set. the mcu clears this bit by writing a 1 to the svset bit. when the usb sets this bit, an interrupt is generated to the mcu. when such a condition occurs, the usb flushes the fifo, and invalidates mcu access to the fifo. when mcu access to the fifo is invalidated, this bit is cleared. [29] send stall (sdstall) s clear the mcu writes a 1 to this bit at the same time it clears ordy, if it decodes a invalid token. the usb issues a stall handshake to the current control transfer. the mcu writes a 0 to end the stall condition. [30] serviced out ready (svordy) w clear the mcu writes a 1 to this bit to clear ordy [31] serviced setup end (svset) w clear the mcu writes a 1 to this bit to clear setend usb controller s3c2 500b 10- 24 31 30 29 28 27 26 25 24 0 3 7 [3:0] maxp value (maxp) [3:0]value x 8 = max packet size [6:4] reserved [7] maxp value setting enable (maxpset) 0 = maxp value isn't changed 1 = maxp value is changed [8:23] reserved [24] out packet ready (ordy) 0 = not received packet, or in in mode 1 = received packet from host [25] in packet ready (inrdy) 0 = not yet loaded packet to ep0 fifo, or in out mode 1 = loading packet to ep0 fifo completed [26] sent stall (ststall) 0 = no stall token is transmitted. 1 = control transaction is ended due to a protocol violation. [27] data end (dend) 0 = not dataend stage 1 = dataend stage [28] setup end (setend) 0 = normal operation state 1 = setup end stage [29] send stall (sdstall) 0 = normal operation state 1 = go to stall token transmt state [30] serviced out ready (svordy) 0 = no operation 1 = ordy bit clear [31] serviced setup end (svset) 0 = no operation 1 = setend bit clear 23 8 6 4 o r d y i n r d y s t s t a l l d e n d s e t e n d s d s t a l l s v o r d y s v s e t m a x p m a x p s e t figure 10-12. usbep0csr register S3C2500B usb controller 10- 25 10.5.8 usb endpoint 1 common status register this register includes the control bits, status bits, in/out status information, and max packet size value for endpoint 1. table 10-17. usbep1csr register register address r/w description reset value usbep1csr 0xf00e001c r/w usb endpoint 1 common status register 0x00000401 table 10-18. usbep1csr register description bit number bit name mcu usb description [2:0] maxp size value (maxp) r/w r if maxp[2:0] is 000, then maxpsize is 0 byte if maxp[2:0] is 001, then maxpsize is 8 bytes if maxp[2:0] is 010, then maxpsize is 16 bytes if maxp[2:0] is 011, then maxpsize is 24 bytes if maxp[2:0] is 100, then maxpsize is 32 bytes [6:3] reserved [7] maxp size set table (maxpset) w ? 0 = usbep1csr[2:0] isn?t overwritten when mcu writes a 32bit value to usbep1csr register. 1 = usbep1csr[2:0] is overwritten. [8] out mode, iso mode (oiso) r/w this bit is valid only when endpoint 1 is set to out. 0 = endpoint 1 will be bulk mode. 1 = endpoint 1 will be iso mode default = 0 [9] out mode, auto clear (oatclr) r/w r this bit is valid only when endpoint 1 is set to out. if set, whenever the mcu unloads last data in endpoint 1 fifo, oordy will automatically be cleared without any intervention form mcu. default = 0 [10] in/out mode selection (mode) r/w 0 = transfer direction will be out 1 = transfer direction will be in default = 1(in) [11] in mode, iso mode (iiso) r/w this bit is valid only when endpoint 1 is set to in. 0 = endpoint 1 will be bulk mode. 1 = endpoint 1 will be iso mode default = 0 usb controller s3c2 500b 10- 26 table 10-18. usbep1csr register description (continued) bit number bit name mcu usb description [12] in mode, auto set (iatset) r/w this bit is valid only when endpoint 1 is set to in. if set, whenever the mcu writes maxp data, iinrdy will be automatically be set without any intervention from mcu. if the mcu writes less than maxp data, then iinrdy bit has to be set by the mcu. default = 0 [14:13] reserved [15] csr2 settable (csr2set) w ? 0 = usbep1csr[12:8] isn't overwritten when mcu writes a 32bit value to usbep1csr register. 1 = usbep1csr[12:8] is overwritten. [16] out mode, out packet ready (oordy) r/c s this bit is valid only when endpoint 1 is set to out. the usb sets this bit once it has loaded a packet of data into the fifo. once the mcu reads the fifo for the entire packet, this bit should be cleared by mcu [17] out mode, fifo full (offull) r r/w this bit is valid only when endpoint 1 is set to out. indicates no more packets can be accepted if usbep1csr[17:16] is 00 = no packet in fifo 01 = 1 packet in fifo 11 = 2 packet of maxp =< 1/2 fifo size or 1 packet of maxp > fifo size [18] out mode, fifo over run (oover) r r/w this bit is valid only when endpoint 1 is set to out iso. this bit is set if the core is not able to load an out iso packet into the fifo [19] out mode, data error (oderr) r r/w this bit is valid only when endpoint 1 is set to out iso. this bit should be sampled with oordy. when set, it indicates the data packet due to be unloaded by the mcu has an error (either bit stuffing or crc). if two packets are loaded into the fifo, and the second packet has an error, then this bit gets set only after the first packet is unloaded. this is automatically cleared when oordy gets cleared. S3C2500B usb controller 10- 27 table 10-18. usbep1csr register description (continued) bit number bit name mcu usb description [20] out mode, fifo flush (offlush) r/w c this bit is valid only when endpoint 1 is set to out. the mcu writes a ?1? to flush the fifo. this bit can be set only when oordy is set. the packet due to be unloaded by the mcu will be flushed. [21] out mode, send stall (osdstall) r/w r this bit is valid only when endpoint 1 is set to out. the mcu writes a ?1? to this bit to issue a stall handshake to the usb. the mcu clears this bit to end the stall condition [22] out mode, sent stall (oststall) r/c s this bit is valid only when endpoint 1 is set to out. the usb sets this bit when an out token is ended with a stall handshake. the usb issues a stall handshake to the host if it sends more than maxp data for the out token. [23] out mode, clear data toggle (ocltog) r s this bit is valid only when endpoint 1 is set to out. when the mcu writes a ?1? to this bit, the data toggle sequence bit is reset to data0. [24] in mode, in packet ready (iinrdy) r/s c this bit is valid only when endpoint 1 is set to in. the mcu sets this bit, after writing a packet of data into the fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so the mcu can load the next packet, while this bit is set , the mcu will not be able to write to the fifo. if the send stall bit is set by the mcu, this bit can not be set. [25] in mode, fifo not empty (inemp) r s this bit is valid only when endpoint 1 is set to in. indicate there is at least one packet of data in fifo. if usbep1csr[25:24] is 10 = 1 packet in fifo 11 = 2 packets of maxp =< 1/2 fifo or 1 packet of maxp > fifo size usb controller s3c2 500b 10- 28 table 10-18. usbep1csr register description (continued) bit number bit name mcu usb description [26] in mode, under run (iunder) r/c s this bit is valid only when endpoint 1 is set to in iso. the usb sets this bit when in iso mode, an in token is received and the iinrdy bit is not set. the usb sends a zero length data packet for such conditions, and the next packet that is loaded into the fifo is flushed. [27] in mode, fifo flush (ifflush) r/w c this bit is valid only when endpoint 1 is set to in. the mcu sets this bit if it intends to flush the in fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in progress, the usb waits until the transmission is complete before the fifo is flushed. if two packets are loaded into the fifo, only the top-most packet (one that was intended to be sent to the host) is flushed, and the corresponding iinrdy bit for that packet is cleared. [28] in mode, send stall (isdstall) r/w r this bit is valid only when endpoint 1 is set to in. the mcu writes a 1 to this register to issue a stall handshake to the usb. the mcu clears this bit to end the stall condition. [29] in mode, sent stall (iststall) r/c s this bit is valid only when endpoint 1 is set to in. the usb sets this bit when a stall handshake is issued to an in token, due to the mcu setting send stall bit. when the usb issues a stall handshake, iinrdy is cleared. [30] in mode, clear data toggle (icltog) w r/c this bit is valid only when endpoint 1 is set to in. when the mcu writes a 1 to this bit, the data toggle bit is cleared. this is a write-only register. [31] reserved S3C2500B usb controller 10- 29 31 0 2 i i n r d y [2:0] maxp value (maxp) [2:0] value x 8 = max packet size [6:3] reserved [7] maxp value setting enable (maxpset) 0 = maxp value isn't changed 1 = maxp value is changed [8] (out) iso mode (oiso) 0 = bulk / interrupt mode 1 = iso mode [9] (out) auto clear (oatclr) 0 = no operation 1 = auto clearing ordy when fifo data unloaded [10] in/out mode setting (mode) 0 = indexed endpoint set to out 1 = indexed endpoint set to in [11] (in) iso mode (iiso) 0 = bulk / interrupt mode 1 = iso mode [12] (in) auto set (iatset) 0 = no operation 1 = auto setting iinrdy when maxp-sized packet loaded [14:13] reserved [15] csr2 setting enable (csr2set) 0 = usbep1csr[12:8] isn't changed 1 = usbep1csr[12:8] is changed [16] (out) out packet ready (oordy) 0 = not received data packet 1 = received packet from host [17] (out) fifo full (offull) 0 = normal operation 1 = fifo full state [18] (out) over run (oover) 0 = normal operation 1 = data received at fifo full state (iso) i n e m p i u n d e r i f f l u s h i s d s t a l l i s t s t a l l i c l t o g o o r d y o f f u l l o o v e r o d e r r o f f l u s h o s d s t a l l o s t s t a l l o c l t o g 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 c s r 2 s e t i a t s e t i i s o m o d e o a t c l r o i s o m a x p s e t m a x p 15 12 11 10 9 8 7 [19] (out) data error (oderr) 0 = normal operation 1 = data error (iso) [20] (out) fifo flush (offlush) 0 = no operation 1 = fifo flush [21] (out) send stall (osdstall) 0 = no operation 1 = stall handshake transmit state [22] (out) sent stall (oststall) 0 = no operation 1 = stall handshake transmitted [23] (out) clear data toggle (ocltog) 0 = no operation 1 = data toggle flag set to 0 [24] (in) in packet ready (iinrdy) 0 = not ready for in operation 1 = ready for in operation [25] (in) fifo not empty (inemp) 0 = no data packet in fifo 1 = there is at least one packet of data in fifo [26] (in) under run (iunder) 0 = no operation 1 = received in token but not ready (iso) [27] (in) fifo flush (ifflush) 0 = no operation 1 = fifo flush [28] (in) send stall (isdstall) 0 = no operation 1 = stall handshake transmit state [29] (in) sent stall (iststall) 0 = no operation 1 = stall handshake transmitted [30] (in) clear toggle (icltog) 0 = no operation 1 = data toggle flag set to 0 [31] reserved 14 13 6 3 figure 10-13. usbep1csr register usb controller s3c2 500b 10- 30 10.5.9 usb endpoint 2 common status register this register includes the control bits, status bits, in/out status information, and max packet size value for endpoint 2. table 10-19. usbep2csr register register address r/w description reset value usbep2csr 0xf00e0020 r/w usb endpoint 2 common status register 0x00000401 table 10-20. usbep2csr register description bit number bit name mcu usb description [2:0] maxp size value r/w r if maxp[2:0] is 000, then maxpsize is 0 byte if maxp[2:0] is 001, then maxpsize is 8 bytes if maxp[2:0] is 010, then maxpsize is 16 bytes if maxp[2:0] is 011, then maxpsize is 24 bytes if maxp[2:0] is 100, then maxpsize is 32 bytes [6:3] reserved [7] maxp size settable (maxpset) w ? 0 = usbep2csr[2:0] isn't overwritten when mcu writes a 32-bit value to usbep2csr register. 1 = usbep2csr[2:0] is overwritten. [8] out mode, iso mode (oiso) r/w this bit is valid only when endpoint 2 is set to out. 0 = endpoint 1 will be bulk mode. 1 = endpoint 1 will be iso mode default = 0 [9] out mode, auto clear (oatclr) r/w r this bit is valid only when endpoint 2 is set to out. if set, whenever the mcu unloads last data in endpoint 1 fifo, oordy will automatically be cleared without any intervention form mcu. default = 0 [10] in/out mode selection (mode) r/w 0 = transfer direction will be out 1 = transfer direction will be in default = 1 (in) [11] in mode, iso mode (iiso) r/w this bit is valid only when endpoint 2 is set to in. 0 = endpoint 2 will be bulk mode. 1 = endpoint 2 will be iso mode default = 0 S3C2500B usb controller 10- 31 table 10-20. usbep2csr register description (continued) bit number bit name mcu usb description [12] in mode, auto set (iatset) r/w this bit is only valid only when endpoint 2 is set to in. if set, whenever the mcu writes maxp data, iinrdy will be automatically be set without any intervention from mcu. if the mcu writes less than maxp data, then iinrdy bit has to be set by the mcu. default = 0 [14:13] reserved [15] csr2 settable (csr2set) w ? 0 = usbep2csr[12:8] isn't overwritten when mcu writes a 32bit value to usbep2csr register. 1 = usbep2csr[12:8] is overwritten. [16] out mode, out packet ready (oordy) r/c s this bit is valid only when endpoint 2 is set to out. the usb sets this bit once it has loaded a packet of data into the fifo. once the mcu reads the fifo for the entire packet, this bit should be cleared by mcu [17] out mode, fifo full (offull) r r/w this bit is valid only when endpoint 2 is set to out. indicates no more packets can be accepted if usbep2csr[17:16] is 00 = no packet in fifo 01 = 1 packet in fifo 11 = 2 packet of maxp =< 1/2 fifo size or 1 packet of maxp > fifo size [18] out mode, fifo over run (oover) r r/w this bit is valid only when endpoint 2 is set to out iso. this bit is set if the core is not able to load an out iso packet into the fifo [19] out mode, data error (oderr) r r/w this bit is valid only when endpoint 2 is set to out iso this bit should be sampled with oordy when set, it indicates the data packet due to be unloaded by the mcu has an error (either bit stuffing or crc). if two packets are loaded into the fifo, and the second packet has an error, then this bit gets set only after the first packet is unloaded. this is automatically cleared when oordy gets cleared. usb controller s3c2 500b 10- 32 table 10-20. usbep2csr register description (continued) bit number bit name mcu usb description [20] out mode, fifo flush (offlush) r/w c this bit is valid only when endpoint 2 is set to out. the mcu writes a ?1? to flush the fifo. this bit can be set only when oordy is set. the packet due to be unloaded by the mcu will be flushed. [21] out mode, send stall (osdstall) r/w r this bit is valid only when endpoint 2 is set to out. the mcu writes a ?1? to this bit to issue a stall handshake to the usb. the mcu clears this bit to end the stall condition [22] out mode, sent stall (oststall) r/c s this bit is valid only when endpoint 2 is set to out. the usb sets this bit when an out token is ended with a stall handshake. the usb issues a stall handshake to the host if it sends more than maxp data for the out token. [23] out mode, clear data toggle (ocltog) r s this bit is valid only when endpoint 2 is set to out. when the mcu writes a ?1? to this bit, the data toggle sequence bit is reset to data0. [24] in mode, in packet ready (iinrdy) r/s c this bit is valid only when endpoint 2 is set to in. the mcu sets this bit, after writing a packet of data into the fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so the mcu can load the next packet, while this bit is set, the mcu will not be able to write to the fifo. if the send stall bit is set by the mcu, this bit can not be set. [25] in mode, fifo not empty (inemp) r s this bit is valid only when endpoint 2 is set to in. indicate there is at least one packet of data in fifo. if usbep2csr[25:24] is 10 = 1 packet in fifo 11 = 2 packets of maxp =< 1/2 fifo or 1 packet of maxp > fifo size [26] in mode, under run (iunder) r/c s this bit is valid only when endpoint 2 is set to in iso. the usb sets this bit when in iso mode, an in token is received and the iinrdy bit is not set. the usb sends a zero length data packet for such conditions, and the next packet that is loaded into the fifo is flushed. S3C2500B usb controller 10- 33 table 10-20. usbep2csr register description (continued) bit number bit name mcu usb description [27] in mode, fifo flush (ifflush) r/w c this bit is valid only when endpoint 2 is set to in. the mcu sets this bit if it intends to flush the in fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in progress, the usb waits until the transmission is complete before the fifo is flushed. if two packets are loaded into the fifo, only the top-most packet (one that was intended to be sent to the host) is flushed, and the corresponding iinrdy bit for that packet is cleared. [28] in mode, send stall (isdstall) r/w r this bit is valid only when endpoint 2 is set to in. the mcu writes a 1 to this register to issue a stall handshake to the usb. the mcu clears this bit to end the stall condition. [29] in mode, sent stall (iststall) r/c s this bit is valid only when endpoint 2 is set to in. the usb sets this bit when a stall handshake is issued to an in token, due to the mcu setting send stall bit. when the usb issues a stall handshake, iinrdy is cleared. [30] in mode, clear data toggle (icltog) w r/c this bit is valid only when endpoint 2 is set to in. when the mcu writes a 1 to this bit, the data toggle bit is cleared. this is a write-only register. [31] reserved usb controller s3c2 500b 10- 34 31 0 2 i i n r d y [2:0] maxp value (maxp) [2:0]value x 8 = max packet size [6:3] reserved [7] maxp value setting enable (maxpset) 0 = maxp value isn't changed 1 = maxp value is changed [8] (out) iso mode (oiso) 0 = bulk / interrupt mode 1 = iso mode [9] (out) auto clear (oatclr) 0 = no operation 1 = auto clearing ordy when fifo data unloaded [10] in/out mode setting (mode) 0 = indexed endpoint set to out 1 = indexed endpoint set to in [11] (in) iso mode (iiso) 0 = bulk / interrupt mode 1 = iso mode [12] (in) auto set (iatset) 0 = no operation 1 = auto setting iinrdy when maxp-sized packet loaded [14:13] reserved [15] csr2 setting enable (csr2set) 0 = usbep2csr[12:8] isn't changed 1 = usbep2csr[12:8] is changed [16] (out) out packet ready (oordy) 0 = not received data packet 1 = received packet from host [17] (out) fifo full (offull) 0 = normal operation 1 = fifo full state [18] (out) over run (oover) 0 = normal operation 1 = data received at fifo full state (iso) i n e m p i u n d e r i f f l u s h i s d s t a l l i s t s t a l l i c l t o g o o r d y o f f u l l o o v e r o d e r r o f f l u s h o s d s t a l l o s t s t a l l o c l t o g 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 c s r 2 s e t i a t s e t i i s o m o d e o a t c l r o i s o m a x p s e t m a x p 15 12 11 10 9 8 7 [19] (out) data error (oderr) 0 = normal operation 1 = data error (iso) [20] (out) fifo flush (offlush) 0 = no operation 1 = fifo flush [21] (out) send stall (osdstall) 0 = no operation 1 = stall handshake transmit state [22] (out) sent stall (oststall) 0 = no operation 1 = stall handshake transmitted [23] (out) clear data toggle (ocltog) 0 = no operation 1 = data toggle flag set to 0 [24] (in) in packet ready (iinrdy) 0 = not ready for in operation 1 = ready for in operation [25] (in) fifo not empty (inemp) 0 = no data packet in fifo 1 = there is at least one packet of data in fifo [26] (in) under run (iunder) 0 = no operation 1 = received in token but not ready (iso) [27] (in) fifo flush (ifflush) 0 = no operation 1 = fifo flush [28] (in) send stall (isdstall) 0 = no operation 1 = stall handshake transmit state [29] (in) sent stall (iststall) 0 = no operation 1 = stall handshake transmitted [30] (in) clear toggle (icltog) 0 = no operation 1 = data toggle flag set to 0 [31] reserved 14 13 6 3 figure 10-14. usbep2csr register S3C2500B usb controller 10- 35 10.5.10 usb endpoint 3 common status register this register includes the control bits, status bits, in/out status information, and max packet size value for endpoint 3. table 10-21. usbep3csr register register address r/w description reset value usbep3csr 0xf00e0024 r/w usb endpoint 3 common status register 0x00000401 table 10-22. usbep3csr register description bit number bit name mcu usb description [3:0] maxp size value r/w r if maxp[3:0] is 0000, then maxpsize is 0 byte if maxp[3:0] is 0001, then maxpsize is 8 bytes if maxp[3:0] is 0010, then maxpsize is 16 bytes if maxp[3:0] is 0011, then maxpsize is 24 bytes if maxp[3:0] is 0100, then maxpsize is 32 bytes if maxp[3:0] is 0101, then maxpsize is 40 bytes if maxp[3:0] is 0110, then maxpsize is 48 bytes if maxp[3:0] is 0111, then maxpsize is 56 bytes if maxp[3:0] is 1000, then maxpsize is 64 bytes [6:4] reserved [7] maxp size settable (maxpset) w ? 0 = usbep3csr[3:0] isn?t overwritten when mcu writes a 32bit value to usbep3csr register. 1 = usbep3csr[3:0] is overwritten. [8] out mode, iso mode (oiso) r/w this bit is valid only when endpoint 3 is set to out. 0 = endpoint 1 will be bulk mode. 1 = endpoint 1 will be iso mode default = 0 [9] out mode, auto clear (oatclr) r/w r this bit is valid only when endpoint 3 is set to out. if set, whenever the mcu unloads last data in endpoint 1 fifo, oordy will automatically be cleared without any intervention form mcu. default = 0 [10] in/out mode selection (mode) r/w 0 = transfer direction will be out 1 = transfer direction will be in default = 1(in) [11] in mode, iso mode (iiso) r/w this bit is valid only when endpoint 3 is set to in. 0 = endpoint 3 will be bulk mode. 1 = endpoint 3 will be iso mode default = 0 usb controller s3c2 500b 10- 36 table 10-22. usbep3csr register description (continued) bit number bit name mcu usb description [12] in mode, auto set (iatset) r/w this bit is only valid only when endpoint 3 is set to in. if set, whenever the mcu writes maxp data, iinrdy will be automatically be set without any intervention from mcu. if the mcu writes less than maxp data, then iinrdy bit has to be set by the mcu. default = 0 [14:13] reserved [15] csr2 settable (csr2set) w ? 0 = usbep3csr[12:8] isn't overwritten when mcu writes a 32bit value to usbep3csr register. 1 = usbep3csr[12:8] is overwritten. [16] out mode, out packet ready (oordy) r/c s this bit is valid only when endpoint 3 is set to out. the usb sets this bit once it has loaded a packet of data into the fifo. once the mcu reads the fifo for the entire packet, this bit should be cleared by mcu [17] out mode, fifo full (offull) r r/w this bit is valid only when endpoint 3 is set to out. indicates no more packets can be accepted if usbep3csr[17:16] is 00 = no packet in fifo 01 = 1 packet in fifo 11 = 2 packet of maxp =< 1/2 fifo size or 1 packet of maxp > fifo size [18] out mode, fifo over run (oover) r r/w this bit is valid only when endpoint 3 is set to out iso. this bit is set if the core is not able to load an out iso packet into the fifo [19] out mode, data error (oderr) r r/w this bit is valid only when endpoint 3 is set to out iso this bit should be sampled with oordy when set, it indicates the data packet due to be unloaded by the mcu has an error (either bit stuffing or crc). if two packets are loaded into the fifo, and the second packet has an error, then this bit gets set only after the first packet is unloaded. this is automatically cleared when oordy gets cleared. S3C2500B usb controller 10- 37 table 10-22. usbep3csr register description (continued) bit number bit name mcu usb description [20] out mode, fifo flush (offlush) r/w c this bit is valid only when endpoint 3 is set to out. the mcu writes a ?1? to flush the fifo. this bit can be set only when oordy is set. the packet due to be unloaded by the mcu will be flushed. [21] out mode, send stall (osdstall) r/w r this bit is valid only when endpoint 3 is set to out. the mcu writes a ?1? to this bit to issue a stall handshake to the usb. the mcu clears this bit to end the stall condition [22] out mode, sent stall (oststall) r/c s this bit is valid only when endpoint 3 is set to out. the usb sets this bit when an out token is ended with a stall handshake. the usb issues a stall handshake to the host if it sends more than maxp data for the out token. [23] out mode, clear data toggle (ocltog) r s this bit is valid only when endpoint 3 is set to out. when the mcu writes a ?1? to this bit, the data toggle sequence bit is reset to data0. [24] in mode, in packet ready (iinrdy) r/s c this bit is valid only when endpoint 3 is set to in. the mcu sets this bit, after writing a packet of data into the fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so the mcu can load the next packet, while this bit is set , the mcu will not be able to write to the fifo. if the send stall bit is set by the mcu, this bit can not be set. [25] in mode, fifo not empty (inemp) r s this bit is valid only when endpoint 3 is set to in. indicate there is at least one packet of data in fifo. if usbep3csr[25:24] is 10 = 1 packet in fifo 11 = 2 packets of maxp =< 1/2 fifo or 1 packet of maxp > fifo size [26] in mode, under run (iunder) r/c s this bit is valid only when endpoint 3 is set to in iso. the usb sets this bit when in iso mode, an in token is received and the iinrdy bit is not set. the usb sends a zero length data packet for such conditions, and the next packet that is loaded into the fifo is flushed. usb controller s3c2 500b 10- 38 table 10-22. usbep3csr register description (continued) bit number bit name mcu usb description [27] in mode, fifo flush (ifflush) r/w c this bit is valid only when endpoint 3 is set to in. the mcu sets this bit if it intends to flush the in fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in progress, the usb waits until the transmission is complete before the fifo is flushed. if two packets are loaded into the fifo, only the top-most packet (one that was intended to be sent to the host) is flushed, and the corresponding iinrdy bit for that packet is cleared. [28] in mode, send stall (isdstall) r/w r this bit is valid only when endpoint 3 is set to in. the mcu writes a 1 to this register to issue a stall handshake to the usb. the mcu clears this bit to end the stall condition. [29] in mode, sent stall (iststall) r/c s this bit is valid only when endpoint 3 is set to in. the usb sets this bit when a stall handshake is issued to an in token, due to the mcu setting send stall bit. when the usb issues a stall handshake, iinrdy is cleared. [30] in mode, clear data toggle (icltog) w r/c this bit is valid only when endpoint 3 is set to in. when the mcu writes a 1 to this bit, the data toggle bit is cleared. this is a write-only register. [31] reserved S3C2500B usb controller 10- 39 31 0 3 i i n r d y [3:0] maxp value (maxp) [3:0]value x 8 = max packet size [6:4] reserved [7] maxp value setting enable (maxpset) 0 = maxp value isn't changed 1 = maxp value is changed [8] (out) iso mode (oiso) 0 = bulk / interrupt mode 1 = iso mode [9] (out) auto clear (oatclr) 0 = no operation 1 = auto clearing ordy when fifo data unloaded [10] in/out mode setting (mode) 0 = indexed endpoint set to out 1 = indexed endpoint set to in [11] (in) iso mode (iiso) 0 = bulk / interrupt mode 1 = iso mode [12] (in) auto set (iatset) 0 = no operation 1 = auto setting iinrdy when maxp-sized packet loaded [14:13] reserved [15] csr2 setting enable (csr2set) 0 = usbep3csr[12:8] isn't changed 1 = usbep3csr[12:8] is changed [16] (out) out packet ready (oordy) 0 = not received data packet 1 = received packet from host [17] (out) fifo full (offull) 0 = normal operation 1 = fifo full state [18] (out) over run (oover) 0 = normal operation 1 = data received at fifo full state (iso) i n e m p i u n d e r i f f l u s h i s d s t a l l i s t s t a l l i c l t o g o o r d y o f f u l l o o v e r o d e r r o f f l u s h o s d s t a l l o s t s t a l l o c l t o g 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 c s r 2 s e t i a t s e t i i s o m o d e o a t c l r o i s o m a x p s e t m a x p 15 12 11 10 9 8 7 [19] (out) data error (oderr) 0 = normal operation 1 = data error (iso) [20] (out) fifo flush (offlush) 0 = no operation 1 = fifo flush [21] (out) send stall (osdstall) 0 = no operation 1 = stall handshake transmit state [22] (out) sent stall (oststall) 0 = no operation 1 = stall handshake transmitted [23] (out) clear data toggle (ocltog) 0 = no operation 1 = data toggle flag set to 0 [24] (in) in packet ready (iinrdy) 0 = not ready for in operation 1 = ready for in operation [25] (in) fifo not empty (inemp) 0 = no data packet in fifo 1 = there is at least one packet of data in fifo [26] (in) under run (iunder) 0 = no operation 1 = received in token but not ready (iso) [27] (in) fifo flush (ifflush) 0 = no operation 1 = fifo flush [28] (in) send stall (isdstall) 0 = no operation 1 = stall handshake transmit state [29] (in) sent stall (iststall) 0 = no operation 1 = stall handshake transmitted [30] (in) clear toggle (icltog) 0 = no operation 1 = data toggle flag set to 0 [31] reserved 14 13 6 4 figure 10-15. usbep3csr register usb controller s3c2 500b 10- 40 10.5.11 usb endpoint 4 common status register this register includes the control bits, status bits, in/out status information, and max packet size value for endpoint 4. table 10-23. usbep4csr register register address r/w description reset value usbep4csr 0xf00e0028 r/w usb endpoint 4 common status register 0x00000401 table 10-24. usbep4csr register description bit number bit name mcu usb description [3:0] maxp size value r/w r if maxp[3:0] is 0000, then maxpsize is 0 byte if maxp[3:0] is 0001, then maxpsize is 8 bytes if maxp[3:0] is 0010, then maxpsize is 16 bytes if maxp[3:0] is 0011, then maxpsize is 24 bytes if maxp[3:0] is 0100, then maxpsize is 32 bytes if maxp[3:0] is 0101, then maxpsize is 40 bytes if maxp[3:0] is 0110, then maxpsize is 48 bytes if maxp[3:0] is 0111, then maxpsize is 56 bytes if maxp[3:0] is 1000, then maxpsize is 64 bytes [6:4] reserved [7] maxp size settable (maxpset) w ? 0 = usbep4csr[3:0] isn't overwritten when mcu writes a 32bit value to usbep4csr register. 1 = usbep4csr[3:0] is overwritten. [8] out mode, iso mode (oiso) r/w this bit is valid only when endpoint 4 is set to out. 0 = endpoint 1 will be bulk mode. 1 = endpoint 1 will be iso mode default = 0 [9] out mode, auto clear (oatclr) r/w r this bit is valid only when endpoint 4 is set to out. if set, whenever the mcu unloads last data in endpoint 1 fifo, oordy will automatically be cleared without any intervention form mcu. default = 0 [10] in/out mode selection (mode) r/w 0 = transfer direction will be out 1 = transfer direction will be in default = 1(in) [11] in mode, iso mode (iiso) r/w this bit is valid only when endpoint 4 is set to in. 0 = endpoint 4 will be bulk mode. 1 = endpoint 4 will be iso mode default = 0 S3C2500B usb controller 10- 41 table 10-24. usbep4csr register description (continued) bit number bit name mcu usb description [12] in mode, auto set (iatset) r/w this bit is only valid only when endpoint 4 is set to in. if set, whenever the mcu writes maxp data, iinrdy will be automatically be set without any intervention from mcu. if the mcu writes less than maxp data, then iinrdy bit has to be set by the mcu. default = 0 [14:13] reserved [15] csr2 settable (csr2set) w ? 0 = usbep4csr[12:8] isn?t overwritten when mcu writes a 32bit value to usbep4csr register. 1 = usbep4csr[12:8] is overwritten. [16] out mode, out packet ready (oordy) r/c s this bit is valid only when endpoint 4 is set to out. the usb sets this bit once it has loaded a packet of data into the fifo. once the mcu reads the fifo for the entire packet, this bit should be cleared by mcu [17] out mode, fifo full (offull) r r/w this bit is valid only when endpoint 4 is set to out. indicates no more packets can be accepted if usbep4csr[17:16] is 00 = no packet in fifo 01 = 1 packet in fifo 11 = 2 packet of maxp =< 1/2 fifo size or 1 packet of maxp > fifo size [18] out mode, fifo over run (oover) r r/w this bit is valid only when endpoint 4 is set to out iso. this bit is set if the core is not able to load an out iso packet into the fifo [19] out mode, data error (oderr) r r/w this bit is valid only when endpoint 4 is set to out iso this bit should be sampled with oordy when set, it indicates the data packet due to be unloaded by the mcu has an error (either bit stuffing or crc). if two packets are loaded into the fifo, and the second packet has an error, then this bit gets set only after the first packet is unloaded. this is automatically cleared when oordy gets cleared. [20] out mode, fifo flush (offlush) r/w c this bit is valid only when endpoint 4 is set to out. the mcu writes a ?1? to flush the fifo. this bit can be set only when oordy is set. the packet due to be unloaded by the mcu will be flushed. usb controller s3c2 500b 10- 42 table 10-24. usbep4csr register description (continued) bit number bit name mcu usb description [21] out mode, send stall (osdstall) r/w r this bit is valid only when endpoint 4 is set to out. the mcu writes a ?1? to this bit to issue a stall handshake to the usb. the mcu clears this bit to end the stall condition [22] out mode, sent stall (oststall) r/c s this bit is valid only when endpoint 4 is set to out. the usb sets this bit when an out token is ended with a stall handshake. the usb issues a stall handshake to the host if it sends more than maxp data for the out token. [23] out mode, clear data toggle (ocltog) r s this bit is valid only when endpoint 4 is set to out. when the mcu writes a ?1? to this bit, the data toggle sequence bit is reset to data0. [24] in mode, in packet ready (iinrdy) r/s c this bit is valid only when endpoint 4 is set to in. the mcu sets this bit, after writing a packet of data into the fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so the mcu can load the next packet, while this bit is set , the mcu will not be able to write to the fifo. if the send stall bit is set by the mcu, this bit can not be set. [25] in mode, fifo not empty (inemp) r s this bit is valid only when endpoint 4 is set to in. indicate there is at least one packet of data in fifo. if usbep4csr[25:24] is 10 = 1 packet in fifo 11 = 2 packets of maxp =< 1/2 fifo or 1 packet of maxp > fifo size [26] in mode, under run (iunder ) r/c s this bit is valid only when endpoint 4 is set to in iso. the usb sets this bit when in iso mode, an in token is received and the iinrdy bit is not set. the usb sends a zero length data packet for such conditions, and the next packet that is loaded into the fifo is flushed. S3C2500B usb controller 10- 43 table 10-24. usbep4csr register description (continued) bit number bit name mcu usb description [27] in mode, fifo flush (ifflush) r/w c this bit is valid only when endpoint 4 is set to in. the mcu sets this bit if it intends to flush the in fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in progress, the usb waits until the transmission is complete before the fifo is flushed. if two packets are loaded into the fifo, only the top-most packet (one that was intended to be sent to the host) is flushed, and the corresponding iinrdy bit for that packet is cleared. [28] in mode, send stall (isdstall) r/w r this bit is valid only when endpoint 4 is set to in. the mcu writes a 1 to this register to issue a stall handshake to the usb. the mcu clears this bit to end the stall condition. [29] in mode, sent stall (iststall) r/c s this bit is valid only when endpoint 4 is set to in. the usb sets this bit when a stall handshake is issued to an in token, due to the mcu setting send stall bit. when the usb issues a stall handshake, iinrdy is cleared. [30] in mode, clear data toggle (icltog) w r/c this bit is valid only when endpoint 4 is set to in. when the mcu writes a 1 to this bit, the data toggle bit is cleared. this is a write-only register. [31] reserved usb controller s3c2 500b 10- 44 31 0 3 i i n r d y [3:0] maxp value (maxp) [3:0]value x 8 = max packet size [6:4] reserved [7] maxp value setting enable (maxpset) 0 = maxp value isn't changed 1 = maxp value is changed [8] (out) iso mode (oiso) 0 = bulk / interrupt mode 1 = iso mode [9] (out) auto clear (oatclr) 0 = no operation 1 = auto clearing ordy when fifo data unloaded [10] in/out mode setting (mode) 0 = indexed endpoint set to out 1 = indexed endpoint set to in [11] (in) iso mode (iiso) 0 = bulk / interrupt mode 1 = iso mode [12] (in) auto set (iatset) 0 = no operation 1 = auto setting iinrdy when maxp-sized packet loaded [14:13] reserved [15] csr2 setting enable (csr2set) 0 = usbep4csr[12:8] isn't changed 1 = usbep4csr[12:8] is changed [16] (out) out packet ready (oordy) 0 = not received data packet 1 = received packet from host [17] (out) fifo full (offull) 0 = normal operation 1 = fifo full state [18] (out) over run (oover) 0 = normal operation 1 = data received at fifo full state (iso) i n e m p i u n d e r i f f l u s h i s d s t a l l i s t s t a l l i c l t o g o o r d y o f f u l l o o v e r o d e r r o f f l u s h o s d s t a l l o s t s t a l l o c l t o g 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 c s r 2 s e t i a t s e t i i s o m o d e o a t c l r o i s o m a x p s e t m a x p 15 12 11 10 9 8 7 [19] (out) data error (oderr) 0 = normal operation 1 = data error (iso) [20] (out) fifo flush (offlush) 0 = no operation 1 = fifo flush [21] (out) send stall (osdstall) 0 = no operation 1 = stall handshake transmit state [22] (out) sent stall (oststall) 0 = no operation 1 = stall handshake transmitted [23] (out) clear data toggle (ocltog) 0 = no operation 1 = data toggle flag set to 0 [24] (in) in packet ready (iinrdy) 0 = not ready for in operation 1 = ready for in operation [25] (in) fifo not empty (inemp) 0 = no data packet in fifo 1 = there is at least one packet of data in fifo [26] (in) under run (iunder) 0 = no operation 1 = received in token but not ready (iso) [27] (in) fifo flush (ifflush) 0 = no operation 1 = fifo flush [28] (in) send stall (isdstall) 0 = no operation 1 = stall handshake transmit state [29] (in) sent stall (iststall) 0 = no operation 1 = stall handshake transmitted [30] (in) clear toggle (icltog) 0 = no operation 1 = data toggle flag set to 0 [31] reserved 14 13 6 4 figure 10-16. usbep4csr register S3C2500B usb controller 10- 45 10.5.12 usb write count for endpoint 0 register when oordy is set for out endpoints, usbwcep0[22:16] maintains the byte-count number of data in fifo due to be unloaded by the mcu. in case of in mode, mcu first writes the byte-count number of data to be loaded into fifo, then write data into fifo. table 10-25. usbwcep0 register register address r/w description reset value usbwcep0 0xf00e0030 r/w usb write count for endpoint 0 register 0x00000000 table 10-26. usbwcep0 register description bit number bit name mcu usb description [6:0] cpu write count (cpuwrtcnt) r/w r the byte-count number of data to be loaded into fifo [15:7] reserved [22:16] write count (wrtcnt) r w the byte-count number of data in fifo due to be unloaded by the mcu [31:23] reserved usb controller s3c2 500b 10- 46 31 22 0 6 [6:0] ep0 cpu write count (cpuwrtcnt) [15:7] reserved [22:16] ep0 write count (wrtcnt) [31:23] reserved 16 15 23 7 wrtcnt cpuwrtcnt figure 10-17. usbwcep0 register S3C2500B usb controller 10- 47 10.5.13 usb write count for endpoint 1 register when oordy is set for out endpoints, usbwcep1[21:16] maintains the byte-count number of data in fifo due to be unloaded by the mcu. in case of in mode, mcu first writes the byte-count number of data to be loaded into fifo, then write data into fifo. table 10-27. usbwcep1 register register address r/w description reset value usbwcep1 0xf00e0034 r/w usb write count for endpoint 1 register 0x00000000 table 10-28. usbwcep1 register description bit number bit name mcu usb description [5:0] cpu write count (cpuwrtcnt) r/w r the byte-count number of data to be loaded into fifo [15:6] reserved [21:16] write count (wrtcnt) r w the byte-count number of data in fifo due to be unloaded by the mcu [31:22] reserved usb controller s3c2 500b 10- 48 31 21 0 5 [5:0] ep1 cpu write count (cpuwrtcnt) [15:6] reserved [21:16] ep1 write count (wrtcnt) [31:22] reserved 16 wrtcnt cpuwrtcnt 22 15 6 figure 10-18. usbwcep1 register S3C2500B usb controller 10- 49 10.5.14 usb write count for endpoint 2 register when oordy is set for out endpoints, usbwcep2[21:16] maintains the byte-count number of data in fifo due to be unloaded by the mcu. in case of in mode, mcu first writes the byte-count number of data to be loaded into fifo, then write data into fifo. table 10-29. usbwcep2 register register address r/w description reset value usbwcep2 0xf00e0038 r/w usb write count for endpoint 2 register 0x00000000 table 10-30. usbwcep2 register description bit number bit name mcu usb description [5:0] cpu write count (cpuwrtcnt) r/w r the byte-count number of data to be loaded into fifo [15:7] reserved [21:16] write count (wrtcnt) r w the byte-count number of data in fifo due to be unloaded by the mcu [31:22] reserved usb controller s3c2 500b 10- 50 31 0 5 [5:0] ep2 cpu write count (cpuwrtcnt) [15:6] reserved [21:16] ep2 write count (wrtcnt) [31:22] reserved 16 21 wrtcnt cpuwrtcnt 22 15 6 figure 10-19. usbwcep2 register S3C2500B usb controller 10- 51 10.5.15 usb write count for endpoint 3 register when oordy is set for out endpoints, usbwcep3[22:16] maintains the byte-count number of data in fifo due to be unloaded by the mcu. in case of in mode, mcu first writes the byte-count number of data to be loaded into fifo, then write data into fifo. table 10-31. usbwcep3 register register address r/w description reset value usbwcep3 0xf00e003c r/w usb write count for endpoint 3 register 0x00000000 table 10-32. usbwcep3 register description bit number bit name mcu usb description [6:0] cpu write count (cpuwrtcnt) r/w r the byte-count number of data to be loaded into fifo [15:7] reserved [22:16] write count (wrtcnt) r w the byte-count number of data in fifo due to be unloaded by the mcu usb controller s3c2 500b 10- 52 31 0 6 [6:0] ep3 cpu write count (cpuwrtcnt) [15:7] reserved [22:16] ep3 write count (wrtcnt) [31:23] reserved 16 22 wrtcnt cpuwrtcnt 23 15 7 figure 10-20. usbwcep3 register S3C2500B usb controller 10- 53 10.5.16 usb write count for endpoint 4 register when oordy is set for out endpoints, usbwcep4[22:16] maintains the byte-count number of data in fifo due to be unloaded by the mcu. in case of in mode, mcu first writes the byte-count number of data to be loaded into fifo, then write data into fifo. table 10-33. usbwcep4 register register address r/w description reset value usbwcep4 0xf00e0040 r/w usb write count for endpoint 4 register 0x00000000 table 10-34. usbwcep4 register description bit number bit name mcu usb description [6:0] cpu write count (cpuwrtcnt) r/w r the byte-count number of data to be loaded into fifo [15:7] reserved [22:16] write count (wrtcnt) r w the byte-count number of data in fifo due to be unloaded by the mcu usb controller s3c2 500b 10- 54 31 22 0 6 [6:0] ep4 cpu write count (cpuwrtcnt) [15:7] reserved [22:16] ep4 write count (wrtcnt) [31:23] reserved 16 wrtcnt cpuwrtcnt 23 15 7 figure 10-21. usbwcep4 register S3C2500B usb controller 10- 55 10.5.17 usb endpoint 0/1/2/3/4 fifo register each endpoint has his own fifo. to access to each fifo data, user must use these registers. table 10-35. usbep0/ 1/ 2/ 3/ 4 descriptions register address r/w description reset value usbep0 usbep1 usbep2 usbep3 usbep4 0xf00e0080 0xf00e0084 0xf00e0088 0xf00e008c 0xf00e0090 r[w] r[w] r[w] r[w] r[w] usb ep0 fifo usb ep1 fifo usb ep2 fifo usb ep3 fifo usb ep4 fifo 0xxxxxxxxx 0xxxxxxxxx 0xxxxxxxxx 0xxxxxxxxx 0xxxxxxxxx usb controller s3c2 500b 10- 56 0 31 ep0 fifo [31:0] endpoint 0 data fifo 0 31 ep1 fifo [31:0] endpoint 1 data fifo 0 31 ep2 fifo [31:0] endpoint 2 data fifo 0 31 ep3 fifo [31:0] endpoint 3 data fifo 0 31 ep4 fifo [31:0] endpoint 4 data fifo figure 10-22. usbep0/1/2/3/4 fifo registers S3C2500B des/3des 11 - 1 11 des/3des 11.1 overview the data encryption standard (des) consists of the data encryption algorithm (des) and triple data encryption algorithm (tdea, as described in ansi x9.52). the des/3des accelerator of the S3C2500B is designed in such a way that they may be used in a computer system or network to provide cryptographic protection to binary coded data. fips pub 81, des modes of operation, describes four different modes for using des described in this standard. those are ecb-electronic codebook, cbc-cipher block chaining, cfb-cipher feedback, and ofb-output feedback. but in the S3C2500B, two modes are supported ? ecb and cbc. the x9.52 standard, "triple data encryption algorithm modes of operation" describes seven different modes for using tdea. those are tecb ? tdea electronic codebook mode of operation, tcbc ? tdea cipher block chaining mode of operation, tcbc-i ? tdea cipher block chaining mode of operation-interleaved, tcfb ? tdea cipher feedback mode of operation, tcfb-p ? tdea cipher feedback mode of operation-pipelined, tofb ? tdea output feedback mode of operation, and tofb-i ? tdea output feedback mode of operation-interleaved. but in the S3C2500B, two modes are supported-tecb and tcbc. the des/3des of S3C2500B supports byte-swapping function for desinfifo, desoutfifo, iv, and keys. 11.2 features des or triple des mode ecb or cbc mode encryption or decription support general dma support des/3des S3C2500B 11- 2 3/2 cycle 2 cycle 1 cycle 1/2 cycle 20/60(des/3des) cycle desin fifo desoutfi fo control status interrupt enable iv input buffer output buffer desctrl key3 add decode pw data key write sig. iv/indata register pwdata paddr penable pselx pwrite pwdata prdata register dreg64 pbox sbox exp status des_mode wr_indata in_mode sig. outdata register left side data left side data left side data in_mode sig. fsm (state machine) key2 key1 keygen fsm (state machine) key48 left side data right side data s y s t e m b u s pr data des/3des figure 11-1. des/3des block diagram S3C2500B des/3des 11 - 3 11.3 des/3des special registers table 11-1. des/3des special registers overview registers address r/w description reset value descon 0xf0090000 r/w des/3des control register 0 00000000 dessta 0xf0090004 r des/3des status register 0x00000231 desint 0xf0090008 r/w des/3des interrupt enable register 0x00000000 desrun 0xf009000c w des/3des run enable register 0x00000000 deskey1l 0xf0090010 r/w key 1 left half. *key 1 is the security key for des, the 1 st des of 3des in the encryption mode or 3 rd des of 3des in the decryption mode. 0x00000000 deskey1r 0xf0090014 r/w key 1 right half 0x00000000 deskey2l 0xf0090018 r/w key 2 left half. *key 2 is the security key for the 2 nd des of 3des. 0x00000000 deskey2r 0xf009001c r/w key 2 right half 0x00000000 deskey3l 0xf0090020 r/w key 3 left half. *key 3 is the security key for the 3 rd des of 3des in the encryption mode or 1 st des of 3des in the decryption mode. 0x00000000 deskey3r 0xf0090024 r/w key 3 right half 0x00000000 desivl 0xf0090028 r/w iv left half. *iv is used for cbc mode only. the iv for the next block is updated automatically. 0x00000000 desivr 0xf009002c r/w iv right half 0x00000000 desinfifo 0xf0090030 w des/3des input fifo this fifo depth is 8 words. 0xxxxxxxxx desoutfifo 0xf0090034 r des/3des output fifo this fifo depth is 8 words. 0xxxxxxxxx des/3des S3C2500B 11- 4 11.3.1 des/3des control register table 11-2. des/3des control register description bit number bit name description [0] run enable 0 = des/3des disable 1 = des/3des enable this bit is the same register as the run enable bit of the run enable register. that is, this bit has two writing address, 0x00 and 0x0c. [1] indata_dma 0 = cpu transfers the data to be encrypted from the external memory to the desinfifo of des/3des 1 = gdma transfers the data to be encrypted from the external memory to the desinfifo of des/3des [2] outdata_dma 0 = cpu transfers the encrypted data from the desoutfifo of des/3des to the external memory 1 = gdma transfers the encrypted data from the desoutfifo of des/3des to the external memory [3] right_left data 0 = cpu write(read) from left half to right half data in desinfifo(out desoutfifo) 1 = cpu write(read) from right half to left half data in desinfifo(out desoutfifo) [4] encryption or decryption 0 = des/3des data will be encrypted. 1 = des/3des data will be decrypted. [5] des or 3des 0 = des algorithm is selected. 1 = triple-des algorithm is selected. [6] encryption mode (ecb or cbc) 0 = des/3des will be running ecb(electronic code book) mode. 1 = des/3des will be running cbc(cipher block chaining) mode. [7] 2word_req 0 = des/3des engine generates available desinfifo bit in the status register to 1 when desinfifo is vacant more than 4 words, and valid desoutfifo bit in the status register to 1 when desoutfifo has more than 4 words valid data. 1 = des/3des engine generates available desinfifo bit in the status register to 1 when desinfifo is vacant more than 2 words, and valid desoutfifo bit in the status register to 1 when desoutfifo has more than 2 words valid data. [8] fifo test 0 = normal operation 1 = desinfifo and desoutfifo test. if this bit sets to 1, user can scan desinfifo and desoutfifo. [9] fifo reset 0 = normal operation 1 = the data in the desinfifo and desoutfifo have been invalid data. [10] swapen_data 0 = no byte swapping for desinfifo and desoutfifo. 1 = cpu or gdma write byte-swapped data to desinfifo, and read byte-swapped data from the desoutfifo. [11] swapen_iv 0 = no byte swapping for desivl/r. 1 = cpu writes byte-swapped iv value to the desivl/r, and reads byte-swapped data from the desivl/r. [12] swapen_keys 0 = no byte swapping for deskey#l/r. 1 = cpu writes byte-swapped data to the deskey#l/r, and reads byte-swapped data from deskey#l/r. S3C2500B des/3des 11 - 5 11.3.2 des/3des status register table 11-3. des/3des status register description bit number bit name description [0] idle this bit indicates whether des/3des is running or not [3:1] reserved these bits have 0 value. [4] available desinfifo desinfifo is vacant 4(or 2, depends on descon[7]) words or more, this bit is set to 1. [5] empty desinfifo desinfifo is vacant all. [6] full desinfifo desinfifo has 8 words valid data. cpu can't write in any more. [7] reserved this bit has 0 value. [8] valid desoutfifo desoutfifo has 4(or 2, depends on descon[7]) valid words or more, this bit is set to 1. [9] empty desoutfifo desoutfifo is vacant all. [10] full desoutfifo desoutfifo has 8 words valid data. cpu have to read data immediately. 11.3.3 des/3des interrupt enable register table 11-4. des/3des interrupt enable register description bit number bit name description [0] int idle interrupt enable register for des/3des engine operation 0 = disable 1 = interrupt signal is generated when the status register [0] (idle) bit goes to high which means the end of the current des/3des operation. [3:1] reserved [4] int available desinfifo interrupt enable register for input fifo, desinfifo 0 = disable 1 = interrupt signal is generated when the status register [4] (available desinfifo) bit goes to high. [7:5] reserved [8] int valid desoutfifo interrupt enable register for output fifo, desoutfifo 0 = disable 1 = interrupt signal is generated when the status register [8] (valid desoutfifo) bit goes to high. des/3des S3C2500B 11- 6 11.3.4 des/3des run enable register table 11-5. des/3des run enable register description bit number bit name description [0] run enable if you set this bit to 1, des/3des engine begin to run. this bit is the same register as the run enable bit of the des/3des control register. you can read this bit by addressing 0x00, too. 11.3.5 des/3des key1 left/right side register table 11-6. des/3des key1 left side register description bit number bit name description [1:32] key 1 left half the left half of the key1 should be stored to this register. the 8 th bit of each byte is parity bit, and it isn't used for encryption/decryption. if users need to byte-swapped key value, they can control it by using descon[12]. if descon[12] is set, byte-swapped key is written to deskey1l. otherwise, original key is written to deskey1l. table 11-7. des/3des key 1 right side register description bit number bit name description [33:64] key 1 right half the right half of the key1 should be stored to this register. the 8 th bit of each byte is parity bit, and it isn't used for encryption/decryption. if users need to byte-swapped key value, they can control it by using descon[12]. if descon[12] is set, byte-swapped key is written to deskey1r. otherwise, original key is written to deskey1r. 11.3.6 des/3des key 2 left/right side register table 11-8. des/3des key 2 left side register description bit number bit name description [1:32] key 2 left half the left half of the key2 should be stored to this register. the 8 th bit of each byte is parity bit, and it isn't used for encryption/decryption. if users need to byte-swapped key value, they can control it by using descon[12]. if descon[12] is set, byte-swapped key is written to deskey2l. otherwise, original key is written to deskey2l. table 11-9. des/3des key 2 right side register description bit number bit name description [33:64] key 2 right half the right half of the key2 should be stored to this register. the 8 th bit of each byte is parity bit, and it isn't used for encryption/decryption. S3C2500B des/3des 11 - 7 if users need to byte-swapped key value, they can control it by using descon[12]. if descon[12] is set, byte-swapped key is written to deskey2r. otherwise, original key is written to deskey2r. des/3des S3C2500B 11- 8 11.3.7 des/3des key 3 left side register table 11-10. des/3des key 3 left side register description bit number bit name description [1:32] key 3 left half the left half of the key3 should be stored to this register. the 8 th bit of each byte is parity bit, and it isn't used for encryption/decryption. if users need to byte-swapped key value, they can control it by using descon[12]. if descon[12] is set, byte-swapped key is written to deskey3l. otherwise, original key is written to deskey3l. table 11-11. des/3des key 3 right side register description bit number bit name description [33:64] key 3 right half the right half of the key3 should be stored to this register. the 8 th bit of each byte is parity bit, and it isn't used for encryption/decryption. if users need to byte-swapped key value, they can control it by using descon[12]. if descon[12] is set, byte-swapped key is written to deskey3r. otherwise, original key is written to deskey3r. 11.3.8 des/3des iv left/right side register table 11-12. des/3des iv left side register description bit number bit name description [1:32] iv left half iv is only used for the cbc mode. the left half of the 1 st iv should be stored in this register. the iv for the next block is updated in this register automatically. if users need to byte-swapped iv value, they can control it by using descon[11]. if descon[11] is set, byte-swapped iv is written to desivl, otherwise, original key is written to desivl. table 11-13. des/3des iv right side register description bit number bit name description [33:64] iv right half iv is only used for the cbc mode. the right half of the 1 st iv should be stored in this register. the iv for the next block is updated in this register automatically. if users need to byte-swapped iv value, they can control it by using descon[11]. if descon[11] is set, byte-swapped iv is written to desivr, otherwise, original key is written to desivr. S3C2500B des/3des 11 - 9 11.3.9 des/3des input/output data fifo register table 11-14. des/3des input data fifo description bit number bit name description [31:0] desinfifo this fifo can be filled by cpu or dma (depends on control register value). this fifo consists of 8 words. if data are transferred by dma the 4-word burst transaction (descon[7] is zero, and dcon#[5] is one) is recommended. otherwise, if data are transferred by cpu, the 2-word transaction (descon[7] is one) is recommended. if descon[3] is zero, the 1 st written data is the left half of data to be encrypted/decrypted, bit[1:32]. the second one is the right half of data to be encrypted/decrypted, bit[33:64]. otherwise, if descon[3] is one, the 1 st written data is the right half of data to be encrypted/decrypted, bit[33:64]. the second one is the left half of data to be encrypted/decrypted, bit[1:32]. the byte order in the desinfifo is lsb first. that is, the lsb byte is stored to desinfifo[31:24]. if you need to swap the byte order, you can control it by using descon[10]. if descon[10] is set, the written data to the desinfifo is automatically byte-swapped. otherwise, the written data have the original byte order. table 11-15. des/3des output data fifo description bit number bit name description [31:0] desoutfifo this fifo can be read by cpu or dma (depends on control register value). this fifo consists of 8 words. if data are transferred by dma the 4-word burst transaction (descon[7] is zero, and dcon#[5] is one) is recommended. otherwise, if data are transferred by cpu, the 2-word transaction (descon[7] is one) is recommended. if descon[3] is zero, the 1 st read data is the left half of data encrypted/decrypted, bit[1:32]. the second one is the right half of data encrypted/decrypted, bit[33:64]. otherwise, if descon[3] is one, the 1 st read data is the right half of data encrypted/decrypted, bit[33:64]. the second one is the left half of data encrypted/decrypted, bit[1:32]. the byte order in the desoutfifo is lsb first. that is the lsb byte is read from desoutfifo[31:24]. if you need to swap the byte order, you can control it by using descon[10]. if descon[10] is set, the read data from the desoutfifo is automatically byte-swapped. otherwise, the read data have the original byte order. des/3des S3C2500B 11- 10 11.4 des/3des operation the 64-bit data to be encoded should be written to desinfifo of des/3des block by cpu or dma. when the data conversion is completed, the valid desoutfifo bit in dessta is set to 1 and the cpu/dma can read the encrypted data from the desoutfifo. the desinfifo and desoutfifo consists of eight 32 bit registers that are used for data storage. the desinfifo has two data request options for data transmission, which is controlled by descon[7]. when the descon[7] is set to "0", the available desinfifo status means that desinfifo is empty for 4 word. it is recommended, when dma mode is selected. when the descon[7] is set to "1", the available desinfifo status means that desinfifo is empty for 2 word. it is recommended, when cpu mode is selected. similarly, the desoutfifo has two data request options for data receiving, which is controlled by descon[7]. when the descon[7] is set to "0", the valid desoutfifo status means that desoutfifo has at least 4 word valid data. it is recommended, when dma mode is selected. when the descon[7] is set to "1", the valid desoutfifo status means that desoutfifo has at least 2 word valid data. it is recommended, when cpu mode is selected. when the available desinfifo or valid desoutfifo request signal (interrupt or dma signal) is generated, the cpu or dma can write or read data to/from the desin/outfifo. software can use des or 3des according to applications, which is controlled by descon[5]. when the descon[5] is set to "0" (the des algorithm is used), the key1 value is used and the key2 and the key3 are ignored. when the descon[5] is set to "1" (the 3des algorithm is used), the key1, key2 and key3 value are used. the 3des algorithm can select the number of keys (2keys or 3keys). it must be noticed that when the 3des with 2keys(not 3keys) is selected, the key value of the key1 register and the key3 register must be the same. S3C2500B des/3des 11 - 11 11.5 performance calculation guide supposed condition: ? desinfifo has already data to be encrypting. ? desoutfifo can be written data to be encrypted. cycle unit (reference figure 11-1 des/3des block diagram) unit 1: from desinfifo to input buffer (1+1/2 cycle) unit 2: from input buffer to des engine (1 cycle) unit 3: des operation (20 cycles for des, 60 cycles for 3des) unit 4: from des engine to output buffer (1/2 cycle) unit 5: from output buffer to desoutfifo (2 cycle) total: 25 cycles for des, 65 cycles for 3des explain: des engine consumes fixed cycle per block (25 cycles for des, and 65 cycles for 3des). if the des operating frequency is 133mhz and the des has one block to be encrypted, the des performance is 341 mbps for des or 131 mbps for 3des. for more real system condition, the user have to consider how many cycles is needed for external memory access. the memory access cycle should be included the performance calculation as follows des performance calculation formula p = (#num of block 64 bit) / {(time of one period) [(#num of block c des ) + (c mem2des + c des2mem )]} ? time of one period: 7.5 ns if operating frequency is 133 mhz ? c des : 25 for des, 65 for 3des ? c mem2des : the cycle from external memory to desinfifo ? c des2mem : the cycle from desoutfifo to external memory S3C2500B gdma contr oller 12 - 1 12 gdma controller 12.1 overview the S3C2500B has a six-channel general dma controller, called the gdma. the six-channel gdma performs the following data transfers without cpu intervention: memory-to-memory (memory to/from memory, memory to/from usb) external device-to-memory (external device to/from memory) huart0/1-to-memory (high-speed uart serial port0/1 to/from memory) des-to-memory (des to/from memory) the on-chip gdma can be started by software and/or an external gdma request (xgdma_req), huart0 request, huart1 request, or des request. software can also be used to restart a gdma operation after it has been stopped. the cpu can recognize when a gdma operation has been completed by software polling and/or when it receives an appropriate internally generated gdma interrupt. the S3C2500B gdma controller can increment or decrement source destination addresses and conduct 8-bit (byte), 16-bit (half-word) or 32-bit (word) data transfer. the gdma does not check the cache coherency. so software must ensure that source and destination addresses must be configured as non-cacheable in the memory system configuration when it configures the gdma channels. the local priority of six-channel gdma can be programmed by fixed priority or round-robin priority in similar manner to the ahb bus priority. please refer to chapter 4, the system configuration. 12.2 feature six gdma channels memory to memory data transfer memory to peripheral data transfer (high speed uart, des, usb) support for four external gdma request from gdma request pins (xgdma_req0 ? xgdma_req3) gdma controller s3c 2500b 12- 2 ahb bus mode selection mode selection mode selection mode selection port 18 data iopcon1[18] xgdma_ack0 port 19 data port 20 data port 21 data xgdma_req0 des huart0 xgdma_req1 des huart0 xgdma_req2 des huart0 xgdma_req3 des huart1 xgdma_req0 des huart1 xgdma_req1 des huart1 mode selection mode selection gdma channel 1 gdma_req gdma_ack gdma channel 2 gdma_req gdma_ack gdma channel 3 gdma_req gdma_ack gdma channel 4 gdma_req gdma_ack gdma channel 5 gdma_req gdma_ack gdma channel 0 gdma_req gdma_ack xgdma_ack1 xgdma_ack2 xgdma_ack3 iopcon1[19] iopcon1[20] iopcon1[21] figure 12-1. gdma controller block diagram S3C2500B gdma contr oller 12 - 3 12.3 gdma special registers table 12-1. gdma special registers overview registers address r/w description reset value dpric dprif dprir 0xf0051000 0xf0052000 0xf0053000 r/w r/w r/w gdma priority configuration register gdma programmable priority register for fixed gdma programmable priority register for round-robin 0 00000000 0x00543210 0x00000000 dcon0 dsar0 ddar0 dtcr0 drer0 dipr0 0xf0050000 0xf0050004 0xf0050008 0xf005000c 0xf0050010 0xf0050014 r/w r/w r/w r/w w r/wc gdma channel 0 control register gdma channel 0 source address register gdma channel 0 destination address register gdma channel 0 transfer count register gdma channel 0 run enable register gdma channel 0 interrupt pending register 0 00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 dcon1 dsar1 ddar1 dtcr1 drer1 dipr1 0xf0050020 0xf0050024 0xf0050028 0xf005002c 0xf0050030 0xf0050034 r/w r/w r/w r/w w r/wc gdma channel 1 control register gdma channel 1 source address register gdma channel 1 destination address register gdma channel 1 transfer count register gdma channel 1 run enable register gdma channel 1 interrupt pending register 0 00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 dcon2 dsar2 ddar2 dtcr2 drer2 dipr2 0xf0050040 0xf0050044 0xf0050048 0xf005004c 0xf0050050 0xf0050054 r/w r/w r/w r/w w r/wc gdma channel 2 control register gdma channel 2 source address register gdma channel 2 destination address register gdma channel 2 transfer count register gdma channel 2 run enable register gdma channel 2 interrupt pending register 0 00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 dcon3 dsar3 ddar3 dtcr3 drer3 dipr3 0xf0050060 0xf0050064 0xf0050068 0xf005006c 0xf0050070 0xf0050074 r/w r/w r/w r/w w r/wc gdma channel 3 control register gdma channel 3 source address register gdma channel 3 destination address register gdma channel 3 transfer count register gdma channel 3 run enable register gdma channel 3 interrupt pending register 0 00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 dcon4 dsar4 ddar4 dtcr4 drer4 dipr4 0xf0050080 0xf0050084 0xf0050088 0xf005008c 0xf0050090 0xf0050094 r/w r/w r/w r/w w r/wc gdma channel 4 control register gdma channel 4 source address register gdma channel 4 destination address register gdma channel 4 transfer count register gdma channel 4 run enable register gdma channel 4 interrupt pending register 0 00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 dcon5 dsar5 ddar5 dtcr5 drer5 dipr5 0xf00500a0 0xf00500a4 0xf00500a8 0xf00500ac 0xf00500b0 0xf00500b4 r/w r/w r/w r/w w r/wc gdma channel 5 control register gdma channel 5 source address register gdma channel 5 destination address register gdma channel 5 transfer count register gdma channel 5 run enable register gdma channel 5 interrupt pending register 0 00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 gdma controller s3c 2500b 12- 4 12.3.1 gdma programmable priority registers the gdma can support the fixed priority and the round-robin priority for the local arbitration of six gdma channels by register setting. especially, the gdma can program the priority order in the fixed priority mode as well as the ratio of the bus occupancy in the round-robin priority mode. the local priority of six channels of gdma can be programmed by the fixed priority or the round-robin priority in similar manner to the ahb bus priority. please refer to chapter 4, the system configuration. the gdma programmable priority registers are dpric (programmable priority register for configuration), dprif (programmable priority register for fixed) and dprir (programmable priority register for round- robin). if the gdma priority configuration register (0xf0051000) dpric = 0x1, the programmable fixed priority is run by dprif register. each gdma channel has its own fixed priority index. for example, the gdma channel 0 has the index 0. the reset value of dprif register is 0x00543210. the first field of dprif[3:0] indicates the highest priority. so, the gdma channel 0 has the highest priority in local arbitration when dpric = 0x1 and the dprif has the reset value. for example, dpric = 0x1 and the dprif is 0x00431520, the fixed priority order from the highest to the lowest is gdma channel 0, channel 2, channel 5, channel 1, channel 3, and channel 4. if the gdma priority configuration register (0xf0051000) dpric = 0x0, the programmable round-robin priority is run by dprir register. all gdma channels own their respective field position in dprir. the ratio of the bus occupancy can be programmed by writing an arbitrary value on each field. the arbitrary value can be from 0x0 to 0xf. the ratio of the bus occupancy of the gdma channel in the first field is (dprir0+1)/((dprir5+1)+(dprir4+1)+(dprir3+1)+(dprir2+1)+(dprir1+1)+(dprir0+1)). the reset value of dprir register is 0x0. so each gdma channel has the same bus occupancy ratio when dpric = 0x0 and the dprir has the reset value. for example, dpric = 0x0 and the dprir is 0x20f100, the expected ratios of the bus occupancy of the gdma channel 0, channel 1, channel 2, channel 3, channel 4, and channel 5 are 1/24, 1/24, 2/24, 16/24, 1/24, and 3/24, respectively. table 12-2. gdma programmable priority registers register address r/w description reset value dpric 0xf0051000 r/w gdma priority configuration register 0x00000000 dprif 0xf0052000 r/w gdma programmable priority register for fixed 0x00543210 dprir 0xf0053000 r/w gdma programmable priority register for round- robin 0x00000000 S3C2500B gdma contr oller 12 - 5 high priority low priority general dma index for dprif field for dprir channel 0 0 dprir[3:0] channel 1 1 dprir[7:4] channel 2 2 dprir[11:8] channel 3 3 dprir[15:12] channel 4 4 dprir[19:16] channel 5 5 dprir[23:20] dprif 16 15 12 11 8 7 4 3 0 19 20 23 24 31 dprif0 dprif1 dprif2 dprif3 dprif4 dprif5 reserved dprir 16 15 12 11 8 7 4 3 0 19 20 23 24 31 dprir0 dprir1 dprir2 dprir3 dprir4 dprir5 reserved [0] priority configuration 0 = round-robin 1 = fixed priority dpric 0 31 x 1 figure 12-2. gdma programmable priority registers gdma controller s3c 2500b 12- 6 12.3.1.1 problem solving with programmable round-robin S3C2500B has stuff to thing about with gdma arbiter. this only applies to gdma arbiter with round-robin priority. assuming all '0's are set for gdma programmable priority register for round-robin, hprir (all same bus occupancy in round-robin), and only three of six channels of gdma are used, the problem arises as follows. number dprir channel expected bus occupancy actual gdma channel run real system bus occupancy 1 0 gdma 0 1/3 gdma 0 1/6 2 0 gdma 1 1/3 gdma 1 1/6 3 0 gdma 2 1/3 gdma 2 1/6 4 0 not used 0 gdma 0 1/6 5 0 not used 0 gdma 0 1/6 6 0 not used 0 gdma 0 1/6 when dprir is 0x0 and only gdma channel 0, 1, and 2 are used, the expected bus occupancy for each channel is 1/3. however, S3C2500B does not work in that way, instead, gdma channel 0 gets 4/6 of the bus occupancy, gdma 1 1/6, and gdma 2 1/6. in short, gdma 0 is run four times more than gdma 1, and 2. this is because S3C2500B is designed to turn the bus occupancy to the next channel when there is non-used gdma channel. for instance, number 1: gdma 0 number 2: gdma 1 number 3: gdma 2 number 4: no gdma ? go to number 5: no gdma ? go to number 6: no gdma ? go to number 1: gdma 0 number 5: no gdma ? go to number 6: no gdma ? go to number 1: gdma 0 number 6: no gdma ? go to number 1: gdma 0 S3C2500B gdma contr oller 12 - 7 the following is the problem solving with software. 1. method 1 dprir channel expected bus occupancy real system bus occupancy dprir channel occupancy 0 gdma 0 1/3 4/6 0 gdma 0 1/3 0 gdma 1 1/3 1/6 3 gdma 1 1/3 0 gdma 2 1/3 1/6 t 3 gdma 2 1/3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 problem problem solving by method 1 writing "0x000330", instead of "0x0" will give each channel of three gdma with the same amount of bus occupancy. 2. method 2 dprir channel expected bus occupancy real system bus occupancy dprir channel occupancy 0 gdma 0 1/3 4/6 0 gdma 0 1/3 0 gdma 1 1/3 1/6 0 0 0 gdma 2 1/3 1/6 t 0 gdma 2 1/3 0 0 0 0 0 0 0 0 0 gdma 4 1/3 0 0 0 0 0 problem problem solving by method 2 with leaving dprir as "0x0" and using every other channel, each channel of three gdma gets the same bus occupancy, as seen above. gdma controller s3c 2500b 12- 8 gdma channel needed recommended problem solving recommended gdma channel used when s/w 2 1 method 2 0, 1, 2, 3, 4, or 5 2 method 2 0/3 or 1/4 or 2/5 3 method 2 0/2/4 or 1/3/5 4 method 1 n/a 5 method 1 n/a 6 method 2 1, 2, 3, 4, 5, and 6 this method works when 1, 2, 4, or 6 gdma channels are needed, but there is no solution when 4 or 5 gdma channels are needed. so we recommend that when you need 1, 2, 3, or 6 gdma channels, use method 2, and when you need 4 or 5 gdma channels, use method 1. S3C2500B gdma contr oller 12 - 9 12.3.2 gdma control registers table 12-3. dcon0/1/2/3/4/5 registers registers address r/w description reset value dcon0 0xf0050000 r/w gdma channel 0 control register 0 00000000 dcon1 0xf0050020 r/w gdma channel 1 control register 0 00000000 dcon2 0xf0050040 r/w gdma channel 2 control register 0x00000000 dcon3 0xf0050060 r/w gdma channel 3 control register 0x00000000 dcon4 0xf0050080 r/w gdma channel 4 control register 0x00000000 dcon5 0xf00500a0 r/w gdma channel 5 control register 0x00000000 table 12-4. gdma control register description bit number bit name description [0] run enable/disable setting this bit to "1", starts a gdma operation. to stop gdma, you must clear this bit to "0". you can use the drer (gdma run enable register) to manipulate this bit. by using the drer, other gdma control register values are not affected. [3:1] gdma mode selection 6 gdma modes can initiate a gdma operation: 1) software mode (memory-to-memory or memory to/from usb, "000"), 2) an external gdma request mode (xgdma_req, "001"), 3) huart tx mode (huart from memory, "010"), 4) huart rx mode (huart to memory, "011"), 5) des in mode (des from memory, "100"), 6) des out mode (des to memory, "101"). [4] single/block mode this bit determines the number of external gdma requests (xgdma_req 0-3) that are required for a gdma operation. in single mode, when [4] = "0", the S3C2500B requires an external gdma request for every gdma operation. in block mode, when [4] = "1", the S3C2500B requires only one external gdma request during the entire gdma operation. an entire gdma operation is defined as the operation of gdma until the counter value is zero. the block mode can be used only when gdma mode is external gdma request mode. [5] four-data burst mode if this bit is set to "1", gdma operates under four-data burst mode. four consecutive source addresses are read and then are written to the consecutive destination addresses. if four-data burst mode is set to "1", "transfer count register (dtcr)" should be set carefully because the four-data burst mode is executed during decreasing of the transfer count. but the misalign of "transfer counter register (dtcr)" can be supported. the four-data burst mode can be used only when gdma mode is software, external gdma request, or des mode. you can use four-data burst mode together with block mode of the external gdma requests. gdma controller s3c 2500b 12- 10 table 12-4. gdma control register description (continued) bit number bit name description [7:6] transfer size these bits determine the transfer data width to be one byte, one half-word, or one word. if you select a byte transfer operation, the source/destination address will be increased or decreased by one with each transfer. each half-word transfer increments or decrements the address by two, and each word transfer by four. note : in huart mode, you should set byte ("00") on transfer size (ts) [7:6] of dcon register. in des mode, you should set word ("10") on transfer size (ts) [7:6] of dcon register. [9:8] source address direction these bits control whether the source address will be increased ("00"), decreased ("01"), or fixed ("10") during a gdma operation. the "fixed" ("10") means the source address will not be changed during a gdma operation. you use this "fixed" feature when transferring data from a single source to multiple destinations. when dcon mode [3:1] is huart rx mode (huart to memory, "011") or des out mode (des to memory, "101"), these bits don?t care. [11:10] destination address direction these bits control whether the destination address will be increased ("00"), decreased ("01"), or fixed ("10") during a gdma operation. the "fixed" ("10") means the destination address will not be changed during a gdma operation. you use this "fixed" feature when transferring data from multiple sources to a single destination. when dcon mode [3:1] is huart tx mode (huart from memory, "010") or des in mode (des from memory, "100"), these bits don?t care. [12] interrupt enable if the interrupt enable bit is "1", a gdma interrupt is generated when gdma operation completes successfully. if this bit is "0", the gdma interrupt is not generated. if you stop the gdma operation by resetting the run enable bit, the gdma interrupt is not generated regardless of this bit. [16:13] external gdma ack count these bits control how many cycles of the external gdma acknowledgement signals provided. if the slow external devices want gdma service, the slow external devices can sample the external gdma ack signal by setting these bits. these bits provide the range of 1 and 16 cycles. if these bits are ?0000?, the single cycle of the external gdma ack are generated. if these bits are ?1111?, the 16 cycles of the external gdma ack are generated. [31] busy status when gdma starts, this read-only status bit is automatically set to "1". when it is "0", gdma is idle. this bit is a read-only bit. note : to ensure the reliability of gdma operations, the gdma control register bits must be configured independently and carefully. if you want four-bust-mode (dcon[5]), you should set both sd (dcon[9:8]) and dd (dcon[11:10]) to ?00" (increase). but sd (dcon[9:8]) and dd (dcon[11:10]) can be "10" (fixed) only for usb endpoints (software mode) and des in/out fifo (des mode) when four-burst-mode (dcon[5]) is set. S3C2500B gdma contr oller 12 - 11 [0] run enable (re) 0 = disable gdma operation 1 = enable gdma operation [3:1] mode selection (mode) 000 = software mode (memory to memory, or momory to/from usb) 001 = external request mode (for external devices) 010 = huart tx mode (huart from memory) 011 = huart rx mode (huart to memory) 100 = des in mode (des from memory) 101 = des out mode (des to memory) 110, 111 = reserved [4] single/block mode (sb) 0 = one xgdma_req initiates a single gdma operation 1 = one xgdma_req initiates a whole gdma operation [5] four-data burst enable (fb) 0 = disable 4-data burst mode 1 = enable 4-data burst mode [7:6] transfer size (ts) 00 = byte (8-bit) 01 = half-word (16-bit) 10 = word (32-bit) 11 = no use [9:8] source address direction (sd) 00 = increase source address 01 = decrease source address 10 = do not change source address (fixed) 11 = reserved [11:10] destination address direction (dd) 00 = increase destination address 01 = decrease destination address 10 = do not change destination address (fixed) 11 = reserved [12] interrupt enable (ie) 0 = do not generate a interrupt when gdma completes 1 = generate a interrupt when gdma completes successfully [16:13] external gdma ack cycle count (xcnt) 0000 = 1 cycle 0001 = 2 cycles 0010 = 3 cycles 0011 = 4 cycles 0100 = 5 cycles 0101 = 6 cycles 0110 = 7 cycles 0111 = 8 cycles 1000 = 9 cycles 1001 = 10 cycles 1010 = 11 cycles 1011 = 12 cycles 1100 = 13 cycles 1101 = 14 cycles 1110 = 15 cycles 1111 = 16 cycles [31] busy status (bs) 0 = gdma is idle 1 = gdma is active r e m o d e s b f b t s s d d d i e b s 31 16 13 12 11 10 9 8 7 6 5 4 3 1 0 17 x c n t reserved figure 12-3. gdma control register gdma controller s3c 2500b 12- 12 12.3.3 gdma source/destination address registers the gdma source/destination address registers contain the 32-bit source/destination addresses for gdma channels 0, 1, 2, 3, 4, and 5. these address registers cover the whole external memory space, including the special purpose registers. you have to reference the memory map of the S3C2500B (chapter 4) when you want to set these address registers. depending on the settings you make to the gdma control register (dcon), the source or destination addresses will either remain the same, or they will be increased or decreased. when dcon mode [3:1] is huart rx mode (huart to memory, "011") or des out mode (des to memory, "101"), the dsar register doesn?t care. also, when dcon mode [3:1] is huart tx mode (huart from memory, "010") or des in mode (des from memory, "100"), the ddar register doesn?t care. table 12-5. dsar0/1/2/3/4/5 and ddar0/1/2/3/4/5 registers registers address r/w description reset value dsar0 0xf0050004 r/w gdma channel 0 source address register 0x00000000 dsar1 0xf0050024 r/w gdma channel 1 source address register 0x00000000 dsar2 0xf0050044 r/w gdma channel 2 source address register 0x00000000 dsar3 0xf0050064 r/w gdma channel 3 source address register 0x00000000 dsar4 0xf0050084 r/w gdma channel 4 source address register 0x00000000 dsar5 0xf00500a4 r/w gdma channel 5 source address register 0x00000000 ddar0 0xf0050008 r/w gdma channel 0 destination address register 0x00000000 ddar1 0xf0050028 r/w gdma channel 1 destination address register 0x00000000 ddar2 0xf0050048 r/w gdma channel 2 destination address register 0x00000000 ddar3 0xf0050068 r/w gdma channel 3 destination address register 0x00000000 ddar4 0xf0050088 r/w gdma channel 4 destination address register 0x00000000 ddar5 0xf00500a8 r/w gdma channel 5 destination address register 0x00000000 31 0 source/destination address [31:0] source/destination address figure 12-4. gdma source/destination address register S3C2500B gdma contr oller 12 - 13 12.3.4 gdma transfer count registers the gdma transfer count register indicates the byte transfer rate, which runs at 24-bit, on gdma channels 0, 1, 2, 3, 4 and 5. whenever gdma transfer count register transmits the data of gdma, it will be diminished by transfer width. in other words, when transfer size (ts) is byte, it will be diminished at 1, in the case of half-word at 2 and word at 4. if it is set in four data burst mode, each value of gdma transfer count will be diminished at 4 times. but if the value of transfer count register is not a multiple of 4 times transfer size, the last misaligned data can be transferred by one transfer size. table 12-6. dtcr0/1/2/3/4/5 registers registers address r/w description reset value dtcr0 0xf005000c r/w gdma channel 0 transfer count register 0x00000000 dtcr1 0xf005002c r/w gdma channel 1 transfer count register 0x00000000 dtcr2 0xf005004c r/w gdma channel 2 transfer count register 0x00000000 dtcr3 0xf005006c r/w gdma channel 3 transfer count register 0x00000000 dtcr4 0xf005008c r/w gdma channel 4 transfer count register 0x00000000 dtcr5 0xf00500ac r/w gdma channel 5 transfer count register 0x00000000 31 24 23 0 transfer count reserved [23:0] transfer count figure 12-5. gdma transfer count register gdma controller s3c 2500b 12- 14 12.3.5 gdma run enable registers the gdma run enable register (drer) can enable or disable the run enable bit, dcon[0] of the gdma control register (dcon). the drer register is write-only register. table 12-7. drer0/1/2/3/4/5 registers registers address r/w description reset value drer0 0xf0050010 w gdma channel 0 run enable register 0xxxxxxxx0 drer1 0xf0050030 w gdma channel 1 run enable register 0xxxxxxxx0 drer2 0xf0050050 w gdma channel 2 run enable register 0xxxxxxxx0 drer3 0xf0050070 w gdma channel 3 run enable register 0xxxxxxxx0 drer4 0xf0050090 w gdma channel 4 run enable register 0xxxxxxxx0 drer5 0xf00500b0 w gdma channel 5 run enable register 0xxxxxxxx0 31 1 0 [0] run enable reserved r e figure 12-6. gdma run enable register S3C2500B gdma contr oller 12 - 15 12.3.6 gdma interrupt pending register the gdma interrupt pending register (dipr) indicates the pending state of gdma interrupt by the pending bit [0] of the dipr register. the dipr[0] is active high. the dipr[0] can be asserted after the gdma operation completes successfully when the interrupt enable field of dcon[12] is "1". once the gdma interrupt service routine is called, the dipr[0] should be de-asserted by writing "1" on dipr[0] in the beginning of the gdma interrupt service routine. table 12-8. dipr0/1/2/3 registers registers address r/w description reset value dipr0 0xf0050014 r/wc gdma channel 0 interrupt pending register 0xxxxxxxx0 dipr1 0xf0050034 r/wc gdma channel 1 interrupt pending register 0xxxxxxxx0 dipr2 0xf0050054 r/wc gdma channel 2 interrupt pending register 0xxxxxxxx0 dipr3 0xf0050074 r/wc gdma channel 3 interrupt pending register 0xxxxxxxx0 dipr4 0xf0050094 r/wc gdma channel 4 interrupt pending register 0xxxxxxxx0 dipr5 0xf00500b4 r/wc gdma channel 5 interrupt pending register 0xxxxxxxx0 31 1 0 reserved i p [0] interrupt pending figure 12-7. gdma interrupt pending register gdma controller s3c 2500b 12- 16 12.4 gdma mode operation 12.4.1 software mode it is the mode that gdma operates without specific request signal with just setting the enable bit of control register by software. when we want to enable the operation, the data transmission is started by setting [3:1] of gdma mode selection bit of dcon register to ?000? and [0] bit of the same register to ?1?. this mode can transmit data between the memories by sending the data, which is designated by the source address register to the destination address register. the data transmission size can be byte, half-word, or word. it is determined by setting [7:6] bit of dcon register. without special usb mode setting of endpoint, read/write are possible. that is, by writing an address of usb endpoint into source address register or destination address register, read/write is possible. also, it is possible to read and write any function registers or buffer/fifo by gdma controller. 12.4.2 external gdma request mode gdma of S3C2500B has four external gdma request (xgdma_req) sources. xgdma_req signal and xgdma_ack signal can be shared with port signals. so it is used by setting i/o ports register (iopcon1). (refer to chapter 15, i/o ports). external device sending xgdma_req transmits the data by gdma during receiving xgdma_ack signal. also external gdma request mode is used by setting gdma mode selection bit [3:1] of dcon register to ?001?. it is similar to the basic operation mode of software, but it is different that gdma transmits the data only after receiving xgdma_req signal. the first external gdma request xgdma_req0 can be serviced by gdma channel 0 and 4. the second external gdma request xgdma_req1 can be serviced by gdma channel 1 and 5. the third external gdma request xgdma_req2 can be serviced by gdma channel 2. the fourth external gdma request xgdma_req3 can be serviced by gdma channel 3. if the slow external devices need the gdma service, the slow external devices can sample the external gdma ack signal by setting dcon [16:13] bits. dcon [16:13] bits provide the range of 1 and 16 cycles of the external gdma ack signal. note the block mode can be used only with the external gdma request mode. 12.4.3 huart mode S3C2500B has two huarts. gdma channel 0,1,2 can transmit the data of huart0. gdma channel 3,4,5 can transmit the data of huart1. if gdma mode selection bit [3:1] to ?010? or ?011?, gdma gets ready to communicate with huart. if gdma mode is "010" (huart tx mode) and gdma receives the request signal transmitted from huart, gdma transfers tx data of huart in memory into tx buffer/fifo of huart. if gdma mode is "011" (huart rx mode) and gdma receives the request signal transmitted from huart, gdma transfers rx data of rx buffer/fifo of huart into memory. when gdma transmits the data of huart, gdma operates in the unit of byte. if it is requested by huart, only one byte is transmitted and gdma waits the following request. (at this time if gdma transfer count register is zero, the operation ends.) note in huart mode, you should set byte (?00?) on transfer size (ts) [7:6] of dcon register. in huart tx mode, you don?t need to care the destination address direction (dd) [11:10] of dcon register either the ddar register. in huart rx mode, you don?t need to care the source address direction (sd) [9:8] of dcon register either the dsar register. S3C2500B gdma contr oller 12 - 17 12.4.4 des mode S3C2500B has only one des. any channel of gdma can transmit the data of des. if gdma mode selection bit "100" or "101", gdma gets ready to communicate with des. if gdma mode is "100" (des in mode) and gdma receives the request signal transmitted from des, gdma transfers in data of des in memory into in buffer/fifo of des. if gdma mode is ?101? (des out mode) and gdma receives the request signal transmitted from des, gdma transfers out data of out buffer/fifo of des into memory. note when gdma is des mode, gdma transmits two words by single request. when gdma is des mode and four-burst mode is enabled, gdma transmits four words by single request. but dtcr register only has to be a multiple of 8 (2 words), because gdma can transmit the last misaligned data. (at this time if gdma count register is zero, the operation is ended.) in des mode, you should set word ("10") on transfer size (ts) [7:6] of dcon register. in des in mode, you don't need to care the destination address direction (dd) [11:10] of dcon register either the ddar register. in des out mode, you don't need to care the source address direction (sd) [9:8] of dcon register either the dsar register. 12.5 gdma function description the following sections provide a functional description of the gdma controller operations. 12.5.1 gdma transfers the gdma transfers data directly between a requester and a target. the requester and target can be memory, huart0, huart1, des, special function registers, usb endpoints, or external devices. an external device requests the gdma service by activating xgdma_req signal. a channel is programmed by writing to registers, which contain the requester address, the target address, the amount of data, and other control contents. huart0, huart1, des, external i/o, or software (memory) can request gdma service. huart0, huart1 and des are internally connected to the gdma. 12.5.2 starting/ending gdma transfers gdma starts to transfer data after the gdma receives service request from xgdma_req signal, huart0, huart1, des, or software. when the entire buffer of data has been transferred, the gdma becomes idle. if you want to perform another buffer transfer, the gdma must be reprogrammed. although the same buffer transfer will be performed again, the gdma must be reprogrammed. gdma controller s3c 2500b 12- 18 12.5.3 data transfer modes 12.5.3.1 single mode a gdma request (xgdma_req or an internal request) causes one byte, one half-word, or one word to be transmitted if four-data burst mode is disabled, or four times of transfer size if four-data burst mode is enabled. single mode requires a gdma request for each data transfer. the xgdma_req signal can be de-asserted after checking that xgdma_ack has been asserted. xgdma_req xgdma_ack rd/wr cycle figure 12-8. external gdma requests (single mode) 12.5.3.2 block mode the assertion of only one gdma request (xgdma_req or an internal request) causes all of the data, as specified by the control register settings, to be transmitted in a single operation. the gdma transfer is completed when the transfer counter value reaches zero. the xgdma_req signal can be de-asserted after checking that xgdma_ack has been asserted. xgdma_req xgdma_ack rd/wr cycle figure 12-9. external gdma requests (block mode) S3C2500B gdma contr oller 12 - 19 12.6 gdma transfer timing data figure 12-10 provides the detailed timing data for gdma data transfers that are triggered by external gdma requests. please note that read/write timing depends on which memory banks are selected. the S3C2500B has the internal clock, hclk, as the operating clock. the clock frequency of hclk is 133mhz, internal clk (hclk) xgdma_req xgdma_ack txdar min.2 cycle txdrs txdrh txdaf programmable by dcon[16:13] ~ ~ ~ ~ ~ ~ txdrs setup time txdrh hold time txdar delay (rising) txdaf delay (falling) 6.5 nsec worst best 0 nsec 7.982 nsec 3.103 nsec 8.002 nsec 2.703 nsec figure 12-10. external gdma requests detailed timing gdma controller s3c 2500b 12- 20 12.6.1 single and one data burst mode (dcon[3:1] = 001, [4] = 0, [5] = 0) xgdma_req and xgdma_ack signals are active high. notes: 1. in this region, gdma operation is independent of the number of xgdma_req signal pulse. for example, although xgdma_req signal pulses 3 times in the ' ' region, gdma transfers data only one time from source address to destination address. current xgdma_req signal is idle state (deasserted) when xgdma_ack siganl is idle state (high). otherwise, gdma recognizes current xgdma_req signal as next one and transfers next data. i recommand that xgdma_req signal is deasserted when xgdma_ack signal is active. 2. ' ' is minimum two cycles. 3. ' ' can be programmed by setting dcon[16:13]. ' ' can be between 1 and 16 cycles. hclk xgdma_req recommand deasserted time xgdma_ack address data source addr dest. addr source data dest. data a ~ ~ c b ~ ~ a b c c figure 12-11. single and one data burst mode timing S3C2500B gdma contr oller 12 - 21 12.6.2 single and four data burst mode (dcon[3:1] = 001, [4] = 0, [5] = 1) xgdma_req & xgdma_ack signals are active high. in four data burst mode, gdma transfers four data and gdma transfer count register (dtcr) value decreases by four. but if the value of transfer count register is not a multiple of 4 times transfer size, the last misaligned data can be transferred by one transfer size. hclk xgdma_req recommand deasserted time xgdma_ack address data dtcr n n-4 note: addres s o rder is source address0 -> source address1 -> source address 2 -> source address3 -> destination address0 -> destination address1 -> destination address2 -> destination address3, and data order is source data0 -> source data1 -> source data2 -> source data3 -> destination data0 -> destination data1 -> destination data2 -> destination data3. sa0 sa1 sa2 sa3 da0 da1 da2 da3 sd0 sd1 sd2 sd3 dd0 dd1 dd2 dd3 programmable by dcon[16:13] ~ ~ ~ ~ ~ ~ figure 12-12. single and four data burst mode timing gdma controller s3c 2500b 12- 22 12.6.3 block and one data burst mode (dcon[3:1] = 001, [4] = 1, [5] = 0) xgdma_req and xgdma_ack signals are active high. gdma transfers data from single xgdma_req signal till gdma transfer count register (dtcr) consumes to 0. hclk xgdma_req recommand deasserted time xgdma_ack address data note: ' ' is in the block mode, gdma starts to operate with first xgdma_req signal. so in the ideal case, gdma does not care the number of xgdma_req signal pulse. but i recommand that xgdma_req siganl is deasserted when xgdma_ack signal is active state. sa0 da0 sd0 dd0 sa1 da1 sd1 dd1 programmable by dcon[16:13] programmable by dcon[16:13] ~ ~ ~ ~ a a ~ ~ ~ ~ ~ ~ figure 12-13. block and one data burst mode timing S3C2500B gdma contr oller 12 - 23 12.6.4 block and four data burst (dcon[3:1] = 001, [4] = 1, [5] = 1) this timing diagram is the same with block and one data burst, except that it is four data burst. hclk xgdma_req recommand deasserted time xgdma_ack address data note: ' ' is in the block mode, gdma starts to operate with first xgdma_req signal. so in the ideal case, gdma does not care the number of xgdma_req signal pulse. but i recommand that xgdma_req siganl is deasserted when xgdma_ack signal is active state. programmable by dcon[16:13] ~ ~ a sa2 sa3 sa1 sa0 da0 da1 da2 da3 a ~ ~ sd2 sd3 sd1 sd0 dd0 dd1 dd2 dd3 ~ ~ figure 12-14. block and four data burst timing one data burst; source address0 and source data0 ? destination address0 and destination data0 ? .... four data burst; source address0 and source data0 ? source address1 and source data1 ? source address2 and source data2 ? source address3 and source data3 ? destination address0 and destination data0 ? destination address1 and destination data1 ? destination address2 and destination data2 ? destination address3 and destination data3 ? source address4 and source data4 ? ... note in four data burst mode, gdma transfers four data and gdma transfer count register (dtcr) value decreases by four. gdma controller s3c 2500b 12- 24 notes S3C2500B serial i/o (console uart) 13- 1 13 serial i/o (console uart) 13.1 overview the S3C2500B console uart (universal asynchronous receiver/transmitter) unit provides one independent asynchronous serial i/o (sio) port. the port can operate in interrupt-based mode. that is, the console uart can generate internal interrupts to transfer data between the cpu and the serial i/o port. 13.2 features the most important features of the S3C2500B console uart include: programmable baud rates console uart source clock selectable (internal clock: pclk2, external clock: ext_uclk) (pclk2 = pclk / 2) infra-red (ir) transmit/receive insertion of one or two stop bits per frame selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers parity checking sio unit has a baud rate generator, transmitter, receiver, and a control unit, as shown in figure 13-1. the baud- rate generator can be driven by the internal system clock, pclk2, or by the external clock, ext_uclk. the transmitter and receiver blocks have independent data registers and shifters. transmit data is written first to the transmit data register. from there, it is copied to the transmit shifter and then shifted out by the transmit data pin, cutxd. receive data is shifted in by the receive data pin, curxd. it is then copied from the shifter to the receive data register when one data byte has been received. the sio control unit provides software controls for mode selection, and for status and interrupt generation. in S3C2500B, software flow control can be selected according to the application. the sio control unit supports echo mode. received data from curxd send to not only curxbuf but also cutxd. this mode is for test only. serial i/o (console uart) S3C2500B 13- 2 s y s t e m b u s control character1,2 (cuchar1,2) uart status register (custat) uart interrupt enable (cuint) uart control register (cucon) transmit shift register transmit data register (cutxbuf) receive shift register receive data register (curxbuf) ir rx decoder curxd 0 1 ir tx encoder 0 1 baud rate divisor baud rate generator cutxd figure 13-1. console uart block diagram S3C2500B serial i/o (console uart) 13- 3 13.3 console uart special registers table 13-1. console uart special registers overview register address r/w description size reset value cucon 0xf0060000 r/w console uart control register w 0x00000000 custat 0xf0060004 r/w console uart status register w 0x00060800 cuint 0xf0060008 r/w console uart interrupt enable register w 0x00000000 cutxbuf 0xf006000c w console uart transmit data register b ? curxbuf 0xf0060010 r console uart receive data register b ? cubrd 0xf0060014 r/w console uart baud rate divisor register h 0x0000 cuchar1 0xf0060018 r/w console uart control character register 1 w 0x00000000 cuchar2 0xf006001c r/w console uart control character register 2 w 0x00000000 serial i/o (console uart) S3C2500B 13- 4 13.3.1 console uart control registers table 13-2. cucon registers register address r/w description size reset value cucon 0xf0060000 r/w console uart control register w 0x00000000 table 13-3. console uart control register description bit number bit name description [1:0] transmit mode (tmode) this two-bit value determines which function is currently able to write tx data to the console uart transmit data register, cutxbuf. 00 = disable tx mode 01 = cpu request 10 = reserved 11 = reserved [3:2] receive mode (rmode) this two-bit value determines which function is currently able to read rx data from the console uart receive data register, curxbuf. note: changing these bits (tmode, rmode) while transmitting / receiving cause abnormal uart operation. to prevent tx/rx data from being lost, changing these bits while transmitting/receiving is strictly prohibited. 00 = disable rx mode 01 = cpu request 10 = reserved 11 = reserved [4] send break (sbr) set this bit to one to cause the console uart to send a break. if this bit value is zero, a break does not send. a break is defined as a continuous low level signal on the transmit data output with the duration of more than one frame transmission time. [5] serial clock select (scsel) this select bit specifies the clock source 0 = internal (pclk2) 1 = external (ext_uclk) [6] reserved [7] loop-back mode (loopb) setting this bit causes the console uart to enter loop-back mode. in loop-back mode, the transmit data output, cutxd, keeps '1' and the transmit data register, cutxbuf, is internally connected to the receive data register, curxbuf. note: this mode is provided for test purposes only. for normal operation, this bit should always be '0'. [10:8] parity mode (pmd) the 3-bit parity mode value specifies how parity generation and checking are performed during console uart transmit and receive operations: 0xx = no parity 100 = odd parity 101 = even parity 110 = parity is forced/checked as a '1' 111 = parity forced/checked as a '0' [11] number of stop bits (stb) this bit specifies how many stop bits are used to signal end-of- frame (eof): 0 = one stop bit per frame 1 = two stop bit per frame S3C2500B serial i/o (console uart) 13- 5 table 13-3. console uart control register description (continued) bit number bit name description [13:12] word length (wl) this two bit word length value indicates the number of data bits to be transmitted or received per frame: 00 = 5-bit 01 = 6-bit 10 = 7-bit 11 = 8-bit [14] infra-red mode (ir) the S3C2500B console uart block supports infra-red (ir) transmit and receive operations. in ir mode, the transmit period is pulsed at a rate of 3/16 that of the normal serial transmit rate (when the transmit data value in the cutxbuf register is zero). to enable ir mode operation, you set cucon[14] to '1'. otherwise, the console uart operates in normal mode. in ir receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value in the receiver data register, curxbuf, as the ir receive data. when this bit is '0', normal console uart mode is selected. when it is '1', infra-red tx/rx mode is selected. note: changing this bit while transmitting cause one tx data losing. because level of infra-red frame start bit and idle state of normal frame are identically high. [28:15] reserved [29] software flow control enable (sfen) this bit determines whether console uart select software flow control or not. if you set cucon[29] to '1', console uart will act in software flow control. in this mode, you have to use control character register. [30] echo mode enable (echo) if you set cucon[30] to '1', rx data is sent not only curxbuf but also tx port directly, so cutxbuf data will not be transmitted. [31] reserved serial i/o (console uart) S3C2500B 13- 6 w l p m d l o o p b s t b r m o d e t m o d e i r s f e n 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 24 21 18 17 16 13 12 11 8 7 6 e c h o s c s e l s b r [1:0] sio transmit mode selection (tmode) 00 = disable 01 = cpu request 10 = reserved 11 = reserved [3:2] sio receive mode selection (rmode) 00 = disable 01 = cpu request 10 = reserved 11 = reserved [4] send break (sbr) 0 = send normal txdata 1 = send break signal [5] serial clock select (scsel) 0 = internal (pclk2) 1 = external (ext_uclk) [6] reserved (this bit should be cleared) [7] loopback mode (loopb) 0 = normal operating mode. 1 = enable loopback mode (only for test) [10:8] parity mode (pmd) 0xx = no parity. 100 = odd parity. 101 = even parity. 110 = parity forced/checked as 1 111 = parity forced/checked as 0 [11] stop bits (stb) 0 = 1 stop bit 1 = 2 stop bits. [13:12] word length (wl) 00 = 5-bit 01 = 6-bit 10 = 7-bit 11 = 8-bit [14] infra-red mode (ir) 0 = normal operating mode 1 = infra-red tx/rx mode figure 13-2. console uart control register S3C2500B serial i/o (console uart) 13- 7 s b r w l p m d l o o p b s t b r m o d e t m o d e i r s f e n 31 0 3 4 5 1 2 30 29 28 26 25 23 22 20 19 15 14 10 24 21 18 17 16 13 12 11 8 7 6 e c h o s c s e l [28:15] reserved (this bit should be cleared) [29] software flow control enable (sfen) 0 = disable software flow control 1 = enable software flow control [30] echo test enable (echo) 0 = disable echo test 1 = enable echo test [31] reserved (this bit should be cleared) figure 13-3. console uart control register serial i/o (console uart) S3C2500B 13- 8 13.3.2 console uart status registers table 13-4. custat registers register address r/w description size reset value custat 0xf0060004 r/w console uart status register w 0x00060800 table 13-5. console uart status register description bit number bit name description [0] receive data valid (rdv) this bit is automatically set to one when curxbuf contains a valid data received over the serial port. the received data can be read from curxbuf. when this bit is '0', there is no valid data. if you set cucon[3:2] to 2'b01 and cuint[0] to 1'b1, the rdv interrupt is requested. you can clear this bit by reading curxbuf. [1] break signal detected (bkd) this bit is automatically set to one to indicate that a break signal has been received in curxbuf. if the bkd interrupt enable bit, cuint[1], is '1', a interrupt is generated when a break occurs. you have to clear this bit by writing '1' to this bit. if not, uart may be stopped. [2] frame error (fer) this bit is automatically set to '1' whenever a frame error occurs during a serial data receiving operation. a frame error occurs when a zero is detected instead of the stop bit(s). if the fer interrupt enable bit, cuint[2], is '1' a interrupt is generated when a frame error occurs. you have to clear this bit by writing '1' to this bit. if not, uart may be stopped. [3] parity error (per) this bit is automatically set to '1' whenever a parity error occurs during a serial data receiving operation. if the per interrupt enable bit, cuint[3], is '1', a interrupt is generated when a parity error occurs. you have to clear this bit by writing '1' to this bit. if not, uart may be stopped. S3C2500B serial i/o (console uart) 13- 9 table 13-5. console uart status register description (continued) bit number bit name description [4] overrun error (oer) this bit is automatically set to '1' whenever an overrun error occurs during a serial data receiving operation. when curxbuf has a previous valid data and a new received data is going to be written into curxbuf, custat[4] is set to '1'. if the oer interrupt enable bit, cuint[4], is '1', a interrupt is generated when a overrun error occurs. you have to clear this bit by writing '1' to this bit. if not, uart may be stopped. [5] control character detect (ccd) custat[5] is automatically set to '1' to indicate that a control character has been received. if the ccd interrupt enable bit, cuint[5], is '1', an interrupt is generated when a control character is detected. you can clear this bit by writing '1' to this bit. note: software flow control mode does not affects tx/rx operation this bit. this bit informs only whether uart receives control character or not. namely, if user want to stop tx/rx operation. user must program that routine. [10:6] reserved [11] receiver in idle (rxidle) this bit is only for cpu to monitor the receiver state of console uart. the rxidle status bit indicates inactive state of curxbuf. [16:12] reserved [17] transmitter idle (ti) custat[17] is automatically set to '1' when the transmit holding register has no valid data to transmit and when the tx shift register is empty. the reset value is '1' [18] transmit holding register empty (the) when cutxbuf is empty without regarding tx shift register , this bit set to '1'. an interrupt is generated when custat[18] is '1', cucon[1:0] is '01', and cuint[18] is '1'. you can clear this bit by writing some data into cutxbuf. [31:19] reserved serial i/o (console uart) S3C2500B 13- 10 [0] receive data valid (rdv) 0 = no valid data (receive fifo top or curxbuf) 1 = valid data present (receive fifo top or curxbuf) [1] break signal deteced (bkd) 0 = no break signal (receive fifo top or curxbuf) 1 = break received [2] frame error (fer) 0 = no frame error (receive fifo top or curxbuf) 1 = frame error occured [3] parity error (per) 0 = no frame error (receive fifo top or curxbuf) 1 = parity error occured [4] overrun error (oer) 0 = no overrun error (receive fifo top or curxbuf) 1 = overrun error occured [5] control character detect (ccd) 0 = no control character (receive fifo top or curxbuf) 1 = control character present (receive fifo top or curxbuf) [10:6] reserved [11] receiver in idle (idle) 0 = receiver is in active state 1 = receiver is in idle state [16:12] reserved [17] transmitter idle (ti) 0 = transmit is in progress 1 = transmitter is in idle: no data for tx [18] transmit holding register empty (the) 0 = tranmit holding register is not empty 1 = transmit holding register is empty [31:19] reserved c c d o e r t h e t i i d l e f e r r d v b k d p e r 31 0 3 4 5 1 2 19 10 18 17 16 12 11 6 figure 13-4. console uart status register S3C2500B serial i/o (console uart) 13- 11 13.3.3 console uart interrupt enable register table 13-6. cuint registers register address r/w description size reset value cuint 0xf0060008 r/w console uart interrupt enable register w 0x00000000 table 13-7. console uart interrupt enable register description bit number bit name description [0] rdvie receive data valid interrupt enable [1] bkdie break signal detected interrupt enable [2] ferie frame error interrupt enable [3] perie parity error interrupt enable [4] oerie overrun error interrupt enable [5] ccdie control character detect interrupt enable [16:6] reserved [17] tiie transmitter idle interrupt enable [18] theie transmit holding register empty interrupt enable [31:19] reserved serial i/o (console uart) S3C2500B 13- 12 [0] receive data valid interrupt enable (rdvie) [1] break signal detected interrupt enable (bkdie) [2] frame error interrupt enable (ferie) [3] parity error interrupt enable (perie) [4] overrun error interrupt enable (oerie) [5] control character detect interrupt enable (ccdie) [16:6] reserved [17] transmitter idle (tiie) [18] transmit holding register empty interrupt enable (theie) [31:19] reserved c c d i e o e r i e t h e i e t i i e f e r i e r d v i e b k d i e p e r i e 31 0 3 4 5 1 2 19 18 17 16 6 figure 13-5. console uart interrupt enable register S3C2500B serial i/o (console uart) 13- 13 13.3.4 uart transmit data register table 13-8. cutxbuf registers register address r/w description size reset value cutxbuf 0xf006000c w console uart transmit data register b ? table 13-9. console uart transmit register description bit number bit name description [7:0] transmit data this field contains the data to be transmitted over the single channel console uart. when this register is written, the transmit data register empty bit in the status register, custat[18], should be ?1?. this is to prevent overwriting of transmit data that may already be present in the cutxbuf. whenever the cutxbuf is written with a new value, the transmit register empty bit, custat[18], is automatically cleared to ?0?. 31 [7:0] transmit data for uart transmit data 0 7 8 figure 13-6. console uart transmit data register serial i/o (console uart) S3C2500B 13- 14 13.3.5 uart receive data register table 13-10. curxbuf registers register address r/w description size reset value curxbuf 0xf0060010 r console uart receive data register b ? table 13-11. console uart receive register description bit number bit name description [7:0] receive data this field contains the data received over the single channel console uart. when the console uart finishes receiving a data frame, the receive data ready bit in the console uart status register, custat[0], should be ?1?. this prevents reading invalid receive data that may already be present in the curxbuf. whenever the curxbuf is read, the receive data valid bit (custat[0]) is automatically cleared to ?0?. 31 [7:0] receive data for uart receive data 0 7 8 figure 13-7. console uart receive data register S3C2500B serial i/o (console uart) 13- 15 13.3.6 uart baud rate divisor register the values stored in the baud rate divisor registers, cubrd, let you determine the serial tx/rx clock rate (baud rate) as follows: brgout = pclk2 or ext_uclk (cnt0+1) 16 cnt1 16 table 13-12. cubrd registers register address r/w description size reset value cubrd 0xf0060014 r/w console uart baud rate divisor register h 0x0000 [3:0] baud rate divisor value cnt1 xxx0 = divide by 1 xxx1 = divide by 16 [15:4] time constant value for cnt0 31 15 16 0 18 17 19 21 20 22 23 24 25 26 27 28 29 30 cnt0 4 3 cnt1 figure 13-8. console uart baud rate divisor register serial i/o (console uart) S3C2500B 13- 16 13.3.7 console uart baud rate examples if the system clock frequency is 133 mhz and pclk2 is selected, the maximum brgout output clock rate is pclk2/16 (= 4,156,250 hz). ext_uclk is the external clock input pin for console uart. pclk2 and ext_uclk can be selected by cucon[5] register. select clock pclk2 brgout ext_uclk 12-bit counter divide by 1 or 16 divide by 16 sample clock cnt0 cnt1 note: cnt0 = cubrd[15:4], cnt1 = cubrd[3:0], select clock = cucon[5] figure 13-9. console uart baud rate generator (brg) table 13-13. typical baud rates examples of console uart baud rates pclk2 = 66.5 mhz ext_uclk = 29.4912 mhz (brgout) cnt0 (dec/hex) cnt1 freq. dev.(%) cnt0 (dec/hex) cnt1 freq. dev.(%) 1200 3463/d87 0 1199.84 0.01 1535 /5ff 0 1200.00 0.00 2400 1731/6c3 0 2399.68 0.01 767 /2ff 0 2400.00 0.00 4800 865/361 0 4799.36 0.01 383 /17f 0 4800.00 0.00 9600 432/1b0 0 9598.73 0.01 191 /bf 0 9600.00 0.00 19200 215/d7 0 19241.90 0.01 95 /5f 0 19200.00 0.00 38400 107/6b 0 38483.80 0.22 47 /2f 0 38400.00 0.00 57600 71/47 0 57725.69 0.22 31 /1f 0 57600.00 0.00 115200 35/23 0 115451.39 0.22 15 /f 0 115200.00 0.00 S3C2500B serial i/o (console uart) 13- 17 13.3.8 uart control character register 1 and 2 these control character registers can be used for software flow control. in software flow control mode, you should write control characters into these registers. any character in these registers can be used as a software control flow character and you can use maximum 8 characters for it. table 13-14. cuchar 1, 2 registers register address r/w description size reset value cuchar1 0xf0060018 r/w console uart control character register 1 w 0x00000000 cuchar2 0xf006001c r/w console uart control character register 2 w 0x00000000 31 15 16 [7:0] control character 0 [15:8] control character 1 [23:16] control character 2 [31:24] control character 3 char0 0 24 23 7 8 char1 char3 char2 figure 13-10. console uart control character 1 register 31 15 16 [7:0] control character 4 [15:8] control character 5 [23:16] control character 6 [31:24] control character 7 char4 0 24 23 7 8 char5 char7 char6 figure 13-11. console uart control character 2 register serial i/o (console uart) S3C2500B 13- 18 S3C2500B serial i/o (console uart) 13- 19 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits sio frame figure 13-13. serial i/o frame timing diagram (normal console uart) 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits ir transmit frame bit frame = t 3/16t 7/16t 6/16t figure 13-14. infra-red transmit mode frame timing diagram serial i/o (console uart) S3C2500B 13- 20 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits ir receive frame bit frame = t 3/16t 13/16t figure 13-15. infra-red receive mode frame timing diagram S3C2500B serial i/ o (high-speed uart) 14- 1 14 serial i/o (high-speed uart) 14.1 overview the S3C2500B high-speed uart (universal asynchronous receiver/transmitter) unit provides two independent asynchronous serial i/o (sio) ports. high-speed uart can operate in interrupt-based or dma-based mode (dma 0, 1, 2 for high-speed uart channel 0, dma 3,4,5 for high-speed uart channel 1) that is, the high- speed uart can generate internal interrupts or dma requests to transfer data between the cpu and the serial i/o ports. 14.2 features the most important features of the S3C2500B high-speed uart include: programmable b aud rates 32-byte transmit fifo and 32-byte receive fifo high-speed uart source clock selectable (internal clock: pclk2, external clock: ext_uclk) (pclk2 = pclk / 2) infra-red (ir) transmit/receive insertion of one or two stop bits per frame selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers parity checking sio unit has a baud rate generator, transmitter, receiver, and a control unit, as shown in figure 14-1. the baud- rate generator can be driven by the internal system clock divided by 2, pclk2, or by the external clock, ext_ uclk. auto baud rate generator tries to get the baud rate from input data in this mode. the transmitter and receiver blocks have independent data buffer registers and data shifters. and 32-byte transmit fifo and 32- byte receive fifo is also provided which include transmit and receive buffer. in non-fifo mode, transmit data is written first to the transmit buffer register. from there, it is copied to the transmit shifter and then shifted out by the transmit data pin, hutxd0/ hutxd1. receive data is shifted in by the receive data pin, hurxd0/hurxd1. it is then copied from the shifter to the receive buffer register when one data byte has been received. otherwise, you can select fifo mode. in fifo mode, transmitter and receiver use transmit fifo and receive fifo, instead of tx/rx buffer register(hutxbuf/hurxbuf). they are controlled by each fifo trigger level. the sio control units provide software controls for mode selection, and for status and interrupt generation. in S3C2500B, software flow control or hardware flow control can be selected according to the application. serial i/o (high-speed uart) S3C2500B 14- 2 control and status block baudrate generator and detector modem control signal txbuffer register -------------- transmit fifo (32 bytes) transmit shift register rxbuffer register -------------- receiver fifo (32 bytes) ir tx encoder ir rx decoder 1 0 huart tx pin huart rx pin ext_uclk baud rate divisor transmit data receive data transmit control receive control receive status transmit status control character register pclk2 hucon : uclk hucon : ir s y s t e m b u s 0 1 0 1 uart_clk receiver shift register figure 14-1. high-speed uart block diagram S3C2500B serial i/ o (high-speed uart) 14- 3 14.3 high-speed uart special registers table 14-1. high-speed uart 0 special registers overview register address r/w description size reset value hucon 0xf0070000 r/w high-speed uart control register w 0x00000000 hustat 0xf0070004 r/w high-speed uart status register w ? huint 0xf0070008 r/w high-speed uart interrupt enable register w 0x00000000 hutxbuf 0xf007000c w high-speed uart transmit data register b ? hurxbuf 0xf0070010 r high-speed uart receive data register b ? hubrd 0xf0070014 r/w high-speed uart baud rate divisor register h 0x00000000 huchar1 0xf0070018 r/w high-speed uart control character register 1 w 0x00000000 huchar2 0xf007001c r/w high-speed uart control character register 2 w 0x00000000 huabb 0xf0070020 r/w high-speed uart autobaud boundary register w 0x1f0f0703 huabt 0xf0070024 r/w high-speed uart autobaud table register w 0x170b0502 table 14-2. high-speed uart 1 special registers overview register address r/w description size reset value hucon 0xf0080000 r/w high-speed uart control register w 0x00000000 hustat 0xf0080004 r/w high-speed uart status register w ? huint 0xf0080008 r/w high-speed uart interrupt enable register w 0x00000000 hutxbuf 0xf008000c w high-speed uart transmit data register b ? hurxbuf 0xf0080010 r high-speed uart receive data register b ? hubrd 0xf0080014 r/w high-speed uart baud rate divisor register h 0x00000000 huchar1 0xf0080018 r/w high-speed uart control character register 1 w 0x00000000 huchar2 0xf008001c r/w high-speed uart control character register 2 w 0x00000000 huabb 0xf0080020 r/w high-speed uart autobaud boundary register w 0x1f0f0703 huabt 0xf0080024 r/w high-speed uart autobaud table register w 0x170b0502 serial i/o (high-speed uart) S3C2500B 14- 4 14.3.1 high-speed uart control registers table 14-3. high-speed uart control registers registers address r/w description reset value hucon 0xf0070000 0xf0080000 r/w high-speed uart control register 0x00000000 table 14-4. high-speed uart control register description bit number bit name description [1:0] transmit mode (tmode) this two-bit value determine which function is currently able to write tx data to the high-speed uart transmit buffer register, hutxbuf. 00 = disable tx mode. 01 = interrupt request 10 = gdma request 11 = reserved (high-speed uart 0 can use only gdma 0,1,2 channel and, high-speed uart 1 can use only gdma 3,4,5 channel ) [3:2] receive mode (rmode) this two-bit value determine which function is currently able to read rx data to the high-speed uart receive buffer register, hurxbuf. note: changing these bits (tmode, rmode) while transmitting/receiving cause abnormal high-speed uart operation. to prevent tx/rx data from being lost, changing these bits while transmitting/receiving is strictly prohibited. 00 = disable rx mode. 01 = interrupt request 10 = gdma request 11 = reserved (high-speed uart 0 can use only gdma 0,1,2 channel and, high-speed uart 1 can use only gdma 3,4,5 channel ) [4] send break (sbr) set this bit to one to cause the high-speed uart to send a break. if this bit value is zero, a break does not send. a break is defined as a continuous low level signal on the transmit data output with the duration of more than one frame transmission time. [5] serial clock selection (scsel) this selection bit specifies the clock source. 0 = internal (pclk2) 1 = external (ext_uclk) [6] auto baud rate detect (aubd) setting this bit causes the high-speed uart to enter auto baud rate detect mode. in this mode, high-speed uart try to get the baud rate from input data. [7] loop-back mode (loopb) setting this bit causes the high-speed uart to enter loop-back mode. in loop-back mode, the transmit data output is sent high level and the transmit buffer register, hutxbuf, is internally connected to the receive buffer register, hurxbuf. note: this mode is provided for test purposes only. for normal operation, this bit should always be "0". [10:8] parity mode (pmd) the 3-bit parity mode value specifies how parity generation and checking are to be performed during high-speed uart transmit and receive operations. 0xx = no parity 100 = odd parity 101 = even parity 110 = parity is forced/checked as a "1" 111 = parity forced/checked as a "0" S3C2500B serial i/ o (high-speed uart) 14- 5 table 14-4. high-speed uart control register description (continued) bit number bit name description [11] number of stop bits (stb) this bit specifies how many stop bits are used to signal end-of- frame (eof). 0 = one stop bit per frame 1 = two stop bit per frame [13:12] word length (wl) this two bit word length value indicates the number of data bits to be transmitted or received per frame. 00 = 5-bit 01 = 6-bit 10 = 7-bit 11 = 8-bit [14] infra-red mode (ir) the S3C2500B high-speed uart block supports infra-red (ir) transmits and receive operations. in ir mode, the transmit period is pulsed at a rate of 3/16 that of the normal serial transmit rate (when the transmit data value in the hutxbuf register is zero). to enable ir mode operation, you set hucon[14] to "1". otherwise, the high-speed uart operates in normal mode. in ir receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value in the receiver buffer register, hurxbuf, as the ir receive data. when this bit is "0", normal high-speed uart mode is selected. when it is "1", infra-red tx/rx mode is selected. note: changing these bits while transmitting cause one tx data losing. because level of infra-red frame start bit and idle state of normal frame are identically high. [15] reserved this bit should be cleared by zero. [16] transmit fifo enable (tfen) S3C2500B high-speed uart block support 32 byte fifo. if this bit set to one, transmit data moved to tx fifo and then sent. [17] receive fifo enable (rfen) S3C2500B high-speed uart block support 32 byte fifo. if this bit set to one, receive data moved to rx fifo. note: changing these bits (tfen, rfen) while transmitting/receiving cause sending/receiving unexpected data. to prevent this, changing these bits while transmitting/receiving is strictly prohibited. [18] transmit fifo reset (tfrst) you set this bit to '1', transmit fifo will be reset. in this case, if there is data in transmit shift register, it will be sent. note: this bit will not cleared automatically. [19] receive fifo reset (rfrst) you set this bit to '1', receive fifo will be reset. in this case, if there is data in receive shift register, it will be received. note: this bit will not cleared automatically. [21:20] transmit fifo trigger level (tftl) this two bit trigger level value determines when the transmitter start to transmit data in 32-byte transmit fifo. 00 = 30-byte empty/32-byte 01 = 24/32 10 = 16/32 11 = 8/32 serial i/o (high-speed uart) S3C2500B 14- 6 table 14-4. high-speed uart control register description (continued) bit number bit name description [23:22] receive fifo trigger level (rftl) this two bit trigger level value determines when the receiver start to move the received data in 32-byte receive fifo. 00 = 1-byte valid/32-byte 01 = 8/32 10 = 18/32 11 = 28/32 [24] data terminal ready to pin (dtr) this bit directly controls the hundtr0/hundtr1 pin. setting this bit to one, the hundtr0/hundtr1 pin goes to low level. if you set this bit to zero, it goes high level. [25] request to send to pin (rts) this bit directly controls the high-speed uarts pin only when the high-speed uart is not hardware flow control mode. if this bit set to one, high-speed uarts pin goes low level. otherwise, it remains high level. [27:26] reserved this bit should be cleared by zero. [28] hardware flow control enable (hfen) this bit determines whether high-speed uart select hardware flow control or not. if this bit set to one, high-speed uart will control all pins concerning to hardware flow control. [29] software flow control enable (sfen) this bit determines whether high-speed uart select software flow control or not. if this bit set to one, high-speed uart will act in software flow control. in this mode, you have to use control character register. [30] echo mode (echo) if this bit is set to one, rx data is sent not only hurxbuf but also tx port directly, so hutxbuf data will not be transmitted. [31] rts/rtr selection (rts/rtr) this selection bit determines output of hunrts0/hunrts1 pin 0 = rts 1 = rtr note: in rxfifo mode, rtr goes to '1' when rxfifo is full, in nonrxfifo mode, rtr goes to '1' when rxbuf is not empty. S3C2500B serial i/ o (high-speed uart) 14- 7 [1:0] sio transmit mode selection (tmode) 00 = disable 01 = interrupt request 10 = gdma request 11 = reserved [3:2] sio receive mode selection (rmode) 00 = disable 01 = interrupt request 10 = gdma request 11 = reserved [4] send break (sbr) 0 = send normal txdata 1 = send break signal [5] serial clock selection (scsel) 0 = internal systen clock divided 2 (pclk2) 1 = external uart clock (uclk) [6] auto baud rate detect (aubd) 0 = normal operating mode. 1 = auto baud rate detect mode [7] loopback mode (loopb) 0 = normal operating mode. 1 = enable loopback mode (only for test) [10:8] parity mode (pmd) 0xx = no parity. 100 = odd parity. 101 = even parity. 110 = parity forced/checked as 1 111 = parity forced/checked as 0 [11] stop bits (stb) 0 = 1 stop bit 1 = 2 stop bits. [13:12] word length (wl) 00 = 5-bit 01 = 6-bit 10 = 7-bit 11 = 8-bit [14] infra-red mode (ir) 0 = normal operating mode. 1 = infra-red tx/rx mode [15] reserved (this bit should be cleared) 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 24 21 18 17 16 13 12 11 8 7 6 h f e n s c s e l s b r r t s d t r r f t l t f t l w l r f r s t t f r s t r f e n t f e n p m d l o o p b a u b d s t b r m o d e t m o d e i r s f e n e c h o r t s r t r figure 14-2. high-speed uart control register serial i/o (high-speed uart) S3C2500B 14- 8 [16] transmit fifo enable (tfen) 0 = disable transmit fifo 1 = enable transmit fifo [17] receive fifo enable (rfen) 0 = disable receive fifo 1 = enable receive fifo [18] tranmit fifo reset (tfrst) 0 = normal operation 1 = reset transmit fifo [19] receive fifo reset (rfrst) 0 = normal operation 1 = reset receive fifo [21:20] transmit fifo trigger level (tftl) 00 = 30/32 byte data 01 = 24/32 byte data 10 = 16/32 byte data 11 = 8/32 byte data (empty tx data / txfifo depth) [23:22] receive fifo trigger level (rftl) 00 = 1/32 byte data 01 = 8/32 byte data 10 = 18/32 byte data 11 = 28/32 byte data (valid rx data / rxfifo depth) [24] data terminal ready to pin (dtr) 0 = undtr0/undtr1 goes high level 1 = undtr0/undtr1 goes low level [25] request to send to pin (rts) 0 = unrts0/unrts1 goes high level 1 = unrts0/unrts1 goes low level [27:26] reserved (this bit should be cleared) [28] hardware flow control enable (hfen) 0 = disable hardware flow control 1 = enable hardware flow control [29] software flow control enable (sfen) 0 = disable software flow control 1 = enable software flow control [30] echo mode (echo) 0 = normal 1 = echo mode [31] rts/rtr selection (rts/rtr) 0 = rts 1 = rtr h f e n s c s e l s b r r t s d t r r f t l t f t l w l r f r s t t f r s t r f e n t f e n p m d l o o p b a u b d s t b r m o d e t m o d e i r s f e n 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 24 21 18 17 16 13 12 11 8 7 6 e c h o r t s r t r figure 14-2. high-speed uart control register (continued) S3C2500B serial i/ o (high-speed uart) 14- 9 14.3.2 high-speed uart status registers table 14-5. high-speed uart status registers registers offset address r/w description reset value hustat 0xf0070004 0xf0080004 r/w high-speed uart status register ? table 14-6. high-speed uart status register description bit number bit name description [0] receive data valid (rdv) this bit automatically set to one when receive fifo-top or hurxbuf contains a valid data received over the serial port. the received data can be read from receive fifo-top or hurxbuf . when this bit is "0", there is no valid data. according to the current setting of the high-speed uart receive mode bits, an interrupt or dma request is generated when hustat[0] is "1". in case of hucon[3:2]='01' and huint[0]=1,interrupt requested, and hucon[3:2]='10' or '11', dma request occurred. you can clear this bit by reading receive fifo or hurxbuf. note: whether receive fifo top or hurxbuf depends on the hucon[17]. [1] break signal detected (bkd) this bit automatically set to one to indicate that a break signal has been received in receive fifo-top or hurxbuf. if the bkd interrupt enable bit, huint[1], is "1", a interrupt is generated when a break occurs. you have to clear this bit by writing '1' to this bit. if not, uart may be stopped. [2] frame error (fer) this bit automatically set to "1" whenever a frame error occurs during a serial data receiving operation. a frame error occurs when a zero is detected instead of the stop bit(s). if the fer interrupt enable bit, huint[2], is "1", a interrupt is generated when a frame error occurs. you have to clear this bit by writing '1' to this bit. if not, uart may be stopped. [3] parity error (per) this bit automatically set to "1" whenever a parity error occurs during a serial data receiving operation. if the per interrupt enable bit, huint[3], is "1", a interrupt is generated when a parity error occurs. you have to clear this bit by writing '1' to this bit. if not, uart may be stopped. serial i/o (high-speed uart) S3C2500B 14- 10 table 14-6. high-speed uart status register description (continued) bit number bit name description [4] overrun error (oer) this bit automatically set to "1" whenever an overrun error occurs during a serial data receiving operation. when hurxbuf has a previous valid data, but a new received data is going to be written into hurxbuf during non-fifo mode and when a new received data is going to be written into rxfifo with fifo full during fifo mode. hustat[4] is set to '1'. if the oer interrupt enable bit, huint[4], is "1", a interrupt is generated when a overrun error occurs. you have to clear this bit by writing '1' to this bit. if not, uart may be stopped. [5] control character detect (ccd) hustat[5] is automatically set to "1" to indicate that a control character has been received. if the ccd interrupt enable bit, huint[5], is "1", an interrupt is generated when a control character is detected. you can clear this bit by writing '1' to this bit. note: software flow control mode does not affects tx/rx operation this bit. this bit informs only whether uart receives control character or not. namely, if user want to stop tx/rx operation. user must program that routine. [6] data carrier detect lost (dcdl) this bit set to 1, if hundcd0/hundcd1 pin is high at the time high- speed uart receiver checks a newly received data whether the data is good frame or not. if the dcd interrupt enable bit, huint[6], is "1", a interrupt is generated when a data carrier is detected. this bit can be used for error check bit in hardware flow control mode. [7] receive fifo data trigger level reach (rfrea) in receive fifo mode, this bit indicate receive fifo has valid data and reach rx trigger level. so high-speed uart request dma to move data in receive fifo. in non-fifo mode, if hurxbuf has a received data , this bit is set to '1' also, an interrupt or dma request is generated when hustat[7] is "1". in case of hucon[3:2]='01' and huint[7]=1,interrupt requested, and hucon[3:2]='10' or '11', dma request occurred. you can clear this bit by reading receive fifo or hurxbuf with a good data. if any error, this bit is cleared by writing '1' to corresponding error bit in hustat register. [8] receive fifo empty (rfemt) this bit is only for cpu to monitor high-speed uart. when receive fifo is empty, this bit is set to '1'. after reset, default value is '1' . [9] receive fifo full (rfful) this bit is only for cpu to monitor high-speed uart. when receive fifo is full, this bit is set to '1'. after reset, default value is '0' [10] receive fifo overrun (rfov) this bit is set to '1' when receive fifo overrun occurs during the receive fifo mode. you can clear this bit by writing '1' to this bit. [11] receiver in idle (ridle) this bit is only for cpu to monitor the receiver state of high-speed uart. the rxidle status bit indicates that the inactive state of rxdata. S3C2500B serial i/ o (high-speed uart) 14- 11 table 14-6. high-speed uart status register description (continued) bit number bit name description [12] receive event time out (e_rxto) during receive fifo mode, if there is a valid data in urxfifo or receive fifo within a promised time internal which is determined according to wl(word length) , this bit is set to '1' . urxfifo is for non-fifo mode and receive fifo is for fifo mode. if the e_rxto interrupt enable bit, huint[12], is "1", an interrupt is generated when a receive event time out is detected and valid data reside in hurxbuf or receive fifo. you can clear this bit by writing '1' to this bit. note: event time = wl*4 +12 this bit set to one when the rx data resides in rxfifo. [13] autobaud rate detection (aubddn) this bit is automatically set to "1" when high-speed uart finishes autobaud rate detection procedure. you can clear this bit by writing "1" to this bit. [14] data set ready (dsr) this bit is only for cpu to monitor high-speed uart. when hundsr0/hundsr1 level is low, this bit is set. and hundsr0/ hundsr1 high, this bit is cleared. [15] clear to send (cts) this bit is only for cpu to monitor high-speed uart. when huncts0/ huncts1 level is low , this bit is set. and huncts0/ huncts1 high, this bit is cleared. [16] cts event occurred (e_cts) this bit is set to '1' whenever huncts0/ huncts1 level changed. if the e_cts interrupt enable bit, huint[16], is "1", a interrupt is generated when a cts event is occurred. you can clear this bit by writing '1' to this bit. [17] transmitter idle (ti) hustat[17] is automatically set to ?1? when the transmit holding register has no valid data to transmit and when the tx shift register is empty. the reset value is '1' [18] transmit holding register empty (the) in transmit fifo mode, when transmit fifo is empty to trigger level, this bit set to '1'. in non-fifo mode, when hutxbuf is empty without regarding tx shift register , this bit set to '1'. an interrupt or dma request is generated when hustat[18] is "1". in case of hucon[1:0]='01' and huint[18]=1, an interrupt requested, and hucon[1:0]='10' or '11', dma request occurred. you can clear this bit by writing txdata into hutxbuf or transmit fifo. [19] transmit fifo empty (tfemt) this bit is only for cpu to monitor high-speed uart. when transmit fifo is empty, this bit is set to '1'. after reset, default value is '1' [20] transmit fifo full (tfful) this bit is only for cpu to monitor high-speed uart. when transmit fifo is full, this bit is set to '1'. after reset, default value is '0' . [31:21] reserved not applicable. serial i/o (high-speed uart) S3C2500B 14- 12 31 0 3 4 5 1 2 20 19 15 14 10 9 21 18 17 16 13 12 11 8 7 6 c c d o e r t f f u l e _ r x t o t f e m t t h e t i e _ c t s r f f u l r f r e a d c d l i d l e f e r r d v d s r b k d p e r r f e m t r f o v c t s [0] receive data valid (rdv) 0 = no valid data (receive fifo-top or hurxbuf) 1 = valid data present (receive fifo-top or hurxbuf) [1] break signal deteced (bkd) 0 = no break signal (receive fifo-top or hurxbuf) 1 = break received [2] frame error (fer) 0 = no frame error (receive fifo-top or hurxbuf) 1 = frame error occured [3] parity error (per) 0 = no frame error (receive fifo-top or hurxbuf) 1 = frame error occured [4] overrun error (oer) 0 = no overrun error (receive fifo-top or hurxbuf) 1 = overrun error occured [5] control character detect (ccd) 0 = no control character (receive fifo-top or hurxbuf) 1 = control character present (receive fifo-top or hurxbuf) [6] data carrier detect lost (dcdl) 0 = dcd pin is low at the receiver checking time 1 = dcd pin is high at the receiver checking time [7] receive fifo data trigger level reach (rfrea) 0 = no valid data in hurxbuf or not reached to trigger level 1 = in rxfifo mode, rxfifo has valid data and reach trigger level in non-fifo mode, hurxbuf has valid data [8] receive fifo empty (rfemt) 0 = receive fifo is not empty 1 = receive fifo is empty [9] receive fifo full (rfful) 0 = receive fifo is not full 1 = receive fifo is full [10] receive fifo overrun (rfov) 0 = receive fifo is not occured 1 = receive fifo overrun occured [11] receiver in idle (idle) 0 = receiver is in idle state 1 = receiver is in active state a u b d d n figure 14-3. high-speed uart status register S3C2500B serial i/ o (high-speed uart) 14- 13 [12] receive event time out (e_rxto) 0 = a promised time is not elapsed during receiving. 1 = valid data in a promised time note: a promised time is determined according to wl (word length): promised time = 4*wl + 12) [13] autobaud rate detection done (aubddn) 0 = before autobaud rate detection 1 = after autobaud rate detection [14] data set ready (dsr) 0 = dsr pin goes high 1 = dsr pin goes low [15] clear to send (cts) 0 = cts pin goes high 1 = cts pin goes low [16] cts event occured (e_cts) 0 = cts pin has changed. 1 = cts pin keep it's level [17] transmitter idle (ti) 0 = transmit is in progress. 1 = transmitter is in idle; no data for tx [18] transmit holding register empty (the) 0 = txfifo at trigger level or tranmit holding register is not empty. 1 = in txfifo mode, txfifo at trigger level is empty. in non-fifo mode, transmit holding register is empty. [19] transmit fifo empty (tfemt) 0 = transmit fifo is not empty 1 = transmit fifo is empty [20] transmit fifo full (tfful) 0 = transmit fifo is not full 1 = transmit fifo is full [31:21] reserved c c d o e r t f f u l e _ r x t o t f e m t t h e t i e _ c t s r f f u l r f r e a d c d l i d l e f e r r d v d s r b k d p e r r f e m t r f o v c t s 31 0 3 4 5 1 2 20 19 15 14 10 9 21 18 17 16 13 12 11 8 7 6 a u b d d n figure 14-3. high-speed uart status register (continued) serial i/o (high-speed uart) S3C2500B 14- 14 14.3.3 high-speed uart interrupt enable register table 14-7. hucon interrupt enable registers registers offset address r/w description reset value huint 0xf0070008 0xf0080008 r/w high-speed uart interrupt enable register 0x00 table 14-8. high-speed uart interrupt enable register description bit number bit name description [0] rdvie receive data valid interrupt enable [1] bkdie break signal detected interrupt enable [2] ferie frame error interrupt enable [3] perie parity error interrupt enable [4] oerie overrun error interrupt enable [5] ccdie control character detect interrupt enable [6] dcdlie dcd high at receiver checking time interrupt enable [7] rfreaie receive fifo data trigger level reach interrupt enable [9:8] reserved [10] ovffie receive fifo overrun interrupt enable [11] reserved [12] e_rxtoie receive event time out interrupt enable [13] aubddnie autobaud rate detection done interrupt enable [15:14] reserved [16] e_ctsie cts event occurred interrupt enable [17] tiie transmitter idle interrupt enable [18] theie transmit holding register empty interrupt enable [31:19] reserved S3C2500B serial i/ o (high-speed uart) 14- 15 [0] receive data valid interrupt enable (rdvie) [1] break signal detected interrupt enable (bkdie) [2] frame error interrupt enable (ferie) [3] parity error interrupt enable (perie) [4] overrun error interrupt enable (oerie) [5] control character detect interrupt enable (ccdie) [6] data carrier detect lost interrupt enable (dcdlie) [7] receive fifo data trigger level reach interrupt enable (rfreaie) [9:8] reserved [10] receive fifo overrun interrupt enable (ovffie) [11] reserved [12] receive event time out interrupt enable (e_rxtoie) [13] autobaud rate detection done interrupt enable (aubddnie) [15:14] reserved [16] cts event occured interrupt enable (e_ctsie) [17] transmitter idle (tiie) [18] transmit holding register empty interrupt enable (theie) this bit used in fifo mode for interrupt enable when transmit fifo empty as much transmit data trigger level. [31:19] reserved 31 0 3 4 5 1 2 19 15 10 9 18 17 16 13 12 11 8 7 6 c c d i e o e r i e e _ r x t o i e t h e i e e _ c t s i e r f r e a i e d c d l i e f e r i e r d v i e b k d i e p e r i e o v f f i e t i i e 14 a u b d d n i e figure 14-4. high-speed uart interrupt enable register serial i/o (high-speed uart) S3C2500B 14- 16 14.3.4 high-speed uart transmit buffer register S3C2500B has a 32-byte transmit fifo, and the bottom of fifo is hutxbuf. all data to be transmitted are stored into this register at first in fifo mode, if next buffer has invalid data, then shifted to next buffer. but in non-fifo mode, a new data to transmit will be moved from hutxbuf to tx shift register. the high-speed uart transmit buffer registers, hutxbuf, contain an 8-bit data value to be transmitted over the high-speed uart channel. table 14-9. hutxbuf registers registers offset address r/w description reset value hutxbuf 0xf007000c 0xf008000c w high-speed uart transmit buffer register ? table 14-10. high-speed uart transmit register description bit number bit name description [7:0] transmit data this field contains the data to be transmitted over the single channel high-speed uart. when this register is written, the transmit buffer register empty bit in the status register, hustat[18], should be "1". this is to prevent overwriting of transmit data that may already be present in the hutxbuf. whenever the hutxbuf is written with a new value, the transmit register empty bit, hustat[18], is automatically cleared to "0". 31 [7:0] transmit data for uart transmit data 0 7 8 figure 14-5. high-speed uart transmit buffer register S3C2500B serial i/ o (high-speed uart) 14- 17 14.3.5 high-speed uart receive buffer register S3C2500B has a 32-byte receive fifo, and the bottom of fifo is hurxbuf. all data to be received are stored in this register at first in fifo mode, if next buffer has invalid data, then shifted to next buffer. but in non-fifo mode, a new received data will be moved to hurxbuf. the high-speed uart receive buffer registers, hurxbuf contain an 8-bit data value to be received over the high-speed uart channel. table 14-11. hurxbuf registers registers offset address r/w description reset value hurxbuf 0xf0070010 0xf0080010 r high-speed uart receive buffer register ? table 14-12. high-speed uart receive register description bit number bit name description [7:0] receive data this field contains the data received over the single channel high- speed uart. when the high-speed uart finishes receiving a data frame, the receive data ready bit in the high-speed uart status register, hustat[14], should be "1". this prevents reading invalid receive data that may already be present in the hurxbuf. whenever the hurxbuf is read, the receive data valid bit(hustat[14]) is automatically cleared to "0". 31 [7:0] receive data for uart receive data 0 7 8 figure 14-6. high-speed uart receive buffer register serial i/o (high-speed uart) S3C2500B 14- 18 14.3.6 high-speed uart baud rate divisor register the values stored in the baud rate divisor registers, hubrd let you determine the serial tx/rx clock rate (baud rate) as follows: brgout = pclk2 or ext_uclk (cnt0+1) 16 cnt1 16 table 14-13. hubrd0 and hubrd0 registers registers offset address r/w description reset value hubrd 0xf0070014 0xf0080014 r/w high-speed uart baud rate divisor register 0x00 31 19 15 16 [3:0] baud reate divisor value cnt1 xxx0 = divide by 1 xxx1 = divide by 16 [15:4] time constant value for cnt0 cnt0 0 18 17 20 30 29 28 27 26 25 24 23 22 21 3 4 cnt1 figure 14-7. high-speed uart baud rate divisor register S3C2500B serial i/ o (high-speed uart) 14- 19 14.3.7 high-speed uart baud rate examples high-speed uart brg input clock, pclk2 is the system clock frequency divided by 2. if the system clock frequency is 133 mhz and pclk2 is selected, the maximum brgout output clock rate is pclk2/16 (= 4,156,250 hz). ext_uclk is the external clock input pin for high-speed uart, pclk2, uclk can be selected by hucon[6] register. select clock brgout 12-bit counter divide by 1 or 16 divide by 16 sample clock cnt0 cnt1 note: cnt0 = cubrd[15:4], cnt1 = cubrd[3:0], select clock = hucon[6] pclk2 ext_uclk figure 14-8. high-speed uart baud rate generator (brg) table 14-14. typical baud rates examples of high-speed uart baud rates pclk2 = 66.5 mhz ext_uclk = 29.4912 mhz (brgout) cnt0 (dec/hex) cnt1 freq. dev.(%) cnt0 (dec/hex) cnt1 freq. dev.(%) 1200 3463 /d87 0 1199.84 0.01 1535 /5ff 0 1200.00 0.00 2400 1731 /6c3 0 2399.68 0.01 767 /2ff 0 2400.00 0.00 4800 865 /361 0 4799.36 0.01 383 /17f 0 4800.00 0.00 9600 432 /160 0 9598.73 0.01 191 /bf 0 9600.00 0.00 19200 215 /d7 0 19241.90 0.01 95 /5f 0 19200.00 0.00 38400 107 /6b 0 38483.80 0.22 47 /2f 0 38400.00 0.00 57600 71 /47 0 57725.69 0.22 31 /1f 0 57600.00 0.00 115200 35 /23 0 115451.39 0.22 15 /f 0 115200.00 0.00 230400 17 /11 0 230902.78 0.22 7 /7 0 230400.00 0.00 460800 8 /8 0 461805.56 0.22 3 /3 0 460800.00 0.00 921600 4 /4 0 831250.00 9.80 1 /1 0 921600.00 0.00 serial i/o (high-speed uart) S3C2500B 14- 20 14.3.8 high-speed uart control character 1 register this control character registers can be used for software flow control. in software flow control mode, you should write control characters into this registers. if not, the reset value will be used as control character. for example, even if you want to use one control character, all control characters will have same value with it. table 14-15. huchar1 registers registers offset address r/w description reset value huchar1 0xf0070018 0xf0080018 r/w high-speed uart control character1 register 0x00 31 15 16 [7:0] control character 0 [15:8] control character 1 [23:16] control character 2 [31:24] control character 3 conchar0 0 24 23 7 8 conchar1 conchar3 conchar2 figure 14-9. high-speed uart control character 1 register S3C2500B serial i/ o (high-speed uart) 14- 21 14.3.9 high-speed uart control character 2 register this control character registers can be used for software flow control. in software flow control mode, you should write control characters into this registers. if not, the reset value will be used as control character. for example, even if you want to use one control character, all control characters will have same value with it. table 14-16. huchar2 registers registers offset address r/w description reset value huchar2 0xf007001c 0xf008001c r/w high-speed uart control character2 register 0x00 31 15 16 [7:0] control character 4 [15:8] control character 5 [23:16] control character 6 [31:24] control character 7 conchar4 0 24 23 7 8 conchar5 conchar7 conchar6 figure 14-10. high-speed uart control character 2 register serial i/o (high-speed uart) S3C2500B 14- 22 14.3.10 high-speed uart autoband boundary register this autoband boundary register limit range of each baud rate value that is auto-detected. abb0 is the lowest boundary value (high baud rate) and abb3 is the highest value (low baud rate) of autobaud boundary register (actually the highest boundary value is abt3). refer figure 14-13 for detail range. abt3 abb3 abb1 abt0 abb0 ~ ~ ~ . . . . . abt3 abt0 figure 14-11. autobaud boundary regsiter range table 14-17. huabb registers registers offset address r/w description reset value huabb 0xf0070020 0xf0080020 r/w high-speed uart autobaud boundary register 0x1f0f0703 31 15 16 [7:0] autobaud boundary 0 [15:8] autobaud boundary 1 [23:16] autobaud boundary 2 [31:24] autobaud boundary 3 abb0 0 24 23 7 8 abb1 abb3 abb2 figure 14-12. high-speed uart autobaud boundary register S3C2500B serial i/ o (high-speed uart) 14- 23 14.3.11 high-speed uart autobaud table regsiter this autobaud table register corrects each baud rate divisor value that is auto-detected. for detail refer figure 14- 15. if high-speed uart uses external uclk (29.4912 mhz) and you want to use 460800 baud rate, though high- speed uart detects baud rate divisor register value (cnt0, cnt1) as 0x04, autobaud mechanism will correct baud rate divisor register value as 0x03, because detected value is between 0x05 (abb1) and 0x02 (abb0). abt0 is lowest table value and abt3 is highest table value, also abt3 is highest boundary value of total range. if out of range value is detected, it will be written normally without modification. if 0x1f was detected rewrite: 0x1f if 0x0b was detected if 0x04 was detected rewrite: 0x07 rewrite: 0x03 abt3 0x1f abb3 0x17 abt2 0x0f abb2 0x0b abt1 0x07 abb1 0x05 abt0 0x03 abb0 0x02 figure 14-13. example of autobaud table register setting table 14-18. huabt registers registers offset address r/w description reset value huabt 0xf0070024 0xf0080024 r/w high-speed uart autobaud boundary register 0x170b0502 31 15 16 [7:0] autobaud table 0 [15:8] autobaud table 1 [23:16] autobaud table 2 [31:24] autobaud table 3 abt0 0 24 23 7 8 abt1 abt3 abt2 figure 14-14. high-speed uart autobaud boundary register serial i/o (high-speed uart) S3C2500B 14- 24 14.4 high-speed uart operation data transmit operation flow: if there is no data at tx buffer fifo of high-speed uart (in case of fifo, if data in the tx fifo are empty as same amount of trigger level), high-speed uart generates interrupt or gdma request signal. it depends on high-speed uart mode. cpu(or software) or gdma controller will read data from memory where high-speed uart transmit data are stored, and send them to tx buffer/fifo. transfer unit is byte. when data come from high-speed uart rx pin, data are stored to rx buffer/fifo, via shift register. if valid rx data are received, high-speed uart generates interrupt or gdma request signal. (similar to tx block, in case of fifo, it is same as tx block. data should be stored as the same level of trigger level.) if there is an error on rx data, high-speed uart does not generate gdma request signal but generates interrupt even in case of gdma mode. (although high-speed uart is fifo mode, if error data shift to fifo top, then high-speed uart generates interrupt.) transfer unit is byte, same as at tx block. 14.4.1 fifo operation tx fifo operation: if there is no valid data on trigger level of tx fifo, high-speed uart generates interrupt (int_txd) or sends a request signal to gdma. during this operation trigger level should be 30/32 (empty depth/fifo depth), 24/32, 16/32 or 8/32. cpu or gdma fills data into tx fifo by byte. rx fifo operation: if received data are filled up to rx fifo trigger level, high-speed uart generate interrupt (int_rxd) or send request signal to gdma. the size of transferred data is 1 byte. if rx data contains error in case of gdma mode operation, high-speed uart generates interrupt instead of sending request signal to gdma. then cpu executes interrupt service routine for error data. so gdma transmits (error free) valid data only from received data. 14.4.2 hardware flow control hardware flow control for transmit operation: when cts signal is asserted during transmit operation - high-speed uart transmits tx data to tx line normally. when cts signal is deasserted during transmit operation - if cts signal is deasserted when high-speed uart transmits tx data to tx line, high-speed uart stops data transmission immediately. in this case, transmitting tx data will be lost. hardware flow control for receive operation: in the hardware flow control, during high-speed uart receive data from rx pin, dcd level have to be low. if dcd level goes high, received data will be pull up by high-speed uart rx block from that time. S3C2500B serial i/ o (high-speed uart) 14- 25 start bit data size txd rts cts figure 14-15. when signal is asserted during transmit operation start bit data region txd rts cts stop bit figure 14-16. when cts signal is de-asserted during transmit operation serial i/o (high-speed uart) S3C2500B 14- 26 start bit data region rxd rts cts stop bit figure 14-17. normal received rx data data region rxd pin signal dcd rxd internal signal start bit stop bit start bit figure 14-18. dcd lost during rx data receive 14.4.3 software flow control software can control high-speed uart by control characters. high-speed uart compares received data with control characters, and if they are identical, it sets "1" at state bit (ccd:hustat[5]) and generates interrupt which masked by interrupt enable register. 14.4.4 auto baud rate detection to use auto baud rate detection, set abb(autobaud rate boundary), abt(autobaud rate table) register and auto baud detect bit(aubd:hucon[6]), when rxd level is low, high-speed uart counts low-level of start signal ( ?a? ) and rewrites counting value of low-level by comparing abb, abt register. this automatically corrects baud rate(cnt0 and cnt1) S3C2500B serial i/ o (high-speed uart) 14- 27 serial i/o (high-speed uart) S3C2500B 14- 28 S3C2500B serial i/ o (high-speed uart) 14- 29 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits sio frame figure 14-22. serial i/o frame timing diagram (normal high-speed uart) 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits ir transmit frame bit frame = t 3/16t 7/16t 6/16t figure 14-23. infra-red transmit mode frame timing diagram serial i/o (high-speed uart) S3C2500B 14- 30 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits ir transmit frame bit frame = t 3/16t 13/16t figure 14-24. infra-red receive mode frame timing diagram S3C2500B i/o ports 15- 1 15 i/o ports 15.1 overview S3C2500B has 64 programmable i/o ports. i/o port function control registers (iopcon2: upper word, iopcon1: lower word) select either function's port or gpio. if iopcon1/2 register is set to gpio, iopmode1/2 register should be set to either input mode or output mode. for example, if you select iopcon1/2 for gpio and iopmode1/2 for input, then i/o port can be used for gpio input mode. when the value is latched in iopdata1/2 register, cpu can read iopdata1/2 register value. if you select iopcon1/2 for gpio and iopmode1/2 for output, then cpu can write the data to iopdata1/2 register and the value can be transferred to the output port. i/o ports = pad ports (or pp) function's port gpio input mode output mode if you select iopcon1[14] for xgdma req[0], then the port is used for gdma req port mode. i/o port signal decision register (iopgdma) is used when iopcon1 is selected for gdma req/ ack. iopgdma controls external gdma req/ ack signals. iopextintpnd register is used for external interrupt status. iopextintpnd is set when external interrupt is generated and is cleared when iopextintpnd register is re-written to '1'. 15.2 features 64 programmable i/o ports configurable to input, output, or i/o mode for dedicated signals 6 external interrupt requests 4 external gdma requests 4 external gdma acknowledges 6 timer outputs 22 hdlc signals 14 uart signals note pp[27] - pp[18] ports support external software reset. when pp[27:18] are in gpio output mode and when nreset or system reset (including watchdog reset) is asserted, the external devices that are connected to pp[27:18] are also reset. (that is, the output signals go low, and rise back to high.) i/o ports S3C2500B 15- 2 15.3 i/o port special register table 15-1. i/o port special registers register address r/w description reset value iopmode1 0xf0030000 r/w i/o port mode select register for port 0 to 31 0xf003ffff iopmode2 0xf0030004 r/w i/o port mode select register for port 32 to 63 0xffffffff iopcon1 0xf0030008 r/w i/o port function control register for port 0 to 31 0x0fffff00 iopcon2 0xf003000c r/w i/o port function control register for port 32 to 63 0x00000000 iopgdma 0xf0030010 r/w i/o port special function register for gdma 0x00000000 iopextint 0xf0030014 r/w i/o port special function register for external interrupt 0x00000000 iopextintpnd 0xf0030018 r/w i/o port external interrupt clear register 0x00000000 iopdata1 0xf003001c r/w i/o port data register port 0 to 31 undefined iopdata2 0xf0030020 r/w i/o port data register port 32 to 63 undefined iopdrv1 0xf0030024 r/w i/o port drive control register port 0 to 31 0x00000000 iopdrv2 0xf0030028 r/w i/o port drive control register port 32 to 63 0x00000000 15.3.1 i/o port mode select register (iopmode1/2) if you set iopcon1/2 registers to gpio, then iopmode1/2 registers should determine whether input or output mode for each port. table 15-2. iopmode1/2 registers register address r/w description reset value iopmode1 0xf0030000 r/w i/o port mode select register for port 0 to 31 0xf003ffff iopmode2 0xf0030004 r/w i/o port mode select register for port 31 to 63 0xffffffff S3C2500B i/o ports 15- 3 31 x 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x x x x x x x x x x x x x x x x x iopmode1 x x x x x x x x 31 x 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x x x x x x x x x x x x x x x x x iopmode2 x x x x x x x x signal port bit note: iopmode1/2 registers bit value 1 is input mode, bit value 0 is output mode. iopmode1 reset value gpio[31] gpio[30] gpio[29] gpio[28] gpio[27] gpio[26] gpio[25] gpio[24] gpio[23] gpio[22] gpio[21] gpio[20] gpio[19] gpio[18] gpio[17] gpio[16] gpio[15] gpio[14] gpio[13] gpio[12] gpio[11] gpio[10] gpio[9] gpio[8] gpio[7] gpio[6] gpio[5] gpio[4] gpio[3] gpio[2] gpio[1] gpio[0] 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 gpio[63] gpio[62] gpio[61] gpio[60] gpio[59] gpio[58] gpio[57] gpio[56] gpio[55] gpio[54] gpio[53] gpio[52] gpio[51] gpio[50] gpio[49] gpio[48] gpio[47] gpio[46] gpio[45] gpio[44] gpio[43] gpio[42] gpio[41] gpio[40] gpio[39] gpio[38] gpio[37] gpio[36] gpio[35] gpio[34] gpio[33] gpio[32] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 signal port iopmode2 reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 see note on 15-1 figure 15-1. i/o port mode registers 1/2 (iopmode1/2) i/o ports S3C2500B 15- 4 15.3.2 i/o port function control register (iopcon 1 /2) the i/o port function select registers, iopcon1/2, are used for function select. iopcon1/2 are used to configure external interrupt signals, gdma req/ ack signals, timer signals, uart tx/ rx signals, and hdlc tx/ rx signals. for example, if you set iopcon1[14] to '0', then port14 is used for gdma req port. if you set the iopgdma[14] to ?1?, then port14 is used for gpio. note if the port is used for a function's port such as an external interrupt request or an external gdma req/ ack signal, its signal function is determined by iopgdma or iopextint register. table 15-3. iopcon1/2 register register address r/w description reset value iopcon1 0xf0030008 r/w i/o port function control register for port 0 to 31 0x0fffff00 iopcon2 0xf003000c r/w i/o port function control register for port 32 to 63 0x00000000 S3C2500B i/o ports 15- 5 0 31 multiplexed signals (0 / 1) default signal iopcon1 default value bit 0 30 0 29 0 28 1 27 1 26 1 25 1 24 1 23 1 22 1 21 1 20 1 19 1 18 1 17 1 16 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 reserved 7-0 high speed uart ndsr0 (huartndsr0)/gpio[31] high speed uart ndtr0 (huartndtr0)/gpio[30] high speed uart rtxd0 (huartrtxd0)/gpio[29] high speed uart rxd0 (huartrxd0)/gpio[28] timer output(tout)[5] / gpio[27] timer output(tout)[4] / gpio[26] timer output(tout)[3] / gpio[25] timer output(tout)[2] / gpio[24] timer output(tout)[1] / gpio[23] timer output(tout)[0] / gpio[22] xgdma ack[3] / gpio[21] xgdma ack[2] / gpio[20] xgdma ack[1] / gpio[19] xgdma ack[0] / gpio[18] xgdma req[3] / gpio[17] xgdma req[2] / gpio[16] xgdma req[1] / gpio[15] xgdma req[0] / gpio[14] external interrupt(xint)[5] / gpio[13] external interrupt(xint)[4] / gpio[12] external interrupt(xint)[3] / gpio[11] external interrupt(xint)[2] / gpio[10] external interrupt(xint)[1] / gpio[9] external interrupt(xint)[0] / gpio[8] huartndsr0 huartndtr0 huarttxd0 huartrxd0 gpio[27] gpio[26] gpio[25] gpio[24] gpio[23] gpio[22] gpio[21] gpio[20] gpio[19] gpio[18] gpio[17] gpio[16] gpio[15] gpio[14] gpio[13] gpio[12] gpio[11] gpio[10] gpio[9] gpio[8] 31 x 0 12 13 14 9 10 11 7 8 x x x x x x reserved 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x x x x x x x x x x x x x x x x x iopcon1 see note on 15-1 figure 15-2. i/o function control register 1 (iopcon1) i/o ports S3C2500B 15- 6 iopcon2 default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 multiplexed signals (0 / 1) hdlc ch.2 txc(htxc2) / gpio[63] bit hdlc ch.2 rxc(hrxc2) / gpio[62] hdlc ch.2 ndcd(hndcd2) / gpio[61] hdlc ch.2 ncts(hncts2) / gpio[60] hdlc ch.2 nrts(hnrts2) / gpio[59] hdlc ch.2 ndtr(hndtr2) / gpio[58] hdlc ch.2 rxd(hrxd2) / gpio[57] hdlc ch.2 txd(htxd2) / gpio[56] hdlc ch.1 txc(htxc1) / gpio[55] hdlc ch.1 rxc(hrxc1) / gpio[54] hdlc ch.1 ndcd(hndcd1) / gpio[53] hdlc ch.1 ncts(hncts1) / gpio[52] hdlc ch.1 nrts(hnrts1) / gpio[51] hdlc ch.1 ndtr(hndtr1) / gpio[50] hdlc ch.1 rxd(hrxd1) / gpio[49] hdlc ch.1 txd(htxd1) / gpio[48] hdlc ch.0 txc(htxc0) / gpio[47] hdlc ch.0 rxc(hrxc0) / gpio[46] hdlc ch.0 ndcd(hndcd0) / gpio[45] hdlc ch.0 ncts(hncts0) / gpio[44] hdlc ch.0 nrts(hnrts0) / gpio[43] hdlc ch.0 ndtr(hndtr0) / gpio[42] high speed uart ndcd1(huartndcd1)/gpio[41] high speed uart ncts1(huartncts1)/gpio[40] high speed uart nrts1(huartnrts1)/gpio[39] high speed uart ndsr1(huartndsr1)/gpio[38] high speed uart ndtr1(huartndtr1)/gpio[37] high speed uart txd1(huarttxd1)/gpio[36] high speed uart rxd1(huartrxd1)/gpio[35] high speed uart ndcd0(huartndcd0)/gpio[34] high speed uart ncts0(huartncts0)/gpio[33] high speed uart nrts0(huartnrts0)/gpio[32] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 x 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x x x x x x x x x x x x x x x x x iopcon2 x x x x x x x x htxc2 default signal hrxc2 hndcd2 hncts2 hnrts2 hndtr2 hrxd2 htxd2 htxc1 hrxc1 hndcd1 hncts1 hnrts1 hndtr1 hrxd1 htxd1 htxc0 hrxc0 hndcd0 hncts0 hnrts0 hndtr0 huartndcd1 huartncts1 huartnrts1 huartndsr1 huartndtr1 huarttxd1 huartrxd1 huartndcd0 huartncts0 huartnrts0 figure 15-3. i/o function control register 2 (iopcon2) S3C2500B i/o ports 15- 7 15.3.3 i/o port control register for gdma (iopgdma) if the port is used for a function's port such as an external gdma req/ ack signal, its signal function is determined by the iopgdma register. iopgdma register is used to configure gdma req/ ack signal. i/o ports provide 3-tap filtering, and you can select filtering on or off. external signals can be active high or low, so you must set the active high or low bits for the proper operation. table 15-4. iopgdma register register address r/w description reset value iopgdma 0xf0030010 r/w i/o port special function register for gdma 0x00000000 [11] control external gdma acknowledge3 output for port 21(xgdma_ack3) [11] 0 = active low 1 = active high [10] control external gdma acknowledge2 output for port 20 (xgdma_ack2) [10] 0 = active low 1 = active high [9] control external gdma acknowledge1 output for port 19(xgdma_ack1) [9] 0 = active low 1 = active high [8] control external gdma acknowledge0 output for port 18 (xgdma_ack0) [8] 0 = active low 1 = active high [7:6] control external gdma request3 input for port 17 (xgdma_req3) [7] 0 = filtering off 1 = filtering on [6] 0 = active low 1 = active high [5:4] control external gdma request2 input for port 16 (xgdma_req2) [5] 0 = filtering off 1 = filtering on [4] 0 = active low 1 = active high [3:2] control external gdma request1 input for port 15 (xgdma_req1) [3] 0 = filtering off 1 = filtering on [2] 0 = active low 1 = active high [1:0] control external gdma request0 input for port 14 (xgdma_req0) [1] 0 = filtering off 1 = filtering on [0] 0 = active low 1 = active high 31 0 12 9 10 11 6 7 8 3 4 5 1 2 x x x x x x iopgdma x x x x x x reserved figure 15-4. i/o port control register for gdma (iopgdma) i/o ports S3C2500B 15- 8 15.3.4 i/o port control register for external interrupt (iopextint) if the port is used for a function's port such as an external interrupt request, its signal function is determined by the iopextint register. iopextint register is used to configure external interrupt request signals. i/o ports provide 3-tap filtering, and you can select filtering on or off. external interrupt provides level or rising or falling edge detection. if you set rising or falling edge detection, rising or falling edge interrupt makes interrupt status high. you can clear the interrupt by writing iopextintpnd register to '1'. if you set level detection, then external interrupt level goes direct to interrupt controller. external signals can be active high or low, so you must set the active high or low bits for the proper operation. table 15-5. iopextint register register address r/w description reset value iopextint 0xf0030014 r/w i/o port special function register for external interrupt 0x00000000 S3C2500B i/o ports 15- 9 [23:20] control external interrupt request5 input for port 13 (xint5) [23] 0 = active low 1 = active high [22] 0 = filtering off 1 = filtering on [21:20] 00 = level detection 01 = rising edge detection 10 = falling edge detection [19:16] control external interrupt request4 input for port 12 (xint4) [19] 0 = active low 1 = active high [18] 0 = filtering off 1 = filtering on [17:16] 00 = level detection 01 = rising edge detection 10 = falling edge detection [15:12] control external interrupt request3 input for port 11 (xint3) [15] 0 = active low 1 = active high [14] 0 = filtering off 1 = filtering on [13:12] 00 = level detection 01 = rising edge detection 10 = falling edge detection [11:8] control external interrupt request2 input for port 10 (xint2) [11] 0 = active low 1 = active high [10] 0 = filtering off 1 = filtering on [9:8] 00 = level detection 01 = rising edge detection 10 = falling edge detection [7:4] control external interrupt request1 input for port 9 (xint1) [7] 0 = active low 1 = active high [6] 0 = filtering off 1 = filtering on [5:4] 00 = level detection 01 = rising edge detection 10 = falling edge detection [3:0] control external interrupt request0 input for port 8 (xint0) [3] 0 = active low 1 = active high [2] 0 = filtering off 1 = filtering on [1:0] 00 = level detection 01 = rising edge detection 10 = falling edge detection 31 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x iopextint 15 16 17 18 19 20 21 22 23 24 x x x x x x x x x x x x x x x x x x reserved figure 15-5. i/o port control register for external interrupt (iopextint) i/o ports S3C2500B 15- 10 15.3.5 i/o port external interrupt clear register (iopextintpnd) external interrupt clear register (iopextintpnd) is set when external interrupt is generated, and you can clear the interrupt status by writing the iopextintpnd status register to '1'. table 15-6. iopextintpnd register register address r/w description reset value iopextintpnd 0xf0030018 r/w i/o port external interrupt clear register 0x00000000 note: iopextintpnd is set when external interrupt is generated and is cleared by writing '1' to the appropriate bit of iopextintpnd register. [5] extintclr5 [4] extintclr4 [3] extintclr3 [2] extintclr2 [1] extintclr1 [0] extintclr0 31 0 6 3 4 5 1 2 x x x x x x iopextintpnd reserved figure 15-6. i/o port external interrupt clear register (iopextintpnd) S3C2500B i/o ports 15- 11 15.3.6 i/o port data register (iopdata1/2) the i/o port data registers, iopdata1/2, contain one-bit read values for i/o ports that are configured to input mode and one-bit write values for ports that are configured to output mode. table 15-7. iopdata1/2 register register address r/w description reset value iopdata1 0xf003001c r/w i/o port data register for port 0 to 31 undefined iopdata2 0xf0030020 r/w i/o port data register for port 32 to 63 undefined 15.3.7 i/o port drive control register (iopdrv1/2) the i/o port drive control registers, iopdrv1/2, control the pad type for which is operating as a tri-state output mode or an open-drain output mode. this register's each bit value programmed as write '1' value for open-drain output mode or write ?0? value for tri-state output mode. table 15-8. iopdrv1/2 register register address r/w description reset value iopdrv1 0xf0030024 r/w i/o port drive control register for port 0 to 31 0x00000000 iopdrv2 0xf0030028 r/w i/o port drive control register for port 32 to 63 0x00000000 i/o ports S3C2500B 15- 12 notes S3C2500B interrupt controller 1 6 - 1 16 interrupt controller 16.1 overview the S3C2500B interrupt controller has a total of 39 interrupt sources. interrupt requests can be generated by internal function blocks or external pins. the arm940t core recognizes two kinds of interrupts: a normal interrupt request (irq) and a fast interrupt request (fiq). therefore all S3C2500B interrupts can be categorized as either irq or fiq. the S3C2500B interrupt controller is level sensitive to each interrupt source. three special registers are used to control interrupt generation and handling: ? interrupt priority registers (intpriorn): the index number of each interrupt source is written to the pre- defined interrupt priority register field to obtain that priority. the interrupt priorities are pre-defined from 0x0 to 0x26. ? interrupt mode register (intmod, extmod): defines the interrupt mode, irq or fiq, for each interrupt source. ? interrupt mask register (intmask, extmask): indicates that the current interrupt has been disabled if the corresponding mask bit is "1". if an interrupt mask bit is "0" the interrupt will be serviced normally. if the global mask bit (bit 31) of extmask register is set to "1", no interrupt is serviced. when the global mask bit has been set to "0", the interrupt is serviced. 16.2 features supports irq and fiq interrupt request level sensitive interrupt sources supports 33 internal interrupt sources supports 6 external interrupt sources supports interrupt sources programmable to different priorities supports global interrupt masking interrupt controller S3C2500B 16- 2 16.3 interrupt sources the 39 interrupt sources in the S3C2500B interrupt structure are listed, in brief, as follows: table 16-1. S3C2500B internal interrupt sources index values interrupt sources [31] watchdog timer interrupt [30] 32-bit timer 5 interrupt [29] 32-bit timer 4 interrupt [28] 32-bit timer 3 interrupt [27] 32-bit timer 2 interrupt [26] 32-bit timer 1 interrupt [25] 32-bit timer 0 interrupt [24] gdma channel 5 interrupt [23] gdma channel 4 interrupt [22] gdma channel 3 interrupt [21] gdma channel 2 interrupt [20] gdma channel 1 interrupt [19] gdma channel 0 interrupt [18] des interrupt [17] ethernet 1 rx interrupt [16] ethernet 1 tx interrupt [15] ethernet 0 rx interrupt [14] ethernet 0 tx interrupt [13] hdlc 2 rx interrupt [12] hdlc 2 tx interrupt [11] hdlc 1 rx interrupt [10] hdlc 1 tx interrupt [9] hdlc 0 rx interrupt [8] hdlc 0 tx interrupt [7] usb interrupt [6] cuart rx interrupt [5] cuart tx interrupt [4] huart 1 rx interrupt [3] huart 1 tx interrupt [2] huart 0 rx interrupt [1] huart 0 tx interrupt [0] iic interrupt S3C2500B interrupt controller 1 6 - 3 table 16-2. S3C2500B external interrupt sources index values interrupt sources [6] iom2 interrupt [5] external interrupt 5 [4] external interrupt 4 [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 16.4 interrupt controller special registers 16.4.1 interrupt mode registers bit settings in the interrupt mode registers, intmod and extmod, specify if an interrupt is to be serviced as a fast interrupt (fiq) or a normal interrupt (irq). table 16-3. intmod, extmod register register address r/w description reset value intmod 0xf0140000 r/w internal interrupt mode register 0x00000000 extmod 0xf0140004 r/w external interrupt mode register 0x00000000 interrupt controller S3C2500B 16- 4 [31:0] internal interrupt mode bits note : each of the 32 bits in the interrupt mode enable register, intmod, corresponds to an interrupt source. when the source interrupt mode bit is set to 1, the interrupt is processed by the arm940t core in fiq (fast interrupt) mode. otherwise, it is processed in irq mode (normal interrupt). the 32 interrupt sources are mapped as follows: [31] watchdog timer interrupt (0 = irq interrupt mode, 1 = fiq interrupt mode) [30] 32-bit timer 5 interrupt [29] 32-bit timer 4 interrupt [28] 32-bit timer 3 interrupt [27] 32-bit timer 2 interrupt [26] 32-bit timer 1 interrupt [25] 32-bit timer 0 interrupt [24] gdma channel 5 interrupt [23] gdma channel 4 interrupt [22] gdma channel 3 interrupt [21] gdma channel 2 interrupt [20] gdma channel 1 interrupt [19] gdma channel 0 interrupt [18] des interrupt [17] ethernet 1 rx interrupt [16] ethernet 1 tx interrupt [15] ethernet 0 rx interrupt [14] ethernet 0 tx interrupt [13] hdlc 2 rx interrupt [12] hdlc 2 tx interrupt [11] hdlc 1 rx interrupt [10] hdlc 1 tx interrupt [9] hdlc 0 rx interrupt [8] hdlc 0 tx interrupt [7] usb interrupt [6] cuart rx interrupt [5] cuart tx interrupt [4] huart 1 rx interrupt [3] huart 1 tx interrupt [2] huart 0 rx interrupt [1] huart 0 tx interrupt [0] iic interrupt 31 x 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x x x x x x x x x intmod 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x x x x x x x x x x x x x x x x x figure 16-1. internal interrupt mode register (intmod) S3C2500B interrupt controller 1 6 - 5 [6:0] external interrupt mode bits note : each of the 7 bits in the external interrupt mode enable register, extmod, corresponds to an external interrupt source. when the source interrupt mode bit is set to 1, the interrupt is processed by the arm940t core in fiq (fast interrupt) mode. otherwise, it is processed in irq mode (normal interrupt). the 7 external interrupt sources are mapped as follows: [6] iom2 interrupt (0 = irq interrupt mode, 1 = fiq interrupt mode ) [5] ext 5 interrupt [4] ext 4 interrupt [3] ext 3 interrupt [2] ext 2 interrupt [1] ext 1 interrupt [0] ext 0 interrupt 31 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x extmod 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x figure 16-2. external interrupt mode register (extmod) 16.4.2 interrupt mask registers the interrupt mask registers, intmask and extmask, contain interrupt mask bits for each interrupt source. table 16-4. intmask, extmask register register address r/w description reset value intmask 0xf0140008 r/w internal interrupt mask register 0xffffffff extmask 0xf014000c r/w external interrupt mask register 0x8000007f interrupt controller S3C2500B 16- 6 [31:0] individual internal interrupt mask bits note: each of the 32 bits in the interrupt mask register, intmask, corresponds to an interrupt source. when a source interrupt mask bit is 1, the interrupt is not serviced by the arm940t when the corresponding interrupt request is generated. if the mask bit is 0, the interrupt is serviced upon request. the 32 interrupt sources are mapped as follows: [31] watchdog timer interrupt (0 = non-masking, 1 = masking) [30] 32-bit timer 5 interrupt [29] 32-bit timer 4 interrupt [28] 32-bit timer 3 interrupt [27] 32-bit timer 2 interrupt [26] 32-bit timer 1 interrupt [25] 32-bit timer 0 interrupt [24] gdma channel 5 interrupt [23] gdma channel 4 interrupt [22] gdma channel 3 interrupt [21] gdma channel 2 interrupt [20] gdma channel 1 interrupt [19] gdma channel 0 interrupt [18] des interrupt [17] ethernet 1 rx interrupt [16] ethernet 1 tx interrupt [15] ethernet 0 rx interrupt [14] ethernet 0 tx interrupt [13] hdlc 2 rx interrupt [12] hdlc 2 tx interrupt [11] hdlc 1 rx interrupt [10] hdlc 1 tx interrupt [9] hdlc 0 rx interrupt [8] hdlc 0 tx interrupt [7] usb interrupt [6] cuart rx interrupt [5] cuart tx interrupt [4] huart 1 rx interrupt [3] huart 1 tx interrupt [2] huart 0 rx interrupt [1] huart 0 tx interrupt [0] iic interrupt intmask 31 x 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x x x x x x x x x 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x x x x x x x x x x x x x x x x x figure 16-3. internal interrupt mask register (intmask) S3C2500B interrupt controller 1 6 - 7 [6:0] individual external interrupt mask bits note: each of the 7 bits in the external interrupt mask register, extmask, (except for the global mask bit, g) corresponds to an external interrupt source. when a source interrupt mask bit is 1, the interrupt is not serviced by the arm940t when the corresponding interrupt request is generated. if the mask bit is 0, the interrupt is serviced upon request. and if global mask bit (bit 31) is 1, no interrupts (include internal and external interrupts) are serviced. after the global mask bit is cleared, the interrupt is serviced. the 7 interrupt sources are mapped as follows: [6] iom2 interrupt (0 = non-masking, 1 = masking) [5] ext 5 interrupt [4] ext 4 interrupt [3] ext 3 interrupt [2] ext 2 interrupt [1] ext 1 interrupt [0] ext 0 interrupt [31] global interrupt mask bit 0 = enable all interrupt requests 1 = disable all interrupt requests extmask 31 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 g x figure 16-4. external interrupt mask register (extmask) interrupt controller S3C2500B 16- 8 16.4.3 interrupt priority registers the interrupt priority registers, intprior0?intprior9, contain information about which interrupt source is assigned to the pre-defined interrupt priority field. each intpriorn register value determines the priority of the corresponding interrupt source. the lowest priority value is 0x0, and the highest priority value is 0x26. the index value of each interrupt source is written to one of the above 39 positions (see figure 16-5). the position value then becomes the written interrupt's priority value. the index value of each interrupt source is listed in table 16-7. table 16-5. interrupt priority register register address r/w description reset value intprior0 0xf0140020 r/w interrupt priority register 0 0x03020100 intprior1 0xf0140024 r/w interrupt priority register 1 0x07060504 intprior2 0xf0140028 r/w interrupt priority register 2 0x0b0a0908 intprior3 0xf014002c r/w interrupt priority register 3 0x0f0e0d0c intprior4 0xf0140030 r/w interrupt priority register 4 0x13121110 intprior5 0xf0140034 r/w interrupt priority register 5 0x17161514 intprior6 0xf0140038 r/w interrupt priority register 6 0x1b1a1918 intprior7 0xf014003c r/w interrupt priority register 7 0x1f1e1d1c intprior8 0xf0140040 r/w interrupt priority register 8 0x23222120 intprior9 0xf0140044 r/w interrupt priority register 9 0x00262524 intprior0 30 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 20 21 22 23 24 28 29 31 intprior1 intprior2 high priority low priority low priority high priority intprior3 intprior4 intprior5 intprior6 intprior7 intprior8 intprior9 0 0 0 0 0 0 priority1 priority5 priority9 priority13 priority17 priority21 priority25 priority29 priority33 priority37 priority0 priority4 priority8 priority12 priority16 priority20 priority24 priority28 priority32 priority36 priority3 priority7 priority11 priority15 priority19 priority23 priority27 priority31 priority35 priority2 priority6 priority10 priority14 priority18 priority22 priority26 priority30 priority34 priority38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 26 25 figure 16-5. interrupt priority register (intpriorn) S3C2500B interrupt controller 1 6 - 9 16.4.4 interrupt offset register the interrupt offset registers, intoffset_fiq and intoffset_irq, contain the interrupt offset address of the interrupt, which has the highest priority among the pending interrupts. the content of the interrupt offset address is "index value of the interrupt source?. if all interrupt pending bits are "0" when you read this register, the return value is "0x00000027". this register is valid only under the irq or fiq mode in the arm940t. in the interrupt service routine, you should read this register before changing the cpu mode. note if the lowest interrupt priority (priority 0) is pending, the intoffset value will be "0x00000000". the reset value will, therefore, be changed to "0x00000027" (to be different from interrupt pending priority 0). table 16-6. intoffset_fiq, intoffset_irq register register address r/w description reset value intoffset_fiq 0xf0140018 r fiq interrupt offset register 0x00000027 intoffset_irq 0xf014001c r irq interrupt offset register 0x00000027 interrupt controller S3C2500B 16- 10 table 16-7. index value of interrupt sources index value type of interrupt sources returned default offset value (hex) [38] watchdog timer interrupt 0 x 26 [37] 32-bit timer 5 interrupt 0 x 25 [36] 32-bit timer 4 interrupt 0 x 24 [35] 32-bit timer 3 interrupt 0 x 23 [34] 32-bit timer 2 interrupt 0 x 22 [33] 32-bit timer 1 interrupt 0 x 21 [32] 32-bit timer 0 interrupt 0 x 20 [31] gdma channel 5 interrupt 0 x 1f [30] gdma channel 4 interrupt 0 x 1e [29] gdma channel 3 interrupt 0 x 1d [28] gdma channel 2 interrupt 0 x 1c [27] gdma channel 1 interrupt 0 x 1b [26] gdma channel 0 interrupt 0 x 1a [25] des interrupt 0 x 19 [24] ethernet 1 rx interrupt 0 x 18 [23] ethernet 1 tx interrupt 0 x 17 [22] ethernet 0 rx interrupt 0 x 16 [21] ethernet 0 tx interrupt 0 x 15 [20] hdlc 2 rx interrupt 0 x 14 [19] hdlc 2 tx interrupt 0 x 13 [18] hdlc 1 rx interrupt 0 x 12 [17] hdlc 1 tx interrupt 0 x 11 [16] hdlc 0 rx interrupt 0 x 10 [15] hdlc 0 tx interrupt 0 x f [14] usb interrupt 0 x e [13] cuart rx interrupt 0 x d [12] cuart tx interrupt 0 x c [11] huart 1 rx interrupt 0 x b [10] huart 1 tx interrupt 0 x a S3C2500B interrupt controller 1 6 - 11 table 16-7. index value of interrupt sources (continued) index value type of interrupt sources returned default offset value (hex) [9] huart 0 rx interrupt 0 x 9 [8] huart 0 tx interrupt 0 x 8 [7] iic interrupt 0 x 7 [6] iom2 interrupt 0 x 6 [5] external interrupt 5 0 x 5 [4] external interrupt 4 0 x 4 [3] external interrupt 3 0 x 3 [2] external interrupt 2 0 x 2 [1] external interrupt 1 0 x 1 [0] external interrupt 0 0 x 0 interrupt controller S3C2500B 16- 12 16.4.5 interrupt by priority register the interrupt by priority registers, ipriorhi and ipriorlo, contain interrupt pending bits, which are re-ordered by the intpriorn register settings. ipriorlo[14] is mapped to the interrupt source of whichever bit index is written into the priority 14 field of the intpriorn registers. this register is useful for testing. to validate the interrupt pending by priority value, you can obtain the highest priority pending interrupt from the interrupt offset register, intoffset. table 16-8. ipriorhi, ipriorlo register register address r/w description reset value ipriorhi 0xf0140010 r high bits, 38-32 bit, interrupt by priority register 0x00000000 ipriorlo 0xf0140014 r low bits, 31-0 bit, interrupt by priority register 0x00000000 16.4.6 interrupt test register the interrupt test registers, inttsthi and inttstlo, are used to monitor a interrupt pending status. the interrupt pending test registers, inttsthi and inttstlo, are also useful for testing. table 16-9. inttsthi, inttstlo register register address r/w description reset value inttsthi 0xf0140048 r high bits, 38-7 bit, interrupt test register 0x00000000 inttstlo 0xf014004c r low bits, 6-0 bit, interrupt test register 0x00000000 S3C2500B 32-bit timers 17- 1 17 32-bit timers 17.1 overview the timer has six 32-bit timers and one watchdog timer. six 32-bit timers have timer mode register (tmod) which is used to control the operation of the six 32-bit timers, timer data registers (tdatan) which are data registers for counting, timer counts registers (tcntn) which are count value registers, and timer interrupt clear register (tic) which is used to clear the current interrupt. these timers can operate in interval mode or in toggle mode. the output signals are toutn. the user can enable or disable timers by setting control bits in timer mode register (tmod). an interrupt request is generated whenever a timer count-out (down count) occurs. watchdog timer (wdt) has watchdog timer register (wdt), which has control bits and data value. 17.2 feature 6 programmable timers interval mode or toggle mode operation hardware watchdog timer 32-bit timers S3C2500B 17- 2 17.3 interval mode operation in interval mode, a timer generates one-shot pulse of preset timer clock duration whenever a time-out occurs. this pulse generates a time-out interrupt that is directly output at the timer's configured output pin (toutn). in this case, the timer frequency monitored at the toutn pin is calculated as: f tout = f sysclk / timer data value , where f sysclk is the system bus clock frequency. 17.4 toggle mode operation in toggle mode, the timer pulse continues to toggle whenever a time-out occurs. an interrupt request is generated whenever the level of the timer output signal is inverted (that is, when the level toggles). the toggle pulse is output directly at the configured output pin. using toggle mode, you can achieve a flexible timer clock range with 50% duty. in toggle mode, the timer frequency monitored at the toutn pin is calculated as follows: f tout = f sysclk / (2 timer data value) f tout f tout time-out time-out time-out interval mode toggle mode (initial toutn is 0) time-out time-out time-out figure 17-1. timer output signal timing S3C2500B 32-bit timers 17- 3 17.5 timer operation guidelines the block diagram in figure 17-2 shows how the 32-bit timers are configured in the S3C2500B. the following guidelines apply to the timer functions. when a timer is enabled, it loads a data value (tdata) to its count register (tcnt) and begins decrement of the count register value (tcnt). when the count register (tcnt) reaches to zero, the associated interrupt is generated. the base value (tdata) is then reloaded to the count register (tcnt), and the timer continues decrement of its count register value (tcnt). if a timer is disabled, you can write a new base value into its registers (tdata). if the timer is halted while it is running, the base value is not automatically re-loaded. f sysclk 32-bit timer count register (tcntn) [down counter] 32-bit timer data register (tdatan) pulse generator tmod.ten tmod.tmdn tmod.tclrn tic intmask interrupt request port 22 - 27 data out iopcon1 auto re-load toutn figure 17-2. 32-bit timer block diagram 32-bit timers S3C2500B 17- 4 17.6 timer special register 17.6.1 timer mode register the timer mode register, tmod, is used to control the operation of the six 32-bit timers. tmod register settings are described in figure 17-3. table 17-1. tmod register register address r/w description reset value tmod 0xf0040000 r/w timer mode register 0x00000000 S3C2500B 32-bit timers 17- 5 [0] timer 0 enable (te0) 0 = disable timer 0 1 = enable timer 0 [1] timer 0 mode selection (tmd0) 0 = interval mode 1 = toggle mode [2] timer 0 initial tout0 value (tclr0) 0 = initial tout0 is 0 in toggle mode 1 = initial tout0 is 1 in toggle mode [3] timer 1 enable (te1) 0 = disable timer 1 1 = enable timer 1 [4] timer 1 mode selection (tmd1) 0 = interval mode 1 = toggle mode [5] timer 1 initial tout1 value (tclr1) 0 = initial tout1 is 0 in toggle mode 1 = initial tout1 is 1 in toggle mode [6] timer 2 enable (te2) 0 = disable timer 2 1 = enable timer 2 [7] timer 2 mode selection (tmd2) 0 = interval mode 1 = toggle mode [8] timer 2 initial tout2 value (tclr2) 0 = initial tout2 is 0 in toggle mode 1 = initial tout2 is 1 in toggle mode 31 0 6 3 4 5 1 2 t m d 0 t e 1 t e 0 t m d 1 t c l r 1 t c l r 0 t e 2 t m d 2 t c l r 2 t e 3 t m d 3 t c l r 3 t e 4 t m d 4 t c l r 4 t e 5 t m d 5 t c l r 5 7 13 10 11 12 8 9 17 14 15 16 [9] timer 3 enable (te3) 0 = disable timer 3 1 = enable timer 3 [10] timer 3 mode selection (tmd3) 0 = interval mode 1 = toggle mode [11] timer 3 initial tout3 value (tclr3) 0 = initial tout3 is 0 in toggle mode 1 = initial tout3 is 1 in toggle mode [12] timer 4 enable (te4) 0 = disable timer 4 1 = enable timer 4 [13] timer 4 mode selection (tmd4) 0 = interval mode 1 = toggle mode [14] timer 4 initial tout4 value (tclr4) 0 = initial tout4 is 0 in toggle mode 1 = initial tout4 is 1 in toggle mode [15] timer 5 enable (te5) 0 = disable timer 5 1 = enable timer 5 [16] timer 5 mode selection (tmd5) 0 = interval mode 1 = toggle mode [17] timer 5 initial tout5 value (tclr5) 0 = initial tout5 is 0 in toggle mode 1 = initial tout5 is 1 in toggle mode 18 figure 17-3. timer mode register (tmod) 32-bit timers S3C2500B 17- 6 17.6.2 timer data registers the timer data registers, tdata0 - tdata5, contain a value that specifies the time-out duration for each timer. the formula for calculating the time-out duration is: (timer data) cycles. the timer is dependent on the system bus clock. when the system bus is 133 mhz, the minimum value, 0x1 for tdata, generates interrupt at every 7.5n sec. it takes about 32.2 sec for tdata to go from 0x0 to 0xffffffff. although tout signal is designed to come out whenever time-out occurs, it is possible for tout signal not to work properly for some tdata values when interrupt is enabled. the reason is that arm940t spends the specific time to reach interrupt service routine after time-out takes place. the elapsed time from time-out to interrupt service routine is approximately 27 cycles (200n sec, at 133 mhz). therefore, tdata should be set to the bigger value than ?0x1a?, to avoid another time-out, while it is carrying out the process between time-out and interrupt routine. table 17-2. tdata0 - tdata5 registers register address r/w description reset value tdata0 0xf0040010 r/w timer 0 data register 0x00000000 tdata1 0xf0040018 r/w timer 1 data register 0x00000000 tdata2 0xf0040020 r/w timer 2 data register 0x00000000 tdata3 0xf0040028 r/w timer 3 data register 0x00000000 tdata4 0xf0040030 r/w timer 4 data register 0x00000000 tdata5 0xf0040038 r/w timer 5 data register 0x00000000 31 0 timer data [31:0] timer 0-5 data value figure 17-4. timer data registers (tdata0 - tdata5) S3C2500B 32-bit timers 17- 7 17.6.3 timer count registers the timer count registers, tcnt0 - tcnt5, contain the current timer 0 - 5 count value, respectively, during the normal operation. table 17-3. tcnt0 - tcnt5 registers register address r/w description reset value tcnt0 0xf0040014 r/w timer 0 count register 0xffffffff tcnt1 0xf004001c r/w timer 1 count register 0xffffffff tcnt2 0xf0040024 r/w timer 2 count register 0xffffffff tcnt3 0xf004002c r/w timer 3 count register 0xffffffff tcnt4 0xf0040034 r/w timer 4 count register 0xffffffff tcnt5 0xf004003c r/w timer 5 count register 0xffffffff 31 0 timer count [31:0] timer 0-5 count value figure 17-5. timer count registers (tcnt0 - tcnt5) 32-bit timers S3C2500B 17- 8 17.6.4 timer interrupt clear registers timer interrupt clear register (tic) clears the current interrupt of the six 32-bit timers and one watchdog timer. table 17-4. timer interrupt clear registers register address r/w description reset value tic 0xf0040004 r/w timer interrupt clear 0x00000000 [0] wdt interrupt clear (wdtic) 0 = no interrupt clear 1 = interrupt clear [1] timer0 interrupt clear (tic0) 0 = no interrupt clear 1 = interrupt clear [2] timer1 interrupt clear (tic1) 0 = no interrupt clear 1 = interrupt clear [3] timer2 interrupt clear (tic2) 0 = no interrupt clear 1 = interrupt clear [4] timer3 interrupt clear (tic3) 0: no interrupt clear 1: interrupt clear [5] timer4 interrupt clear (tic4) 0 = no interrupt clear 1 = interrupt clear [6] timer5 interrupt clear (tic5) 0 = no interrupt clear 1 = interrupt clear tic 31 0 6 3 4 5 1 2 t i c 0 7 w d t i c t i c 1 t i c 2 t i c 3 t i c 4 t i c 5 figure 17-6. timer interrupt clear register S3C2500B 32-bit timers 17- 9 17.6.5 watchdog timer register (wdt) to use watchdog timer, watchdog timer register (wdt) must be set. if wdt[29] (rst) is ?1? when wdt[31] (en) was asserted, the timeout counter in watchdog timer is cleared as ?0?. following this cycle, wdt[29] (rst) is automatically de-asserted. watchdog timer timeout value (wdtval) can be set as shown in table 17-6. if the user set two or more bits of wdtval, the lowest significant bit of those let the watch dog timer time out. table 17-5. wdt register register address r/w description reset value wdt 0xf0040008 r/w watchdog timer register 0x00000000 watchdog timer timeout value (wdtval) [17:0] watchdog timer timeout value (wdtval) [29] watchdog timer counter reset (rst) when set to '1', watchdog timer counter is reset. [30] watchdog timer mode (mode) 0 = interrupt mode 1 = reset mode [31] watchdog timer enable (en) 0 = disable 1 = enable 31 m o d e 30 29 28 18 17 0 r s t e n figure 17-7. watchdog timer register (wdt) 32-bit timers S3C2500B 17- 10 table 17-6. watchdog timer timeout value (wdtval, x: don't care) (when watchdog timer operates at 133 mhz) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 count (n x 7.5ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 no operation x x x x x x x x x x x x x x x x x 1 2 09 (3.8us) x x x x x x x x x x x x x x x x 1 0 2 12 (30.7us) x x x x x x x x x x x x x x x 1 0 0 2 15 (245.8us) x x x x x x x x x x x x x x 1 0 0 0 2 16 (491.5us) x x x x x x x x x x x x x 1 0 0 0 0 2 17 (983.0us) x x x x x x x x x x x x 1 0 0 0 0 0 2 18 (1.97ms) x x x x x x x x x x x 1 0 0 0 0 0 0 2 19 (3.93ms) x x x x x x x x x x 1 0 0 0 0 0 0 0 2 20 (7.86ms) x x x x x x x x x 1 0 0 0 0 0 0 0 0 2 21 (15.72ms) x x x x x x x x 1 0 0 0 0 0 0 0 0 0 2 22 (31.45ms) x x x x x x x 1 0 0 0 0 0 0 0 0 0 0 2 23 (62.91ms) x x x x x x 1 0 0 0 0 0 0 0 0 0 0 0 2 24 (125.82ms) x x x x x 1 0 0 0 0 0 0 0 0 0 0 0 0 2 25 (251.65ms) x x x x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2 26 (503.31ms) x x x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 27 (1.00s) x x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 28 (2.01s) x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 29 (4.02s) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 30 (8.05s) S3C2500B electrical data 18- 1 18 electrical data 18.1 overview this chapter describes the S3C2500B electrical data. 18.2 absolute maximum ratings table 18-1. absolute maximum ratings symbol parameter rating unit v dd dc supply voltage 1.8v v dd 2.7 v 3.3v v dd 3.8 v in dc input voltage 3.3v input buffer 3.8 v out dc output voltage 3.3v input buffer 3.8 i latch latch-up current 200 ma t stg storage termperature - 65 to 150 c 18.3 recommended operating conditions table 18-2. recommended operating conditions symbol parameter rating unit v dd dc supply voltage 1.8v core 1.8 5% v 3.3v i/o 3.3 5% pll dc supply voltage 1.8v core 1.8 5% v in dc input voltage 3.3v input buffer 3.0 - 3.6 v out dc output voltage 3.3v output buffer 3.0 - 3.6 t a commercial temperature range ?40 to 85 c electrical data s3c 2500b 18- 2 18.4 dc electrical specifications table 18-3. d.c electric characteristics v dd = 3.3 v 5%, t a = -40 to 85 c symbol parameter condition min type max unit v ih high level input voltage v lvcmos interface 2.0 ? ? v il low level input voltage v lvcmos interface ? ? 0.8 vt switching threshold ? 1.4 v vt + schmitt trigger, positive-going threshold cmos ? ? 2.0 v vt _ schmitt trigger, negative- going threshold cmos 0.8 ? ? v i ih high level input current m a input buffer v in = v dd -10 ? 10 input buffer with pull- down 10 33 60 i il low level input current m a input buffer v in = v ss -10 ? 10 input buffer with pull-up -60 -33 -10 v oh high level output voltage v type b1 to b12 i oh = -1 m a v dd -0.05 ? ? type b1 i oh = -1 ma 2.4 type b2 i oh = -2 ma type b4 i oh = -4 ma type b8 i oh = -8 ma type b12 i oh = -12 ma type b12 i oh = -12 ma type b16 i oh = -16 ma type b20 i oh = -20 ma type b24 i oh = -24 ma S3C2500B electrical data 18- 3 table 18-3. d.c electric characteristics (continued) symbol parameter condition min type max unit v ol low level output voltage v type b1 to b12 i ol = 1 m a ? ? 0.05 type b1 i ol = 1 ma 0.4 type b2 i ol = 2 ma type b4 i ol = 4 ma type b8 i ol = 8 ma type b12 i ol = 12 ma type b16 i ol = 16 ma type b20 i ol = 20 ma type b24 i ol = 24 ma i oz tri-state output leakage current v out = v ss or v dd -10 10 m a i ds quiescent supply current 100 m a i dd maximum operating current v dd = 3.3 v/1.8 v frequency = 133mhz (note) ma c in input capacitance any input bi-directional buffers 4 pf c out output capacitance any output buffer 4 pf note: later, it will be updated. electrical data s3c 2500b 18- 4 18.5 max power consumption condition: 1. S3C2500B es sample 2. smdk2500 evaluation board (rev 1.0) without lcd module. hclkout damping resister (r146) = 48 w . 3. clock mode: async 166mhz/133mhz 4. samsung diagnostic test: all test (remap mode, i-cache on, d-cache on) 5. samsung diagnostic test: idle (remap mode, i-cache on, d-cache) table 18-4. max power consumption voltage temperature max power consumption 3.3 v 95 c 760.2 mw 1.8 v 3.3 v 80 c 740.4 mw 1.8 v 3.3 v 25 c 741.3 mw 1.8 v 3.3 v 0 c 738 mw 1.8 v 3.3 v - 30 c 748.5 mw 1.8 v 3.3 v - 50 c 737.1 mw 1.8 v 3.3 v idle (25 c) 664.2 mw 1.8 v the output can differ under other circumstances. S3C2500B electrical data 18- 5 18.6 ac electrical characteristics table 18-4. operating frequency characteristic min max units core frequency 33 166 mhz system bus frequency 33 133 mhz usb frequency 48 48 mhz table 18-5. clock ac timing specification characteristic min max units internal pll lock time ? 150 m s frequency of operation (xclk) ? 133 mhz xclk cycle time 7.5 ? ns xclk duty cycle 45 55 % frequency of operation (hclko) ? 133 mhz hclko cycle time 7.5 ? ns hclko duty cycle 45 55 % electrical data s3c 2500b 18- 6 table 18-6. ac electrical characteristics for S3C2500B signal name description min max unit tnrcsd rom/sram chip select delay time 1.32 3.43 ns tnrcsh rom/sram chip select hold time 1.17 3.02 ns tnoed rom/sram output enable delay time 0.79 1.93 ns tnoeh rom/sram output enable hold time 0.69 1.7 ns tnsdwed rom/sram write byte enable delay time 1.23 2.82 ns tnsdweh rom/sram write byte enable hold time 1.42 3.28 ns taddrd rom/sram address delay time 1.02 2.39 ns taddrh rom/sram address hold time 0.94 2.24 ns tdatad rom/sram data delay time 1.55 3.79 ns tdatah rom/sram data hold time 1.37 3.18 ns taled rom/sram address latch enable delay time 1.43 3.01 ns taleh rom/sram address latch enable hold time 1.26 3.09 ns tmaddrd rom/sram muxed bus address delay time 1.86 4.42 ns tmaddrh rom/sram muxed bus address hold time 1.09 2.72 ns tnwaitd rom/sram wait signal delay time 1 5.11 ns tnwaith rom/sram wait signalhold time 1 5.11 ns tcc sdram clock cycle time 7.5 7.5 ps tch sdram clock high pulse width 4.1 4.5 ps tcl sdram clock low pulse width 3.4 3.5 ps tcasd sdram column address strobe delay time 2.0 4.7 ps tcash sdram column address strobe hold time 2.0 4.6 ps trasd sdram row address strobe delay time 2.0 4.8 ps trash sdram row address strobe hold time 2.0 4.7 ps tcsd sdram chip select delay time 2.0 4.8 ps tcsd sdram chip select hold time 2.0 4.7 ps twed sdram write enable delay time 1.7 4.0 ps tweh sdram write enable hold time 1.7 3.9 ps twdd sdram write data delay time 2.3 5.3 ps twdh sdram write data hold time 1.6 3.5 ps trdd sdram read data delay time 6.0 7.0 ps trdh sdram read data hold time 6.0 7.0 ps taddrd sdram address delay time 2.2 5.0 ps taddrh sdram address hold time 2.2 4.9 ps tdqmd sdram data input/output mask delay time 2.0 4.9 ps tdqmh sdram data input/output mask hold time 1.8 4.2 ps S3C2500B mechani cal data 19- 1 19 mechanical data 19.1 overview the S3C2500B is available in a 272-pin bga package (272-bga-2727-an). mechanical data s3c 2500b 19- 2 27.00 0.10 24.00 0.10 0.60 0.10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 k j h g f e d c b a n m l 1.17 0.05 0.36(0.56) 0.10 2.13(2.33) 0.20 0.15 max 272-bga-2727-an f 0.38 max 18 19 20 1.27 y w v u 272- f 0.76 0.015 15 16 17 1.27 t r p 27.00 0.10 24.00 0.10 a1 corner a1 corner figure 19-1. 272-bga-2727-an package dimensions |
Price & Availability of S3C2500B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |